// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2024 Rockchip Electronics Co., Ltd. */ /dts-v1/; //#include "rv1106-tb-nofastae-emmc.dtsi" #include "rv1106.dtsi" #include "rv1106-evb-v10.dtsi" #include "rv1106-thunder-boot-emmc.dtsi" / { model = "Luckfox Pico Ultra"; compatible = "rockchip,rv1106g-evb1-v11", "rockchip,rv1106"; chosen { bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip"; }; vcc_1v8: vcc-1v8 { compatible = "regulator-fixed"; regulator-name = "vcc_1v8"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; vcc_3v3: vcc-3v3 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; leds: leds { compatible = "gpio-leds"; work_led: work{ gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "activity"; default-state = "on"; }; }; }; /***************************** audio ********************************/ &i2s0_8ch { #sound-dai-cells = <0>; status = "okay"; }; &acodec { #sound-dai-cells = <0>; pa-ctl-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; status = "okay"; }; /***************************** emmc *******************************/ &emmc { status = "okay"; }; /***************************** csi ********************************/ &csi2_dphy_hw { status = "okay"; }; &csi2_dphy0 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; csi_dphy_input0: endpoint@0 { reg = <0>; remote-endpoint = <&sc3338_out>; data-lanes = <1 2>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; csi_dphy_output: endpoint@0 { reg = <0>; remote-endpoint = <&mipi_csi2_input>; }; }; }; }; &i2c4 { rockchip,amp-shared; status = "okay"; pinctrl-0 = <&i2c4m2_xfer>; sc3338: sc3338@30 { compatible = "smartsens,sc3338"; status = "okay"; reg = <0x30>; clocks = <&cru MCLK_REF_MIPI0>; clock-names = "xvclk"; pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&mipi_refclk_out0>; rockchip,camera-module-index = <0>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "FKO1"; rockchip,camera-module-lens-name = "30IRC-F16"; port { sc3338_out: endpoint { remote-endpoint = <&csi_dphy_input0>; data-lanes = <1 2>; }; }; }; }; &mipi0_csi2 { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; mipi_csi2_input: endpoint@1 { reg = <1>; remote-endpoint = <&csi_dphy_output>; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; mipi_csi2_output: endpoint@0 { reg = <0>; remote-endpoint = <&cif_mipi_in>; }; }; }; }; &rkcif { status = "okay"; }; &rkcif_mipi_lvds { status = "okay"; memory-region-thunderboot = <&rkisp_thunderboot>; //thunderboot pinctrl-names = "default"; pinctrl-0 = <&mipi_pins>; port { /* MIPI CSI-2 endpoint */ cif_mipi_in: endpoint { remote-endpoint = <&mipi_csi2_output>; }; }; }; &rkcif_mipi_lvds_sditf { status = "okay"; port { /* MIPI CSI-2 endpoint */ mipi_lvds_sditf: endpoint { remote-endpoint = <&isp_in>; }; }; }; &rkisp { status = "okay"; }; &rkisp_vir0 { status = "okay"; port@0 { isp_in: endpoint { remote-endpoint = <&mipi_lvds_sditf>; }; }; }; /***************************** ethernet ****************************/ &gmac { status = "okay"; }; /***************************** fiq ********************************/ &fiq_debugger { rockchip,baudrate = <115200>; pinctrl-names = "default"; pinctrl-0 = <&uart2m1_xfer>; }; /***************************** usb ********************************/ &usbdrd_dwc3 { extcon = <&u2phy>; //dr_mode = "peripheral";//for rndis dr_mode = "otg"; //for uvc status = "okay"; }; /***************************** other ******************************/ &mailbox { status = "okay"; }; /********************** thunder-boot ******************************/ &thunder_boot_service { status = "okay"; }; &rkisp_thunderboot { /* reg's offset MUST match with RTOS */ /* * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) * e.g. 2304x1296: 0xf30000 */ reg = <0x00860000 0xf30000>; }; &ramdisk_r { reg = <0x1790000 (40 * 0x00100000)>; }; &ramdisk_c { reg = <0x3f90000 (20 * 0x00100000)>; };