// ----------------------------------------------------------------------------- // 2018-11-16 10:46:46 // ----------------------------------------------------------------------------- // GIT SHA1: a993cbaae4605d2613d18194371b2e50b91a25ff // ----------------------------------------------------------------------------- #define FBUS_DMAC_REG_BASE 0x40000000 #define SBUS_DMAC_REG_BASE 0x50000000 #define I2S_TRX_REG_BASE 0x60000000 #define I2CMST_REG_BASE 0x60000400 #define SPIMST_REG_BASE 0x60000800 #define USB20_REG_BASE 0x70000000 #define SYS_REG_BASE 0xc0000000 #define CSR_ALLON_BASE 0xc0000100 #define TU0_US_REG_BASE 0xc0000200 #define TU1_US_REG_BASE 0xc0000210 #define TU2_US_REG_BASE 0xc0000220 #define TU3_US_REG_BASE 0xc0000230 #define TM0_MS_REG_BASE 0xc0000240 #define TM1_MS_REG_BASE 0xc0000250 #define TM2_MS_REG_BASE 0xc0000260 #define TM3_MS_REG_BASE 0xc0000270 #define MCU_WDT_REG_BASE 0xc0000280 #define SYS_WDT_REG_BASE 0xc0000284 #define PWM_REG_BASE 0xc00002c0 #define IO_REG_BASE 0xc0000500 #define CSR_I2C_SLV_BASE 0xc0000600 #define SD_REG_BASE 0xc0000800 #define SPI_REG_BASE 0xc0000a00 #define CSR_I2C_MST_BASE 0xc0000b00 #define UART_REG_BASE 0xc0000c00 #define DAT_UART_REG_BASE 0xc0000d00 #define FLASH_SPI_REG_BASE 0xc0001000 #define DMA_REG_BASE 0xc0001c00 #define D2_DMA_REG_BASE 0xc0001e00 #define INT_CTRL_REG_BASE 0xc0002000 #define SYS_UTILS_BASE 0xc0003000 #define RTC_MISC_REG_BASE 0xc0004000 #define HCI_REG_BASE 0xc1000000 #define CO_REG_BASE 0xc2000000 #define EFS_REG_BASE 0xc2000100 #define CSR_SPIMAS_BASE 0xc3000000 #define SPIMAS_TX_BUF_BASE 0xc3000100 #define SPIMAS_RX_BUF_BASE 0xc3000200 #define MRX_REG_BASE 0xc6000000 #define AMPDU_REG_BASE 0xc6001000 #define MT_REG_CSR_BASE 0xc6002000 #define TXQ0_MT_Q_REG_CSR_BASE 0xc6002100 #define TXQ1_MT_Q_REG_CSR_BASE 0xc6002200 #define TXQ2_MT_Q_REG_CSR_BASE 0xc6002300 #define TXQ3_MT_Q_REG_CSR_BASE 0xc6002400 #define TXQ4_MT_Q_REG_CSR_BASE 0xc6002500 #define TXQ5_MT_Q_REG_CSR_BASE 0xc6002600 #define MT_RESPFRM_REG_BASE 0xc6003000 #define HIF_INFO_BASE 0xca000000 #define PHY_RATE_INFO_BASE 0xca000200 #define MAC_GLB_SET_BASE 0xca000300 #define BTCX_REG_BASE 0xca000400 #define MIB_REG_BASE 0xca000800 #define WSID_EXT_BASE 0xca010000 #define RF_REG_BASE 0xcb000000 #define CSR_TU_RF_BASE 0xccb0a000 #define CSR_TU_PMU_BASE 0xccb0b000 #define CSR_TU_PHY_BASE 0xccb0e000 #define MB_REG_BASE 0xcd000000 #define ID_MNG_REG_BASE 0xcd010000 #define MMU_REG_BASE 0xcf000000 #define CSR_TEMP_REG_BASE 0xcfff0000 // ----------------------------------------------------------------------------- // bank size // ----------------------------------------------------------------------------- #define FBUS_DMAC_REG_BANK_SIZE 0x000003f8 #define SBUS_DMAC_REG_BANK_SIZE 0x000003f8 #define I2S_TRX_REG_BANK_SIZE 0x000001cc #define I2CMST_REG_BANK_SIZE 0x00000070 #define SPIMST_REG_BANK_SIZE 0x000000f4 #define USB20_REG_BANK_SIZE 0x00008004 #define SYS_REG_BANK_SIZE 0x00000100 #define CSR_ALLON_BANK_SIZE 0x00000044 #define TU0_US_REG_BANK_SIZE 0x0000000c #define TU1_US_REG_BANK_SIZE 0x0000000c #define TU2_US_REG_BANK_SIZE 0x0000000c #define TU3_US_REG_BANK_SIZE 0x0000000c #define TM0_MS_REG_BANK_SIZE 0x0000000c #define TM1_MS_REG_BANK_SIZE 0x0000000c #define TM2_MS_REG_BANK_SIZE 0x0000000c #define TM3_MS_REG_BANK_SIZE 0x0000000c #define MCU_WDT_REG_BANK_SIZE 0x00000004 #define SYS_WDT_REG_BANK_SIZE 0x00000004 #define PWM_REG_BANK_SIZE 0x00000028 #define IO_REG_BANK_SIZE 0x00000040 #define CSR_I2C_SLV_BANK_SIZE 0x00000014 #define SD_REG_BANK_SIZE 0x00000180 #define SPI_REG_BANK_SIZE 0x00000020 #define CSR_I2C_MST_BANK_SIZE 0x00000050 #define UART_REG_BANK_SIZE 0x00000034 #define DAT_UART_REG_BANK_SIZE 0x00000060 #define FLASH_SPI_REG_BANK_SIZE 0x00000034 #define DMA_REG_BANK_SIZE 0x00000014 #define D2_DMA_REG_BANK_SIZE 0x00000014 #define INT_CTRL_REG_BANK_SIZE 0x000000f8 #define SYS_UTILS_BANK_SIZE 0x00000070 #define RTC_MISC_REG_BANK_SIZE 0x00000008 #define HCI_REG_BANK_SIZE 0x0000016c #define CO_REG_BANK_SIZE 0x000000ac #define EFS_REG_BANK_SIZE 0x00000040 #define CSR_SPIMAS_BANK_SIZE 0x00000020 #define SPIMAS_TX_BUF_BANK_SIZE 0x00000020 #define SPIMAS_RX_BUF_BANK_SIZE 0x00000020 #define MRX_REG_BANK_SIZE 0x000001b4 #define AMPDU_REG_BANK_SIZE 0x00000014 #define MT_REG_CSR_BANK_SIZE 0x00000100 #define TXQ0_MT_Q_REG_CSR_BANK_SIZE 0x00000014 #define TXQ1_MT_Q_REG_CSR_BANK_SIZE 0x00000014 #define TXQ2_MT_Q_REG_CSR_BANK_SIZE 0x00000014 #define TXQ3_MT_Q_REG_CSR_BANK_SIZE 0x00000014 #define TXQ4_MT_Q_REG_CSR_BANK_SIZE 0x00000014 #define TXQ5_MT_Q_REG_CSR_BANK_SIZE 0x00000014 #define MT_RESPFRM_REG_BANK_SIZE 0x00000140 #define HIF_INFO_BANK_SIZE 0x0000009c #define PHY_RATE_INFO_BANK_SIZE 0x00000004 #define MAC_GLB_SET_BANK_SIZE 0x00000054 #define BTCX_REG_BANK_SIZE 0x00000014 #define MIB_REG_BANK_SIZE 0x00000480 #define WSID_EXT_BANK_SIZE 0x000001dc #define RF_REG_BANK_SIZE 0x00c0b100 #define CSR_TU_RF_BANK_SIZE 0x00001000 #define CSR_TU_PMU_BANK_SIZE 0x00000100 #define CSR_TU_PHY_BANK_SIZE 0x00001434 #define MB_REG_BANK_SIZE 0x000000a0 #define ID_MNG_REG_BANK_SIZE 0x00000084 #define MMU_REG_BANK_SIZE 0x0000003c #define CSR_TEMP_REG_BANK_SIZE 0x00000034 // FBUS_DMAC_REG #define ADR_FBUS_SAR0 (FBUS_DMAC_REG_BASE+0x00000000) #define ADR_FBUS_DAR0 (FBUS_DMAC_REG_BASE+0x00000008) #define ADR_FBUS_CTL0_1 (FBUS_DMAC_REG_BASE+0x00000018) #define ADR_FBUS_CTL0_2 (FBUS_DMAC_REG_BASE+0x0000001c) #define ADR_FBUS_CFG0_1 (FBUS_DMAC_REG_BASE+0x00000040) #define ADR_FBUS_CFG0_2 (FBUS_DMAC_REG_BASE+0x00000044) #define ADR_FBUS_SAR1 (FBUS_DMAC_REG_BASE+0x00000058) #define ADR_FBUS_DAR1 (FBUS_DMAC_REG_BASE+0x00000060) #define ADR_FBUS_CTL1_1 (FBUS_DMAC_REG_BASE+0x00000070) #define ADR_FBUS_CTL1_2 (FBUS_DMAC_REG_BASE+0x00000074) #define ADR_FBUS_CFG1_1 (FBUS_DMAC_REG_BASE+0x00000098) #define ADR_FBUS_CFG1_2 (FBUS_DMAC_REG_BASE+0x0000009c) #define ADR_FBUS_RAWTR (FBUS_DMAC_REG_BASE+0x000002c0) #define ADR_FBUS_RAWERR (FBUS_DMAC_REG_BASE+0x000002e0) #define ADR_FBUS_STATUSTR (FBUS_DMAC_REG_BASE+0x000002e8) #define ADR_FBUS_STATUSERR (FBUS_DMAC_REG_BASE+0x00000308) #define ADR_FBUS_MASKTR (FBUS_DMAC_REG_BASE+0x00000310) #define ADR_FBUS_MASKERR (FBUS_DMAC_REG_BASE+0x00000330) #define ADR_FBUS_CLRTR (FBUS_DMAC_REG_BASE+0x00000338) #define ADR_FBUS_CLRERR (FBUS_DMAC_REG_BASE+0x00000358) #define ADR_FBUS_COMBINED_INT_STATUS (FBUS_DMAC_REG_BASE+0x00000360) #define ADR_FBUS_SHS_SRC_REQ_CFG (FBUS_DMAC_REG_BASE+0x00000368) #define ADR_FBUS_SHS_DST_REQ_CFG (FBUS_DMAC_REG_BASE+0x00000370) #define ADR_FBUS_SHS_SRC_SREQ_CFG (FBUS_DMAC_REG_BASE+0x00000378) #define ADR_FBUS_SHS_DST_SREQ_CFG (FBUS_DMAC_REG_BASE+0x00000380) #define ADR_FBUS_DMA_EN (FBUS_DMAC_REG_BASE+0x00000398) #define ADR_FBUS_CH_EN (FBUS_DMAC_REG_BASE+0x000003a0) #define ADR_FBUS_DMAC_INFO (FBUS_DMAC_REG_BASE+0x000003f4) // SBUS_DMAC_REG #define ADR_SBUS_SAR0 (SBUS_DMAC_REG_BASE+0x00000000) #define ADR_SBUS_DAR0 (SBUS_DMAC_REG_BASE+0x00000008) #define ADR_SBUS_CTL0_1 (SBUS_DMAC_REG_BASE+0x00000018) #define ADR_SBUS_CTL0_2 (SBUS_DMAC_REG_BASE+0x0000001c) #define ADR_SBUS_CFG0_1 (SBUS_DMAC_REG_BASE+0x00000040) #define ADR_SBUS_CFG0_2 (SBUS_DMAC_REG_BASE+0x00000044) #define ADR_SBUS_SAR1 (SBUS_DMAC_REG_BASE+0x00000058) #define ADR_SBUS_DAR1 (SBUS_DMAC_REG_BASE+0x00000060) #define ADR_SBUS_CTL1_1 (SBUS_DMAC_REG_BASE+0x00000070) #define ADR_SBUS_CTL1_2 (SBUS_DMAC_REG_BASE+0x00000074) #define ADR_SBUS_CFG1_1 (SBUS_DMAC_REG_BASE+0x00000098) #define ADR_SBUS_CFG1_2 (SBUS_DMAC_REG_BASE+0x0000009c) #define ADR_SBUS_RAWTR (SBUS_DMAC_REG_BASE+0x000002c0) #define ADR_SBUS_RAWERR (SBUS_DMAC_REG_BASE+0x000002e0) #define ADR_SBUS_STATUSTR (SBUS_DMAC_REG_BASE+0x000002e8) #define ADR_SBUS_STATUSERR (SBUS_DMAC_REG_BASE+0x00000308) #define ADR_SBUS_MASKTR (SBUS_DMAC_REG_BASE+0x00000310) #define ADR_SBUS_MASKERR (SBUS_DMAC_REG_BASE+0x00000330) #define ADR_SBUS_CLRTR (SBUS_DMAC_REG_BASE+0x00000338) #define ADR_SBUS_CLRERR (SBUS_DMAC_REG_BASE+0x00000358) #define ADR_SBUS_COMBINED_INT_STATUS (SBUS_DMAC_REG_BASE+0x00000360) #define ADR_SBUS_SHS_SRC_REQ_CFG (SBUS_DMAC_REG_BASE+0x00000368) #define ADR_SBUS_SHS_DST_REQ_CFG (SBUS_DMAC_REG_BASE+0x00000370) #define ADR_SBUS_SHS_SRC_SREQ_CFG (SBUS_DMAC_REG_BASE+0x00000378) #define ADR_SBUS_SHS_DST_SREQ_CFG (SBUS_DMAC_REG_BASE+0x00000380) #define ADR_SBUS_DMA_EN (SBUS_DMAC_REG_BASE+0x00000398) #define ADR_SBUS_CH_EN (SBUS_DMAC_REG_BASE+0x000003a0) #define ADR_SBUS_DMAC_INFO (SBUS_DMAC_REG_BASE+0x000003f4) // I2S_TRX_REG #define ADR_I2S_EN (I2S_TRX_REG_BASE+0x00000000) #define ADR_I2S_RX_EN (I2S_TRX_REG_BASE+0x00000004) #define ADR_I2S_TX_EN (I2S_TRX_REG_BASE+0x00000008) #define ADR_I2S_SCLK_SCR_EN (I2S_TRX_REG_BASE+0x0000000c) #define ADR_I2S_WS_DEF (I2S_TRX_REG_BASE+0x00000010) #define ADR_RESET_RX_FIFO (I2S_TRX_REG_BASE+0x00000014) #define ADR_RESET_TX_FIFO (I2S_TRX_REG_BASE+0x00000018) #define ADR_L_TRX_DATA (I2S_TRX_REG_BASE+0x00000020) #define ADR_R_TRX_DATA (I2S_TRX_REG_BASE+0x00000024) #define ADR_I2S_RX_CH_EN (I2S_TRX_REG_BASE+0x00000028) #define ADR_I2S_TX_CH_EN (I2S_TRX_REG_BASE+0x0000002c) #define ADR_I2S_RX_WORD_RES (I2S_TRX_REG_BASE+0x00000030) #define ADR_I2S_TX_WORD_RES (I2S_TRX_REG_BASE+0x00000034) #define ADR_I2S_INTR (I2S_TRX_REG_BASE+0x00000038) #define ADR_I2S_INTR_MASK (I2S_TRX_REG_BASE+0x0000003c) #define ADR_I2S_RXFO (I2S_TRX_REG_BASE+0x00000040) #define ADR_I2S_TXFO (I2S_TRX_REG_BASE+0x00000044) #define ADR_I2S_RX_FIFO_TH (I2S_TRX_REG_BASE+0x00000048) #define ADR_I2S_TX_FIFO_TH (I2S_TRX_REG_BASE+0x0000004c) #define ADR_I2S_RX_FIFO_FLUSH (I2S_TRX_REG_BASE+0x00000050) #define ADR_I2S_TX_FIFO_FLUSH (I2S_TRX_REG_BASE+0x00000054) #define ADR_I2S_RX_DMA (I2S_TRX_REG_BASE+0x000001c0) #define ADR_I2S_TX_DMA (I2S_TRX_REG_BASE+0x000001c8) // I2CMST_REG #define ADR_I2CMST_CFG0 (I2CMST_REG_BASE+0x00000000) #define ADR_I2CMST_TAR (I2CMST_REG_BASE+0x00000004) #define ADR_I2CMST_TRX_CMD_DATA (I2CMST_REG_BASE+0x00000010) #define ADR_I2CMST_SCLK_H_WIDTH (I2CMST_REG_BASE+0x00000014) #define ADR_I2CMST_SCLK_L_WIDTH (I2CMST_REG_BASE+0x00000018) #define ADR_I2CMST_INT (I2CMST_REG_BASE+0x0000002c) #define ADR_I2CMST_INT_MASK (I2CMST_REG_BASE+0x00000030) #define ADR_I2CMST_INT_STA (I2CMST_REG_BASE+0x00000034) #define ADR_I2CMST_RX_FIFO_TH (I2CMST_REG_BASE+0x00000038) #define ADR_I2CMST_TX_FIFO_TH (I2CMST_REG_BASE+0x0000003c) #define ADR_I2CMST_ENABLE (I2CMST_REG_BASE+0x0000006c) // SPIMST_REG #define ADR_SPIMST_CFG0 (SPIMST_REG_BASE+0x00000000) #define ADR_SPIMST_CFG1 (SPIMST_REG_BASE+0x00000004) #define ADR_SPIMST_EN (SPIMST_REG_BASE+0x00000008) #define ADR_SPIMST_CEN (SPIMST_REG_BASE+0x00000010) #define ADR_SPIMST_SCLK_RATE (SPIMST_REG_BASE+0x00000014) #define ADR_SPIMST_TXFIFO_TH (SPIMST_REG_BASE+0x00000018) #define ADR_SPIMST_RXFIFO_TH (SPIMST_REG_BASE+0x0000001c) #define ADR_SPIMST_STATUS (SPIMST_REG_BASE+0x00000028) #define ADR_SPIMST_INT_MASK (SPIMST_REG_BASE+0x0000002c) #define ADR_SPIMST_INT (SPIMST_REG_BASE+0x00000030) #define ADR_SPIMST_TRX_DATA (SPIMST_REG_BASE+0x00000060) #define ADR_SPIMST_RX_SAMPLE_DLY (SPIMST_REG_BASE+0x000000f0) // USB20_REG #define ADR_APPLICATION_CONTROL_REG (USB20_REG_BASE+0x00004000) #define ADR_MEMORY_DESTINATION_ADDRESS_REG (USB20_REG_BASE+0x00004004) #define ADR_USB_AND_DEVICE_CONTROL_REG (USB20_REG_BASE+0x00004008) #define ADR_HANDSHAKE_AND_HALT_BIT_REG (USB20_REG_BASE+0x00004010) #define ADR_SETUP_TRANSACTION_REG_0 (USB20_REG_BASE+0x00004018) #define ADR_SETUP_TRANSACTION_REG_1 (USB20_REG_BASE+0x0000401c) #define ADR_TXBUFFER_CONTROL_REG_0 (USB20_REG_BASE+0x00004030) #define ADR_TXBUFFER_CONTROL_REG_1 (USB20_REG_BASE+0x00004034) #define ADR_TXBUFFER_CONTROL_REG_2 (USB20_REG_BASE+0x00004038) #define ADR_TXBUFFER_CONTROL_REG_3 (USB20_REG_BASE+0x0000403c) #define ADR_INTERRUPT_ENABLE_REG (USB20_REG_BASE+0x00004050) #define ADR_INTERRUPT_DISABLE_REG (USB20_REG_BASE+0x00004054) #define ADR_INTERRUPT_STATUS_REG (USB20_REG_BASE+0x00004058) #define ADR_PHYSICAL_INTERFACE_REG_0 (USB20_REG_BASE+0x00004074) #define ADR_ENDPOINT_DESCRIPTOR_REG_0 (USB20_REG_BASE+0x00004080) #define ADR_ENDPOINT_DESCRIPTOR_REG_1 (USB20_REG_BASE+0x00004084) #define ADR_ENDPOINT_DESCRIPTOR_REG_2 (USB20_REG_BASE+0x00004088) #define ADR_ENDPOINT_DESCRIPTOR_REG_3 (USB20_REG_BASE+0x0000408c) #define ADR_ENDPOINT_DESCRIPTOR_REG_4 (USB20_REG_BASE+0x00004090) #define ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_0 (USB20_REG_BASE+0x00004180) #define ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1 (USB20_REG_BASE+0x00004184) #define ADR_USB_EP4_AGGREGATION_REG (USB20_REG_BASE+0x00004188) #define ADR_USB_ACC_CTRL_REG_0 (USB20_REG_BASE+0x000041ac) #define ADR_USB_ACC_EP2_DATA_REG_0 (USB20_REG_BASE+0x000041b0) #define ADR_USB_ACC_EP2_DATA_REG_1 (USB20_REG_BASE+0x000041b4) #define ADR_USB_ACC_CTRL_REG_1 (USB20_REG_BASE+0x000041b8) #define ADR_USB_ACC_STATUS_REG (USB20_REG_BASE+0x000041bc) #define ADR_EP1_DATA_REG_0 (USB20_REG_BASE+0x000041c0) #define ADR_EP1_DATA_REG_1 (USB20_REG_BASE+0x000041c4) #define ADR_EP1_DATA_REG_2 (USB20_REG_BASE+0x000041c8) #define ADR_USB_CONTROLLER_LOW_POWER_STATUS_REG (USB20_REG_BASE+0x000041cc) #define ADR_USB_CONTROLLER_CTRL_STATUS_REG_0 (USB20_REG_BASE+0x000041d0) #define ADR_USB_CONTROLLER_CTRL_STATUS_REG_1 (USB20_REG_BASE+0x000041d4) #define ADR_USB_CONTROLLER_CTRL_STATUS_REG_2 (USB20_REG_BASE+0x000041d8) #define ADR_USB_CONTROLLER_CTRL_STATUS_REG_3 (USB20_REG_BASE+0x000041dc) #define ADR_USB_PHY_CTRL_STATUS_REG_0 (USB20_REG_BASE+0x000041e0) #define ADR_USB_PHY_CTRL_STATUS_REG_1 (USB20_REG_BASE+0x000041e4) #define ADR_USB_PHY_CTRL_STATUS_REG_2 (USB20_REG_BASE+0x000041e8) #define ADR_USB_PHY_CTRL_STATUS_REG_3 (USB20_REG_BASE+0x000041ec) #define ADR_OTG_LINK_WRITE_REG (USB20_REG_BASE+0x00008000) // SYS_REG #define ADR_BRG_SW_RST (SYS_REG_BASE+0x00000000) #define ADR_BOOT (SYS_REG_BASE+0x00000004) #define ADR_CHIP_ID_0 (SYS_REG_BASE+0x00000008) #define ADR_CHIP_ID_1 (SYS_REG_BASE+0x0000000c) #define ADR_CHIP_ID_2 (SYS_REG_BASE+0x00000010) #define ADR_CHIP_ID_3 (SYS_REG_BASE+0x00000014) #define ADR_CLOCK_SELECTION (SYS_REG_BASE+0x00000018) #define ADR_PLATFORM_CLOCK_ENABLE (SYS_REG_BASE+0x0000001c) #define ADR_SYS_CSR_CLOCK_ENABLE (SYS_REG_BASE+0x00000020) #define ADR_BOOTSTRAP_SAMPLE (SYS_REG_BASE+0x00000024) #define ADR_N10_DBG1 (SYS_REG_BASE+0x00000028) #define ADR_N10_DBG2 (SYS_REG_BASE+0x0000002c) #define ADR_ROPMUSTATE (SYS_REG_BASE+0x00000030) #define ADR_ROM_READ_PROT (SYS_REG_BASE+0x00000034) #define ADR_GPIO_IQ_LOG_STOP (SYS_REG_BASE+0x00000038) #define ADR_TB_ADR_SEL (SYS_REG_BASE+0x00000044) #define ADR_TB_RDATA (SYS_REG_BASE+0x00000048) #define ADR_UART_W2B (SYS_REG_BASE+0x0000004c) #define ADR_SYSCTRL_COMMAND (SYS_REG_BASE+0x00000054) #define ADR_FBUS_CLK_SEL (SYS_REG_BASE+0x00000058) #define ADR_SYSCTRL_STATUS (SYS_REG_BASE+0x0000005c) #define ADR_I2SMAS_CFG (SYS_REG_BASE+0x0000006c) #define ADR_HBUSREQ_LOCK (SYS_REG_BASE+0x00000090) #define ADR_HBURST_LOCK (SYS_REG_BASE+0x00000094) #define ADR_FENCE_CTRL (SYS_REG_BASE+0x00000098) #define ADR_FENCE_STATUS (SYS_REG_BASE+0x0000009c) #define ADR_POWER_SW_INFO (SYS_REG_BASE+0x000000a0) #define ADR_VIAROM_EMA (SYS_REG_BASE+0x000000a4) #define ADR_TEST_MODE (SYS_REG_BASE+0x000000b0) #define ADR_MANUAL_RESET_N (SYS_REG_BASE+0x000000b4) #define ADR_DEBUG_FIRMWARE_EVENT_FLAG (SYS_REG_BASE+0x000000b8) #define ADR_DEBUG_HOST_EVENT_FLAG (SYS_REG_BASE+0x000000bc) #define ADR_CHIP_INFO_ID_0 (SYS_REG_BASE+0x000000c0) #define ADR_CHIP_INFO_ID_1 (SYS_REG_BASE+0x000000c4) #define ADR_CHIP_TYPE_VER (SYS_REG_BASE+0x000000c8) #define ADR_CHIP_DATE_YYYYMMDD (SYS_REG_BASE+0x000000cc) #define ADR_CHIP_DATE_00HHMMSS (SYS_REG_BASE+0x000000d0) #define ADR_CHIP_GITSHA_0 (SYS_REG_BASE+0x000000d4) #define ADR_CHIP_GITSHA_1 (SYS_REG_BASE+0x000000d8) #define ADR_CHIP_GITSHA_2 (SYS_REG_BASE+0x000000dc) #define ADR_CHIP_GITSHA_3 (SYS_REG_BASE+0x000000e0) #define ADR_CHIP_GITSHA_4 (SYS_REG_BASE+0x000000e4) #define ADR_N10CFG_DEF_IVB (SYS_REG_BASE+0x000000e8) #define ADR_N10CFG_SETTING (SYS_REG_BASE+0x000000ec) #define ADR_USB20_HOST_SEL (SYS_REG_BASE+0x000000f0) #define ADR_CHIP_INFO_FPGATAG (SYS_REG_BASE+0x000000f4) #define ADR_PMU_MODE_TRAN_INT (SYS_REG_BASE+0x000000f8) #define ADR_DEBUG_SIM_FINISH (SYS_REG_BASE+0x000000fc) // CSR_ALLON #define ADR_ALWAYS_ON_CFG00 (CSR_ALLON_BASE+0x00000000) #define ADR_SDIO_RESET_WAKE_CFG (CSR_ALLON_BASE+0x00000004) #define ADR_BOOT_INFO (CSR_ALLON_BASE+0x00000008) #define ADR_SPARE_UART_INFO (CSR_ALLON_BASE+0x0000000c) #define ADR_POWER_ON_OFF_CTRL (CSR_ALLON_BASE+0x00000010) #define ADR_HOST_WAKE_WIFI_CTRL (CSR_ALLON_BASE+0x00000014) #define ADR_PRESCALER_USTIMER (CSR_ALLON_BASE+0x00000018) #define ADR_DESIGN_FOR_TEST_ASSERTION (CSR_ALLON_BASE+0x0000001c) #define ADR_WAKE_PMU_ENABLE (CSR_ALLON_BASE+0x00000020) #define ADR_SRAMCFG_SETTING (CSR_ALLON_BASE+0x00000028) #define ADR_ROM_PATCH00_0 (CSR_ALLON_BASE+0x00000030) #define ADR_ROM_PATCH00_1 (CSR_ALLON_BASE+0x00000034) #define ADR_ROM_PATCH01_0 (CSR_ALLON_BASE+0x00000038) #define ADR_ROM_PATCH01_1 (CSR_ALLON_BASE+0x0000003c) #define ADR_DESIGN_FOR_TEST (CSR_ALLON_BASE+0x00000040) // TU0_US_REG #define ADR_TU0_MICROSECOND_TIMER (TU0_US_REG_BASE+0x00000000) #define ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE (TU0_US_REG_BASE+0x00000004) #define ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE (TU0_US_REG_BASE+0x00000008) // TU1_US_REG #define ADR_TU1_MICROSECOND_TIMER (TU1_US_REG_BASE+0x00000000) #define ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE (TU1_US_REG_BASE+0x00000004) #define ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE (TU1_US_REG_BASE+0x00000008) // TU2_US_REG #define ADR_TU2_MICROSECOND_TIMER (TU2_US_REG_BASE+0x00000000) #define ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE (TU2_US_REG_BASE+0x00000004) #define ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE (TU2_US_REG_BASE+0x00000008) // TU3_US_REG #define ADR_TU3_MICROSECOND_TIMER (TU3_US_REG_BASE+0x00000000) #define ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE (TU3_US_REG_BASE+0x00000004) #define ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE (TU3_US_REG_BASE+0x00000008) // TM0_MS_REG #define ADR_TM0_MILLISECOND_TIMER (TM0_MS_REG_BASE+0x00000000) #define ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE (TM0_MS_REG_BASE+0x00000004) #define ADR_TM0_MILLISECOND_TIMER_PRESCALE (TM0_MS_REG_BASE+0x00000008) // TM1_MS_REG #define ADR_TM1_MILLISECOND_TIMER (TM1_MS_REG_BASE+0x00000000) #define ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE (TM1_MS_REG_BASE+0x00000004) #define ADR_TM1_MILLISECOND_TIMER_PRESCALE (TM1_MS_REG_BASE+0x00000008) // TM2_MS_REG #define ADR_TM2_MILLISECOND_TIMER (TM2_MS_REG_BASE+0x00000000) #define ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE (TM2_MS_REG_BASE+0x00000004) #define ADR_TM2_MILLISECOND_TIMER_PRESCALE (TM2_MS_REG_BASE+0x00000008) // TM3_MS_REG #define ADR_TM3_MILLISECOND_TIMER (TM3_MS_REG_BASE+0x00000000) #define ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE (TM3_MS_REG_BASE+0x00000004) #define ADR_TM3_MILLISECOND_TIMER_PRESCALE (TM3_MS_REG_BASE+0x00000008) // MCU_WDT_REG #define ADR_MCU_WDOG_REG (MCU_WDT_REG_BASE+0x00000000) // SYS_WDT_REG #define ADR_SYS_WDOG_REG (SYS_WDT_REG_BASE+0x00000000) // PWM_REG #define ADR_PWM_0_CTRL (PWM_REG_BASE+0x00000000) #define ADR_PWM_0_SET (PWM_REG_BASE+0x00000004) #define ADR_PWM_1_CTRL (PWM_REG_BASE+0x00000008) #define ADR_PWM_1_SET (PWM_REG_BASE+0x0000000c) #define ADR_PWM_2_CTRL (PWM_REG_BASE+0x00000010) #define ADR_PWM_2_SET (PWM_REG_BASE+0x00000014) #define ADR_PWM_3_CTRL (PWM_REG_BASE+0x00000018) #define ADR_PWM_3_SET (PWM_REG_BASE+0x0000001c) #define ADR_PWM_4_CTRL (PWM_REG_BASE+0x00000020) #define ADR_PWM_4_SET (PWM_REG_BASE+0x00000024) // IO_REG #define ADR_MANUAL_IO (IO_REG_BASE+0x00000000) #define ADR_MANUAL_PU (IO_REG_BASE+0x00000004) #define ADR_MANUAL_PD (IO_REG_BASE+0x00000008) #define ADR_MANUAL_DS (IO_REG_BASE+0x0000000c) #define ADR_IO_PO (IO_REG_BASE+0x00000010) #define ADR_IO_PI (IO_REG_BASE+0x00000014) #define ADR_IO_PIE (IO_REG_BASE+0x00000018) #define ADR_IO_POEN (IO_REG_BASE+0x0000001c) #define ADR_IO_PUE (IO_REG_BASE+0x00000020) #define ADR_IO_PDE (IO_REG_BASE+0x00000024) #define ADR_IO_DS (IO_REG_BASE+0x00000028) #define ADR_IO_FUNC_SEL (IO_REG_BASE+0x0000002c) #define ADR_INT_THRU_GPIO (IO_REG_BASE+0x00000030) #define ADR_BIST_CTRL (IO_REG_BASE+0x00000034) #define ADR_BIST_CTRL1 (IO_REG_BASE+0x00000038) #define ADR_BIST_CTRL2 (IO_REG_BASE+0x0000003c) // CSR_I2C_SLV #define ADR_I2CS_ID_ADDR (CSR_I2C_SLV_BASE+0x00000000) #define ADR_I2CS_STATUS (CSR_I2C_SLV_BASE+0x00000004) #define ADR_I2CS_TIME_CNT (CSR_I2C_SLV_BASE+0x00000008) #define ADR_I2CS_STATE (CSR_I2C_SLV_BASE+0x0000000c) #define ADR_I2CS_CTRL (CSR_I2C_SLV_BASE+0x00000010) // SD_REG #define ADR_IO_PORT_REG (SD_REG_BASE+0x00000000) #define ADR_INT_MASK_REG (SD_REG_BASE+0x00000004) #define ADR_INT_STATUS_REG (SD_REG_BASE+0x00000008) #define ADR_FN1_STATUS_REG (SD_REG_BASE+0x0000000c) #define ADR_CARD_RCA_REG (SD_REG_BASE+0x00000020) #define ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG (SD_REG_BASE+0x00000040) #define ADR_SDIO_CARD_STATUS_REG (SD_REG_BASE+0x00000050) #define ADR_R5_RESP_FLAG_OUT_TIMING (SD_REG_BASE+0x00000054) #define ADR_SDIO_DELAY_CHAIN_0 (SD_REG_BASE+0x00000058) #define ADR_SDIO_DELAY_CHAIN_1 (SD_REG_BASE+0x0000005c) #define ADR_FN1_DMA_START_ADDR_REG (SD_REG_BASE+0x00000060) #define ADR_FN1_INT_CTRL_RESET (SD_REG_BASE+0x00000064) #define ADR_MCU_NOTIFY_HOST_EVENT (SD_REG_BASE+0x00000068) #define ADR_FN1_DMA_RD_START_ADDR_REG (SD_REG_BASE+0x0000006c) #define ADR_CCCR_00H_REG (SD_REG_BASE+0x000000c0) #define ADR_CCCR_04H_REG (SD_REG_BASE+0x000000c4) #define ADR_CCCR_08H_REG (SD_REG_BASE+0x000000c8) #define ADR_CCCR_14H_REG (SD_REG_BASE+0x000000cc) #define ADR_CCCR_13H_REG (SD_REG_BASE+0x000000d0) #define ADR_FBR_100H_REG (SD_REG_BASE+0x000000e0) #define ADR_FBR_109H_REG (SD_REG_BASE+0x000000e8) #define ADR_F0_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000100) #define ADR_F0_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000104) #define ADR_F0_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000108) #define ADR_F0_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000010c) #define ADR_F0_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000110) #define ADR_F0_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000114) #define ADR_F0_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000118) #define ADR_F0_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000011c) #define ADR_F0_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000120) #define ADR_F0_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000124) #define ADR_F0_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000128) #define ADR_F0_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000012c) #define ADR_F0_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000130) #define ADR_F0_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000134) #define ADR_F0_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000138) #define ADR_F0_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000013c) #define ADR_F1_CIS_CONTENT_REG_0 (SD_REG_BASE+0x00000140) #define ADR_F1_CIS_CONTENT_REG_1 (SD_REG_BASE+0x00000144) #define ADR_F1_CIS_CONTENT_REG_2 (SD_REG_BASE+0x00000148) #define ADR_F1_CIS_CONTENT_REG_3 (SD_REG_BASE+0x0000014c) #define ADR_F1_CIS_CONTENT_REG_4 (SD_REG_BASE+0x00000150) #define ADR_F1_CIS_CONTENT_REG_5 (SD_REG_BASE+0x00000154) #define ADR_F1_CIS_CONTENT_REG_6 (SD_REG_BASE+0x00000158) #define ADR_F1_CIS_CONTENT_REG_7 (SD_REG_BASE+0x0000015c) #define ADR_F1_CIS_CONTENT_REG_8 (SD_REG_BASE+0x00000160) #define ADR_F1_CIS_CONTENT_REG_9 (SD_REG_BASE+0x00000164) #define ADR_F1_CIS_CONTENT_REG_10 (SD_REG_BASE+0x00000168) #define ADR_F1_CIS_CONTENT_REG_11 (SD_REG_BASE+0x0000016c) #define ADR_F1_CIS_CONTENT_REG_12 (SD_REG_BASE+0x00000170) #define ADR_F1_CIS_CONTENT_REG_13 (SD_REG_BASE+0x00000174) #define ADR_F1_CIS_CONTENT_REG_14 (SD_REG_BASE+0x00000178) #define ADR_F1_CIS_CONTENT_REG_15 (SD_REG_BASE+0x0000017c) // SPI_REG #define ADR_SPI_MODE (SPI_REG_BASE+0x00000000) #define ADR_TX_SEG (SPI_REG_BASE+0x00000010) #define ADR_SPI_TO_PHY_PARAM1 (SPI_REG_BASE+0x00000018) #define ADR_SPI_TO_PHY_PARAM2 (SPI_REG_BASE+0x0000001c) // CSR_I2C_MST #define ADR_TWIM_EN (CSR_I2C_MST_BASE+0x00000000) #define ADR_TWIM_STATUS_SETTING (CSR_I2C_MST_BASE+0x00000004) #define ADR_TWIM_INTERRUPT_EN (CSR_I2C_MST_BASE+0x00000008) #define ADR_TWIM_INTERRUPT (CSR_I2C_MST_BASE+0x0000000c) #define ADR_TWIM_INTERRUPT_STATUS (CSR_I2C_MST_BASE+0x00000010) #define ADR_TWIM_STATUS_RECORD_0 (CSR_I2C_MST_BASE+0x00000014) #define ADR_TWIM_STATUS_RECORD_1 (CSR_I2C_MST_BASE+0x00000018) #define ADR_TWIM_DEV_A (CSR_I2C_MST_BASE+0x0000001c) #define ADR_TWIM_TXD_DATA (CSR_I2C_MST_BASE+0x00000020) #define ADR_TWIM_RXD_DATA (CSR_I2C_MST_BASE+0x00000024) #define ADR_TWIM_PSCL (CSR_I2C_MST_BASE+0x00000028) #define ADR_TWIM_TRANS_PSDA (CSR_I2C_MST_BASE+0x0000002c) #define ADR_TWIM_DELAY_ACK (CSR_I2C_MST_BASE+0x00000030) #define ADR_I2CM_EN (CSR_I2C_MST_BASE+0x00000034) #define ADR_I2CM_DEV_A (CSR_I2C_MST_BASE+0x00000038) #define ADR_I2CM_LEN (CSR_I2C_MST_BASE+0x0000003c) #define ADR_I2CM_WDAT (CSR_I2C_MST_BASE+0x00000040) #define ADR_I2CM_RDAT (CSR_I2C_MST_BASE+0x00000044) #define ADR_I2CM_EN_2 (CSR_I2C_MST_BASE+0x00000048) #define ADR_I2CM_START_STOP_PERIOD (CSR_I2C_MST_BASE+0x0000004c) // UART_REG #define ADR_UART_DATA (UART_REG_BASE+0x00000000) #define ADR_UART_IER (UART_REG_BASE+0x00000004) #define ADR_UART_FCR (UART_REG_BASE+0x00000008) #define ADR_UART_LCR (UART_REG_BASE+0x0000000c) #define ADR_UART_MCR (UART_REG_BASE+0x00000010) #define ADR_UART_LSR (UART_REG_BASE+0x00000014) #define ADR_UART_MSR (UART_REG_BASE+0x00000018) #define ADR_UART_SPR (UART_REG_BASE+0x0000001c) #define ADR_UART_RTHR (UART_REG_BASE+0x00000020) #define ADR_UART_ISR (UART_REG_BASE+0x00000024) #define ADR_UART_TTHR (UART_REG_BASE+0x00000028) #define ADR_UART_INT_MAP (UART_REG_BASE+0x0000002c) #define ADR_UART_POINTER (UART_REG_BASE+0x00000030) // DAT_UART_REG #define ADR_HSUART_TRX_CHAR (DAT_UART_REG_BASE+0x00000000) #define ADR_HSUART_INTRRUPT_ENABLE (DAT_UART_REG_BASE+0x00000004) #define ADR_HSUART_FIFO_CTRL (DAT_UART_REG_BASE+0x00000008) #define ADR_HSUART_LINE_CTRL (DAT_UART_REG_BASE+0x0000000c) #define ADR_HSUART_MODEM_CTRL (DAT_UART_REG_BASE+0x00000010) #define ADR_HSUART_LINE_STATUS (DAT_UART_REG_BASE+0x00000014) #define ADR_HSUART_MODEM_STATUS (DAT_UART_REG_BASE+0x00000018) #define ADR_HSUART_SCRATCH_BOARD (DAT_UART_REG_BASE+0x0000001c) #define ADR_HSUART_FIFO_THRESHOLD (DAT_UART_REG_BASE+0x00000020) #define ADR_HSUART_INTERRUPT_STATUS (DAT_UART_REG_BASE+0x00000024) #define ADR_HSUART_DIV_FRAC (DAT_UART_REG_BASE+0x00000028) #define ADR_HSUART_EXPANSION_INTERRUPT_STATUS (DAT_UART_REG_BASE+0x0000002c) #define ADR_HSUART_DMA_RX_STR_ADDR (DAT_UART_REG_BASE+0x00000040) #define ADR_HSUART_DMA_RX_END_ADDR (DAT_UART_REG_BASE+0x00000044) #define ADR_HSUART_DMA_RX_WPT (DAT_UART_REG_BASE+0x00000048) #define ADR_HSUART_DMA_RX_RPT (DAT_UART_REG_BASE+0x0000004c) #define ADR_HSUART_DMA_TX_STR_ADDR (DAT_UART_REG_BASE+0x00000050) #define ADR_HSUART_DMA_TX_END_ADDR (DAT_UART_REG_BASE+0x00000054) #define ADR_HSUART_DMA_TX_WPT (DAT_UART_REG_BASE+0x00000058) #define ADR_HSUART_DMA_TX_RPT (DAT_UART_REG_BASE+0x0000005c) // FLASH_SPI_REG #define ADR_MANUAL_MODE_TX_ADDR (FLASH_SPI_REG_BASE+0x00000000) #define ADR_MANUAL_MODE_RX_ADDR (FLASH_SPI_REG_BASE+0x00000004) #define ADR_SPI_PARAM (FLASH_SPI_REG_BASE+0x00000008) #define ADR_SPI_PARAM2 (FLASH_SPI_REG_BASE+0x0000000c) #define ADR_SPI_TX_LEN (FLASH_SPI_REG_BASE+0x00000010) #define ADR_SPI_RX_LEN (FLASH_SPI_REG_BASE+0x00000014) #define ADR_CMD_SET (FLASH_SPI_REG_BASE+0x00000018) #define ADR_CMD_SET_1 (FLASH_SPI_REG_BASE+0x0000001c) #define ADR_FLASH_IO0_DLY (FLASH_SPI_REG_BASE+0x00000020) #define ADR_FLASH_IO1_DLY (FLASH_SPI_REG_BASE+0x00000024) #define ADR_INS_SPACE_START_ADDR (FLASH_SPI_REG_BASE+0x00000028) #define ADR_INS_SPACE_END_ADDR (FLASH_SPI_REG_BASE+0x0000002c) #define ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR (FLASH_SPI_REG_BASE+0x00000030) // DMA_REG #define ADR_DMA_ADR_SRC (DMA_REG_BASE+0x00000000) #define ADR_DMA_ADR_DST (DMA_REG_BASE+0x00000004) #define ADR_DMA_CTRL (DMA_REG_BASE+0x00000008) #define ADR_DMA_INT (DMA_REG_BASE+0x0000000c) #define ADR_DMA_FILL_CONST (DMA_REG_BASE+0x00000010) // D2_DMA_REG #define ADR_D2_DMA_ADR_SRC (D2_DMA_REG_BASE+0x00000000) #define ADR_D2_DMA_ADR_DST (D2_DMA_REG_BASE+0x00000004) #define ADR_D2_DMA_CTRL (D2_DMA_REG_BASE+0x00000008) #define ADR_D2_DMA_INT (D2_DMA_REG_BASE+0x0000000c) #define ADR_D2_DMA_FILL_CONST (D2_DMA_REG_BASE+0x00000010) // INT_CTRL_REG #define ADR_MASK_TYPHOST_INT_MAP_02 (INT_CTRL_REG_BASE+0x00000068) #define ADR_RAW_TYPHOST_INT_MAP_02 (INT_CTRL_REG_BASE+0x0000006c) #define ADR_POSTMASK_TYPHOST_INT_MAP_02 (INT_CTRL_REG_BASE+0x00000070) #define ADR_MASK_TYPHOST_INT_MAP_15 (INT_CTRL_REG_BASE+0x00000074) #define ADR_RAW_TYPHOST_INT_MAP_15 (INT_CTRL_REG_BASE+0x00000078) #define ADR_POSTMASK_TYPHOST_INT_MAP_15 (INT_CTRL_REG_BASE+0x0000007c) #define ADR_MASK_TYPHOST_INT_MAP_31 (INT_CTRL_REG_BASE+0x00000080) #define ADR_RAW_TYPHOST_INT_MAP_31 (INT_CTRL_REG_BASE+0x00000084) #define ADR_POSTMASK_TYPHOST_INT_MAP_31 (INT_CTRL_REG_BASE+0x00000088) #define ADR_MASK_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x0000008c) #define ADR_RAW_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x00000090) #define ADR_POSTMASK_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x00000094) #define ADR_SUMMARY_TYPHOST_INT_MAP (INT_CTRL_REG_BASE+0x00000098) #define ADR_MASK_TYPMCU_INT_MAP_02 (INT_CTRL_REG_BASE+0x0000009c) #define ADR_RAW_TYPMCU_INT_MAP_02 (INT_CTRL_REG_BASE+0x000000a0) #define ADR_POSTMASK_TYPMCU_INT_MAP_02 (INT_CTRL_REG_BASE+0x000000a4) #define ADR_MASK_TYPMCU_INT_MAP_15 (INT_CTRL_REG_BASE+0x000000a8) #define ADR_RAW_TYPMCU_INT_MAP_15 (INT_CTRL_REG_BASE+0x000000ac) #define ADR_POSTMASK_TYPMCU_INT_MAP_15 (INT_CTRL_REG_BASE+0x000000b0) #define ADR_MASK_TYPMCU_INT_MAP_31 (INT_CTRL_REG_BASE+0x000000b4) #define ADR_RAW_TYPMCU_INT_MAP_31 (INT_CTRL_REG_BASE+0x000000b8) #define ADR_POSTMASK_TYPMCU_INT_MAP_31 (INT_CTRL_REG_BASE+0x000000bc) #define ADR_MASK_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000c0) #define ADR_RAW_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000c4) #define ADR_POSTMASK_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000c8) #define ADR_SUMMARY_TYPMCU_INT_MAP (INT_CTRL_REG_BASE+0x000000cc) #define ADR_GPIO_INTERRUPT_BANK_00_TO_07 (INT_CTRL_REG_BASE+0x000000d0) #define ADR_GPIO_INTERRUPT_BANK_08_TO_15 (INT_CTRL_REG_BASE+0x000000d4) #define ADR_GPIO_INTERRUPT_BANK_16_TO_22 (INT_CTRL_REG_BASE+0x000000d8) #define ADR_GPIO_INTERRUPT_MODE_00_TO_07 (INT_CTRL_REG_BASE+0x000000dc) #define ADR_GPIO_INTERRUPT_MODE_08_TO_15 (INT_CTRL_REG_BASE+0x000000e0) #define ADR_GPIO_INTERRUPT_MODE_16_TO_22 (INT_CTRL_REG_BASE+0x000000e4) #define ADR_IPC_INTERRUPT (INT_CTRL_REG_BASE+0x000000e8) #define ADR_CLR_INT_STS2 (INT_CTRL_REG_BASE+0x000000ec) #define ADR_CLR_INT_STS1 (INT_CTRL_REG_BASE+0x000000f0) #define ADR_CLR_INT_STS0 (INT_CTRL_REG_BASE+0x000000f4) // SYS_UTILS #define ADR_ROM_PATCH02_0 (SYS_UTILS_BASE+0x00000000) #define ADR_ROM_PATCH02_1 (SYS_UTILS_BASE+0x00000004) #define ADR_ROM_PATCH03_0 (SYS_UTILS_BASE+0x00000008) #define ADR_ROM_PATCH03_1 (SYS_UTILS_BASE+0x0000000c) #define ADR_ROM_PATCH04_0 (SYS_UTILS_BASE+0x00000010) #define ADR_ROM_PATCH04_1 (SYS_UTILS_BASE+0x00000014) #define ADR_ROM_PATCH05_0 (SYS_UTILS_BASE+0x00000018) #define ADR_ROM_PATCH05_1 (SYS_UTILS_BASE+0x0000001c) #define ADR_ROM_PATCH06_0 (SYS_UTILS_BASE+0x00000020) #define ADR_ROM_PATCH06_1 (SYS_UTILS_BASE+0x00000024) #define ADR_ROM_PATCH07_0 (SYS_UTILS_BASE+0x00000028) #define ADR_ROM_PATCH07_1 (SYS_UTILS_BASE+0x0000002c) #define ADR_ROM_PATCH08_0 (SYS_UTILS_BASE+0x00000030) #define ADR_ROM_PATCH08_1 (SYS_UTILS_BASE+0x00000034) #define ADR_ROM_PATCH09_0 (SYS_UTILS_BASE+0x00000038) #define ADR_ROM_PATCH09_1 (SYS_UTILS_BASE+0x0000003c) #define ADR_ROM_PATCH10_0 (SYS_UTILS_BASE+0x00000040) #define ADR_ROM_PATCH10_1 (SYS_UTILS_BASE+0x00000044) #define ADR_ROM_PATCH11_0 (SYS_UTILS_BASE+0x00000048) #define ADR_ROM_PATCH11_1 (SYS_UTILS_BASE+0x0000004c) #define ADR_ROM_PATCH12_0 (SYS_UTILS_BASE+0x00000050) #define ADR_ROM_PATCH12_1 (SYS_UTILS_BASE+0x00000054) #define ADR_ROM_PATCH13_0 (SYS_UTILS_BASE+0x00000058) #define ADR_ROM_PATCH13_1 (SYS_UTILS_BASE+0x0000005c) #define ADR_ROM_PATCH14_0 (SYS_UTILS_BASE+0x00000060) #define ADR_ROM_PATCH14_1 (SYS_UTILS_BASE+0x00000064) #define ADR_ROM_PATCH15_0 (SYS_UTILS_BASE+0x00000068) #define ADR_ROM_PATCH15_1 (SYS_UTILS_BASE+0x0000006c) // RTC_MISC_REG #define ADR_BROWNOUT_INT (RTC_MISC_REG_BASE+0x00000000) #define ADR_BROWNOUT_SETUP (RTC_MISC_REG_BASE+0x00000004) // HCI_REG #define ADR_CONTROL (HCI_REG_BASE+0x00000000) #define ADR_HCI_TRX_MODE (HCI_REG_BASE+0x00000004) #define ADR_TX_FLOW_0 (HCI_REG_BASE+0x00000008) #define ADR_TX_FLOW_1 (HCI_REG_BASE+0x0000000c) #define ADR_REMAINING_RX_PACKET_LENGTH (HCI_REG_BASE+0x00000010) #define ADR_RX_PACKET_LENGTH_STATUS (HCI_REG_BASE+0x00000014) #define ADR_THRESHOLD (HCI_REG_BASE+0x00000018) #define ADR_TX_ERROR_RECEOVERY (HCI_REG_BASE+0x0000001c) #define ADR_TXFID_INCREASE (HCI_REG_BASE+0x00000020) #define ADR_GLOBAL_SEQUENCE (HCI_REG_BASE+0x00000028) #define ADR_HCI_REG_0X2C (HCI_REG_BASE+0x0000002c) #define ADR_HCI_TX_RX_INFO_SIZE (HCI_REG_BASE+0x00000030) #define ADR_HCI_TX_INFO_CLEAR (HCI_REG_BASE+0x00000034) #define ADR_HCI_TO_PKTBUF_SETTING (HCI_REG_BASE+0x00000038) #define ADR_HCI_MANUAL_ALLOC (HCI_REG_BASE+0x00000040) #define ADR_HCI_MANUAL_ALLOC_ACTION (HCI_REG_BASE+0x00000044) #define ADR_HCI_MANUAL_ALLOC_STATUS (HCI_REG_BASE+0x00000048) #define ADR_TX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000050) #define ADR_TX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000054) #define ADR_RX_ETHER_TYPE_0 (HCI_REG_BASE+0x00000060) #define ADR_RX_ETHER_TYPE_1 (HCI_REG_BASE+0x00000064) #define ADR_TX_PACKET_LENGTH (HCI_REG_BASE+0x00000094) #define ADR_TX_PACKET_ID (HCI_REG_BASE+0x00000098) #define ADR_RX_RESCUE_HELPER (HCI_REG_BASE+0x0000009c) #define ADR_HCI_FORCE_PRE_BULK_IN (HCI_REG_BASE+0x000000a0) #define ADR_HCI_BULK_IN_TIME_OUT_VALUE (HCI_REG_BASE+0x000000a4) #define ADR_HCI_STATE_DEBUG_MODE_0 (HCI_REG_BASE+0x000000a8) #define ADR_HCI_STATE_DEBUG_MODE_2 (HCI_REG_BASE+0x000000b0) #define ADR_HCI_STATE_DEBUG_MODE_3 (HCI_REG_BASE+0x000000b4) #define ADR_HCI_STATE_DEBUG_MODE_4 (HCI_REG_BASE+0x000000b8) #define ADR_HCI_STATE_DEBUG_MODE_5 (HCI_REG_BASE+0x000000bc) #define ADR_HCI_STATE_DEBUG_MODE_6 (HCI_REG_BASE+0x000000c0) #define ADR_HCI_STATE_DEBUG_MODE_7 (HCI_REG_BASE+0x000000c8) #define ADR_HCI_TX_ON_DEMAND_LENGTH (HCI_REG_BASE+0x000000cc) #define ADR_HCI_TX_ALLOC_SUCCESS_COUNT (HCI_REG_BASE+0x000000d0) #define ADR_HCI_TX_ALLOC_SPENDING_TIME (HCI_REG_BASE+0x000000d8) #define ADR_RX_TRAP_COUNT (HCI_REG_BASE+0x00000100) #define ADR_TX_TRAP_COUNT (HCI_REG_BASE+0x00000108) #define ADR_RX_DROP_COUNT (HCI_REG_BASE+0x00000110) #define ADR_TX_DROP_COUNT (HCI_REG_BASE+0x00000118) #define ADR_RX_HOST_EVENT_COUNT (HCI_REG_BASE+0x00000120) #define ADR_TX_HOST_COMMAND_COUNT (HCI_REG_BASE+0x00000128) #define ADR_RX_PACKET_COUNTER (HCI_REG_BASE+0x00000130) #define ADR_TX_PACKET_COUNTER (HCI_REG_BASE+0x00000138) #define ADR_SDIO_RX_FAIL_COUNT (HCI_REG_BASE+0x00000140) #define ADR_SDIO_TX_FAIL_COUNT (HCI_REG_BASE+0x00000148) #define ADR_CORRECT_RATE_REPORT_LENGTH (HCI_REG_BASE+0x00000150) #define ADR_TX_PACKET_SEND_TO_RX_DIRECTLY (HCI_REG_BASE+0x00000154) #define ADR_POWER_SAVING_PEER_REJECT_FUNCTION (HCI_REG_BASE+0x00000158) #define ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION (HCI_REG_BASE+0x0000015c) #define ADR_RX_HCI_EXP_0_CTRL (HCI_REG_BASE+0x00000160) #define ADR_RX_HCI_EXP_0_LEN (HCI_REG_BASE+0x00000164) #define ADR_FORCE_RX_AGGREGATION_MODE (HCI_REG_BASE+0x00000168) // CO_REG #define ADR_CS_START_ADDR (CO_REG_BASE+0x00000000) #define ADR_CS_ADD_LEN (CO_REG_BASE+0x00000004) #define ADR_CS_CMD (CO_REG_BASE+0x00000008) #define ADR_CS_INI_BUF (CO_REG_BASE+0x0000000c) #define ADR_CS_PSEUDO_BUF (CO_REG_BASE+0x00000010) #define ADR_CS_CHECK_SUM (CO_REG_BASE+0x00000014) #define ADR_RAND_EN (CO_REG_BASE+0x00000018) #define ADR_RAND_NUM (CO_REG_BASE+0x0000001c) #define ADR_MUL_OP1 (CO_REG_BASE+0x00000060) #define ADR_MUL_OP2 (CO_REG_BASE+0x00000064) #define ADR_MUL_ANS0 (CO_REG_BASE+0x00000068) #define ADR_MUL_ANS1 (CO_REG_BASE+0x0000006c) #define ADR_DMA_RDATA (CO_REG_BASE+0x00000070) #define ADR_DMA_WDATA (CO_REG_BASE+0x00000074) #define ADR_DMA_LEN (CO_REG_BASE+0x00000078) #define ADR_DMA_CLR (CO_REG_BASE+0x0000007c) #define ADR_NAV_DATA (CO_REG_BASE+0x00000080) #define ADR_CO_NAV (CO_REG_BASE+0x00000084) #define ADR_SHA_DST_ADDR (CO_REG_BASE+0x000000a0) #define ADR_SHA_SRC_ADDR (CO_REG_BASE+0x000000a4) #define ADR_SHA_SETTING (CO_REG_BASE+0x000000a8) // EFS_REG #define ADR_EFUSE_CLK_FREQ (EFS_REG_BASE+0x00000000) #define ADR_EFUSE_LDO_TIME (EFS_REG_BASE+0x00000004) #define ADR_EFUSE_STATUS (EFS_REG_BASE+0x00000008) #define ADR_EFUSE_STATUS2 (EFS_REG_BASE+0x0000000c) #define ADR_EFUSE_WR_KICK (EFS_REG_BASE+0x00000010) #define ADR_EFUSE_RD_KICK (EFS_REG_BASE+0x00000014) #define ADR_EFUSE_VDDQ_EN (EFS_REG_BASE+0x00000018) #define ADR_EFUSE_WDATA_0_0 (EFS_REG_BASE+0x00000020) #define ADR_EFUSE_WDATA_0_1 (EFS_REG_BASE+0x00000024) #define ADR_EFUSE_WDATA_0_2 (EFS_REG_BASE+0x00000028) #define ADR_EFUSE_WDATA_0_3 (EFS_REG_BASE+0x0000002c) #define ADR_EFUSE_WDATA_0_4 (EFS_REG_BASE+0x00000030) #define ADR_EFUSE_WDATA_0_5 (EFS_REG_BASE+0x00000034) #define ADR_EFUSE_WDATA_0_6 (EFS_REG_BASE+0x00000038) #define ADR_EFUSE_WDATA_0_7 (EFS_REG_BASE+0x0000003c) // CSR_SPIMAS #define ADR_SPI_DELAY (CSR_SPIMAS_BASE+0x00000000) #define ADR_SPI_CLK_DIV (CSR_SPIMAS_BASE+0x00000004) #define ADR_SPI_BUSY (CSR_SPIMAS_BASE+0x00000008) #define ADR_SPI_CLR (CSR_SPIMAS_BASE+0x0000000c) #define ADR_SPI_MAS_MODE (CSR_SPIMAS_BASE+0x00000010) #define ADR_SPI_M_CFG (CSR_SPIMAS_BASE+0x00000014) #define ADR_SPI_CFG (CSR_SPIMAS_BASE+0x00000018) #define ADR_SPI_MAS_COMMAND_LEN (CSR_SPIMAS_BASE+0x0000001c) // SPIMAS_TX_BUF // SPIMAS_RX_BUF // MRX_REG #define ADR_MRX_MCAST_TB0_0 (MRX_REG_BASE+0x00000000) #define ADR_MRX_MCAST_TB0_1 (MRX_REG_BASE+0x00000004) #define ADR_MRX_MCAST_MK0_0 (MRX_REG_BASE+0x00000008) #define ADR_MRX_MCAST_MK0_1 (MRX_REG_BASE+0x0000000c) #define ADR_MRX_MCAST_CTRL0 (MRX_REG_BASE+0x00000010) #define ADR_MRX_MCAST_TB1_0 (MRX_REG_BASE+0x00000014) #define ADR_MRX_MCAST_TB1_1 (MRX_REG_BASE+0x00000018) #define ADR_MRX_MCAST_MK1_0 (MRX_REG_BASE+0x0000001c) #define ADR_MRX_MCAST_MK1_1 (MRX_REG_BASE+0x00000020) #define ADR_MRX_MCAST_CTRL1 (MRX_REG_BASE+0x00000024) #define ADR_MRX_MCAST_TB2_0 (MRX_REG_BASE+0x00000028) #define ADR_MRX_MCAST_TB2_1 (MRX_REG_BASE+0x0000002c) #define ADR_MRX_MCAST_MK2_0 (MRX_REG_BASE+0x00000030) #define ADR_MRX_MCAST_MK2_1 (MRX_REG_BASE+0x00000034) #define ADR_MRX_MCAST_CTRL2 (MRX_REG_BASE+0x00000038) #define ADR_MRX_MCAST_TB3_0 (MRX_REG_BASE+0x0000003c) #define ADR_MRX_MCAST_TB3_1 (MRX_REG_BASE+0x00000040) #define ADR_MRX_MCAST_MK3_0 (MRX_REG_BASE+0x00000044) #define ADR_MRX_MCAST_MK3_1 (MRX_REG_BASE+0x00000048) #define ADR_MRX_MCAST_CTRL3 (MRX_REG_BASE+0x0000004c) #define ADR_MRX_PHY_INFO (MRX_REG_BASE+0x00000050) #define ADR_MRX_BA_DBG (MRX_REG_BASE+0x00000054) #define ADR_MRX_FLT_TB0 (MRX_REG_BASE+0x00000070) #define ADR_MRX_FLT_TB1 (MRX_REG_BASE+0x00000074) #define ADR_MRX_FLT_TB2 (MRX_REG_BASE+0x00000078) #define ADR_MRX_FLT_TB3 (MRX_REG_BASE+0x0000007c) #define ADR_MRX_FLT_TB4 (MRX_REG_BASE+0x00000080) #define ADR_MRX_FLT_TB5 (MRX_REG_BASE+0x00000084) #define ADR_MRX_FLT_TB6 (MRX_REG_BASE+0x00000088) #define ADR_MRX_FLT_TB7 (MRX_REG_BASE+0x0000008c) #define ADR_MRX_FLT_TB8 (MRX_REG_BASE+0x00000090) #define ADR_MRX_FLT_TB9 (MRX_REG_BASE+0x00000094) #define ADR_MRX_FLT_TB10 (MRX_REG_BASE+0x00000098) #define ADR_MRX_FLT_TB11 (MRX_REG_BASE+0x0000009c) #define ADR_MRX_FLT_TB12 (MRX_REG_BASE+0x000000a0) #define ADR_MRX_FLT_TB13 (MRX_REG_BASE+0x000000a4) #define ADR_MRX_FLT_TB14 (MRX_REG_BASE+0x000000a8) #define ADR_MRX_FLT_TB15 (MRX_REG_BASE+0x000000ac) #define ADR_MRX_FLT_EN0 (MRX_REG_BASE+0x000000b0) #define ADR_MRX_FLT_EN1 (MRX_REG_BASE+0x000000b4) #define ADR_MRX_FLT_EN2 (MRX_REG_BASE+0x000000b8) #define ADR_MRX_FLT_EN3 (MRX_REG_BASE+0x000000bc) #define ADR_MRX_FLT_EN4 (MRX_REG_BASE+0x000000c0) #define ADR_MRX_FLT_EN5 (MRX_REG_BASE+0x000000c4) #define ADR_MRX_FLT_EN6 (MRX_REG_BASE+0x000000c8) #define ADR_MRX_FLT_EN7 (MRX_REG_BASE+0x000000cc) #define ADR_MRX_FLT_EN8 (MRX_REG_BASE+0x000000d0) #define ADR_MRX_LEN_FLT (MRX_REG_BASE+0x000000d4) #define ADR_RX_FLOW_DATA (MRX_REG_BASE+0x000000e0) #define ADR_RX_FLOW_MNG (MRX_REG_BASE+0x000000e4) #define ADR_RX_FLOW_CTRL (MRX_REG_BASE+0x000000e8) #define ADR_RX_TIME_STAMP_CFG (MRX_REG_BASE+0x000000ec) #define ADR_DBG_FF_FULL (MRX_REG_BASE+0x000000f0) #define ADR_DBG_WFF_FULL (MRX_REG_BASE+0x000000f4) #define ADR_DBG_MB_FULL (MRX_REG_BASE+0x000000f8) #define ADR_BA_CTRL (MRX_REG_BASE+0x00000100) #define ADR_BA_TA_0 (MRX_REG_BASE+0x00000104) #define ADR_BA_TA_1 (MRX_REG_BASE+0x00000108) #define ADR_BA_TID (MRX_REG_BASE+0x0000010c) #define ADR_BA_ST_SEQ (MRX_REG_BASE+0x00000110) #define ADR_BA_SB0 (MRX_REG_BASE+0x00000114) #define ADR_BA_SB1 (MRX_REG_BASE+0x00000118) #define ADR_MRX_WATCH_DOG (MRX_REG_BASE+0x0000011c) #define ADR_ACK_GEN_EN (MRX_REG_BASE+0x00000120) #define ADR_ACK_GEN_PARA (MRX_REG_BASE+0x00000124) #define ADR_ACK_GEN_RA_0 (MRX_REG_BASE+0x00000128) #define ADR_ACK_GEN_RA_1 (MRX_REG_BASE+0x0000012c) #define ADR_MIB_LEN_FAIL (MRX_REG_BASE+0x00000130) #define ADR_TRAP_HW_ID (MRX_REG_BASE+0x00000134) #define ADR_ID_IN_USE (MRX_REG_BASE+0x00000138) #define ADR_MRX_ERR (MRX_REG_BASE+0x0000013c) #define ADR_GROUP_WSID (MRX_REG_BASE+0x00000190) #define ADR_HDR_ADDR_SEL (MRX_REG_BASE+0x00000194) #define ADR_FRAME_TYPE_CNTR_SET (MRX_REG_BASE+0x00000198) #define ADR_AMPDU_SCOREBOAD_SIZE (MRX_REG_BASE+0x0000019c) #define ADR_CHANNEL (MRX_REG_BASE+0x000001a0) #define ADR_HIGH_PRIORITY_FRM_HW_ID (MRX_REG_BASE+0x000001a4) #define ADR_DUAL_IDX_EXTEND (MRX_REG_BASE+0x000001a8) #define ADR_MRX_FLT_EN9 (MRX_REG_BASE+0x000001ac) #define ADR_MRX_FLT_EN10 (MRX_REG_BASE+0x000001b0) // AMPDU_REG #define ADR_PHY_INFO (AMPDU_REG_BASE+0x00000000) #define ADR_AMPDU_SIG (AMPDU_REG_BASE+0x00000004) #define ADR_MIB_AMPDU (AMPDU_REG_BASE+0x00000008) #define ADR_LEN_FLT (AMPDU_REG_BASE+0x0000000c) #define ADR_MIB_DELIMITER (AMPDU_REG_BASE+0x00000010) // MT_REG_CSR #define ADR_MTX_INT_STS (MT_REG_CSR_BASE+0x00000000) #define ADR_MTX_INT_EN (MT_REG_CSR_BASE+0x00000004) #define ADR_MTX_MISC_EN (MT_REG_CSR_BASE+0x00000008) #define ADR_MTX_TX_REPORT_OPTION (MT_REG_CSR_BASE+0x0000000c) #define ADR_MTX_STATUS0 (MT_REG_CSR_BASE+0x00000010) #define ADR_MTX_STATUS4 (MT_REG_CSR_BASE+0x00000014) #define ADR_MTX_HALT_OPTION (MT_REG_CSR_BASE+0x00000018) #define ADR_MTX_PHYTX_DBG1 (MT_REG_CSR_BASE+0x0000001c) #define ADR_MTX_MIB_WSID0 (MT_REG_CSR_BASE+0x00000020) #define ADR_MTX_MIB_WSID1 (MT_REG_CSR_BASE+0x00000024) #define ADR_MTX_MIB_WSID2 (MT_REG_CSR_BASE+0x00000028) #define ADR_MTX_MIB_WSID3 (MT_REG_CSR_BASE+0x0000002c) #define ADR_MTX_MIB_WSID4 (MT_REG_CSR_BASE+0x00000030) #define ADR_MTX_MIB_WSID5 (MT_REG_CSR_BASE+0x00000034) #define ADR_MTX_MIB_WSID6 (MT_REG_CSR_BASE+0x00000038) #define ADR_MTX_MIB_WSID7 (MT_REG_CSR_BASE+0x0000003c) #define ADR_STAT_CONF0 (MT_REG_CSR_BASE+0x00000040) #define ADR_STAT_CONF1 (MT_REG_CSR_BASE+0x00000044) #define ADR_MTX_PEER_PS_LOCK (MT_REG_CSR_BASE+0x00000060) #define ADR_MTX_PEER_LOCK_STATUS (MT_REG_CSR_BASE+0x00000060) #define ADR_MTX_RATERPT (MT_REG_CSR_BASE+0x00000064) #define ADR_MTX_DBGOPT_FORCE_RATE (MT_REG_CSR_BASE+0x00000068) #define ADR_MTX_DBGOPT_FORCE_RATE_ENABLE (MT_REG_CSR_BASE+0x0000006c) #define ADR_MTX_DBG_PHYTXIPTIMEOUT (MT_REG_CSR_BASE+0x00000078) #define ADR_MTX_DBG_MORE (MT_REG_CSR_BASE+0x0000007c) #define ADR_MTX_DBG_ROIFSAIR1 (MT_REG_CSR_BASE+0x00000080) #define ADR_MTX_DBG_ROIFSAIR2 (MT_REG_CSR_BASE+0x00000084) #define ADR_MTX_BCN_PKT_SET0 (MT_REG_CSR_BASE+0x00000088) #define ADR_MTX_BCN_PKT_SET1 (MT_REG_CSR_BASE+0x0000008c) #define ADR_MTX_BCN_DTIM_SET0 (MT_REG_CSR_BASE+0x00000090) #define ADR_MTX_BCN_DTIM_SET1 (MT_REG_CSR_BASE+0x00000094) #define ADR_MTX_BCN_DTIM_CONFG (MT_REG_CSR_BASE+0x00000098) #define ADR_MTX_BCN_DTIM_INT_W1CLR (MT_REG_CSR_BASE+0x0000009c) #define ADR_MTX_BCN_INT_STS (MT_REG_CSR_BASE+0x000000a0) #define ADR_MTX_BCN_EN_INT (MT_REG_CSR_BASE+0x000000a4) #define ADR_MTX_BCN_EN_MISC (MT_REG_CSR_BASE+0x000000a8) #define ADR_MTX_BCN_MISC (MT_REG_CSR_BASE+0x000000ac) #define ADR_MTX_BCN_PRD (MT_REG_CSR_BASE+0x000000b0) #define ADR_MTX_BCN_TSF_L (MT_REG_CSR_BASE+0x000000b4) #define ADR_MTX_BCN_TSF_U (MT_REG_CSR_BASE+0x000000b8) #define ADR_MTX_TIME_TOUT (MT_REG_CSR_BASE+0x000000c0) #define ADR_MTX_TIME_IFS (MT_REG_CSR_BASE+0x000000c4) #define ADR_MTX_TIME_FINETUNE (MT_REG_CSR_BASE+0x000000c8) #define ADR_MTX_STATUS (MT_REG_CSR_BASE+0x000000cc) #define ADR_MTX_PHYRXIFS_DBG (MT_REG_CSR_BASE+0x000000d0) #define ADR_MTX_DBG_IFSAIRRO0 (MT_REG_CSR_BASE+0x000000e0) #define ADR_MTX_DBG_IFSAIRRO1 (MT_REG_CSR_BASE+0x000000e4) #define ADR_MTX_DBG_IFSAIRRO2 (MT_REG_CSR_BASE+0x000000e8) #define ADR_MTX_DBG_IFSAIRRO3 (MT_REG_CSR_BASE+0x000000ec) #define ADR_MTX_NAV (MT_REG_CSR_BASE+0x000000f0) #define ADR_MTX_DBG_RO_BASE1 (MT_REG_CSR_BASE+0x000000f4) #define ADR_MTX_DBG_RO_BASE2 (MT_REG_CSR_BASE+0x000000f8) #define ADR_MTX_DBG_RO_BASE3 (MT_REG_CSR_BASE+0x000000fc) // TXQ0_MT_Q_REG_CSR #define ADR_TXQ0_MTX_Q_MISC_EN (TXQ0_MT_Q_REG_CSR_BASE+0x00000000) #define ADR_TXQ0_MTX_Q_AIFSN (TXQ0_MT_Q_REG_CSR_BASE+0x00000004) #define ADR_TXQ0_MTX_Q_BKF_CNT_DBG (TXQ0_MT_Q_REG_CSR_BASE+0x00000008) #define ADR_TXQ0_MTX_Q_HWDBG (TXQ0_MT_Q_REG_CSR_BASE+0x0000000c) #define ADR_TXQ0_MTX_Q_HWDBG2 (TXQ0_MT_Q_REG_CSR_BASE+0x00000010) // TXQ1_MT_Q_REG_CSR #define ADR_TXQ1_MTX_Q_MISC_EN (TXQ1_MT_Q_REG_CSR_BASE+0x00000000) #define ADR_TXQ1_MTX_Q_AIFSN (TXQ1_MT_Q_REG_CSR_BASE+0x00000004) #define ADR_TXQ1_MTX_Q_BKF_CNT_DBG (TXQ1_MT_Q_REG_CSR_BASE+0x00000008) #define ADR_TXQ1_MTX_Q_HWDBG (TXQ1_MT_Q_REG_CSR_BASE+0x0000000c) #define ADR_TXQ1_MTX_Q_HWDBG2 (TXQ1_MT_Q_REG_CSR_BASE+0x00000010) // TXQ2_MT_Q_REG_CSR #define ADR_TXQ2_MTX_Q_MISC_EN (TXQ2_MT_Q_REG_CSR_BASE+0x00000000) #define ADR_TXQ2_MTX_Q_AIFSN (TXQ2_MT_Q_REG_CSR_BASE+0x00000004) #define ADR_TXQ2_MTX_Q_BKF_CNT_DBG (TXQ2_MT_Q_REG_CSR_BASE+0x00000008) #define ADR_TXQ2_MTX_Q_HWDBG (TXQ2_MT_Q_REG_CSR_BASE+0x0000000c) #define ADR_TXQ2_MTX_Q_HWDBG2 (TXQ2_MT_Q_REG_CSR_BASE+0x00000010) // TXQ3_MT_Q_REG_CSR #define ADR_TXQ3_MTX_Q_MISC_EN (TXQ3_MT_Q_REG_CSR_BASE+0x00000000) #define ADR_TXQ3_MTX_Q_AIFSN (TXQ3_MT_Q_REG_CSR_BASE+0x00000004) #define ADR_TXQ3_MTX_Q_BKF_CNT_DBG (TXQ3_MT_Q_REG_CSR_BASE+0x00000008) #define ADR_TXQ3_MTX_Q_HWDBG (TXQ3_MT_Q_REG_CSR_BASE+0x0000000c) #define ADR_TXQ3_MTX_Q_HWDBG2 (TXQ3_MT_Q_REG_CSR_BASE+0x00000010) // TXQ4_MT_Q_REG_CSR #define ADR_TXQ4_MTX_Q_MISC_EN (TXQ4_MT_Q_REG_CSR_BASE+0x00000000) #define ADR_TXQ4_MTX_Q_AIFSN (TXQ4_MT_Q_REG_CSR_BASE+0x00000004) #define ADR_TXQ4_MTX_Q_BKF_CNT_DBG (TXQ4_MT_Q_REG_CSR_BASE+0x00000008) #define ADR_TXQ4_MTX_Q_HWDBG (TXQ4_MT_Q_REG_CSR_BASE+0x0000000c) #define ADR_TXQ4_MTX_Q_HWDBG2 (TXQ4_MT_Q_REG_CSR_BASE+0x00000010) // TXQ5_MT_Q_REG_CSR #define ADR_TXQ5_MTX_Q_MISC_EN (TXQ5_MT_Q_REG_CSR_BASE+0x00000000) #define ADR_TXQ5_MTX_Q_AIFSN (TXQ5_MT_Q_REG_CSR_BASE+0x00000004) #define ADR_TXQ5_MTX_Q_BKF_CNT_DBG (TXQ5_MT_Q_REG_CSR_BASE+0x00000008) #define ADR_TXQ5_MTX_Q_HWDBG (TXQ5_MT_Q_REG_CSR_BASE+0x0000000c) #define ADR_TXQ5_MTX_Q_HWDBG2 (TXQ5_MT_Q_REG_CSR_BASE+0x00000010) // MT_RESPFRM_REG #define ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION (MT_RESPFRM_REG_BASE+0x00000000) #define ADR_MTX_RESPFRM_RATE_TABLE_00 (MT_RESPFRM_REG_BASE+0x00000004) #define ADR_MTX_RESPFRM_RATE_TABLE_01 (MT_RESPFRM_REG_BASE+0x00000008) #define ADR_MTX_RESPFRM_RATE_TABLE_02 (MT_RESPFRM_REG_BASE+0x0000000c) #define ADR_MTX_RESPFRM_RATE_TABLE_03 (MT_RESPFRM_REG_BASE+0x00000010) #define ADR_MTX_RESPFRM_RATE_TABLE_11 (MT_RESPFRM_REG_BASE+0x00000014) #define ADR_MTX_RESPFRM_RATE_TABLE_12 (MT_RESPFRM_REG_BASE+0x00000018) #define ADR_MTX_RESPFRM_RATE_TABLE_13 (MT_RESPFRM_REG_BASE+0x0000001c) #define ADR_MTX_RESPFRM_RATE_TABLE_90_B0 (MT_RESPFRM_REG_BASE+0x00000020) #define ADR_MTX_RESPFRM_RATE_TABLE_91_B1 (MT_RESPFRM_REG_BASE+0x00000024) #define ADR_MTX_RESPFRM_RATE_TABLE_92_B2 (MT_RESPFRM_REG_BASE+0x00000028) #define ADR_MTX_RESPFRM_RATE_TABLE_93_B3 (MT_RESPFRM_REG_BASE+0x0000002c) #define ADR_MTX_RESPFRM_RATE_TABLE_94_B4 (MT_RESPFRM_REG_BASE+0x00000030) #define ADR_MTX_RESPFRM_RATE_TABLE_95_B5 (MT_RESPFRM_REG_BASE+0x00000034) #define ADR_MTX_RESPFRM_RATE_TABLE_96_B6 (MT_RESPFRM_REG_BASE+0x00000038) #define ADR_MTX_RESPFRM_RATE_TABLE_97_B7 (MT_RESPFRM_REG_BASE+0x0000003c) #define ADR_MTX_RESPFRM_RATE_TABLE_C0_E0 (MT_RESPFRM_REG_BASE+0x00000040) #define ADR_MTX_RESPFRM_RATE_TABLE_C1_E1 (MT_RESPFRM_REG_BASE+0x00000044) #define ADR_MTX_RESPFRM_RATE_TABLE_C2_E2 (MT_RESPFRM_REG_BASE+0x00000048) #define ADR_MTX_RESPFRM_RATE_TABLE_C3_E3 (MT_RESPFRM_REG_BASE+0x0000004c) #define ADR_MTX_RESPFRM_RATE_TABLE_C4_E4 (MT_RESPFRM_REG_BASE+0x00000050) #define ADR_MTX_RESPFRM_RATE_TABLE_C5_E5 (MT_RESPFRM_REG_BASE+0x00000054) #define ADR_MTX_RESPFRM_RATE_TABLE_C6_E6 (MT_RESPFRM_REG_BASE+0x00000058) #define ADR_MTX_RESPFRM_RATE_TABLE_C7_E7 (MT_RESPFRM_REG_BASE+0x0000005c) #define ADR_MTX_RESPFRM_RATE_TABLE_D0_F0 (MT_RESPFRM_REG_BASE+0x00000060) #define ADR_MTX_RESPFRM_RATE_TABLE_D1_F1 (MT_RESPFRM_REG_BASE+0x00000064) #define ADR_MTX_RESPFRM_RATE_TABLE_D2_F2 (MT_RESPFRM_REG_BASE+0x00000068) #define ADR_MTX_RESPFRM_RATE_TABLE_D3_F3 (MT_RESPFRM_REG_BASE+0x0000006c) #define ADR_MTX_RESPFRM_RATE_TABLE_D4_F4 (MT_RESPFRM_REG_BASE+0x00000070) #define ADR_MTX_RESPFRM_RATE_TABLE_D5_F5 (MT_RESPFRM_REG_BASE+0x00000074) #define ADR_MTX_RESPFRM_RATE_TABLE_D6_F6 (MT_RESPFRM_REG_BASE+0x00000078) #define ADR_MTX_RESPFRM_RATE_TABLE_D7_F7 (MT_RESPFRM_REG_BASE+0x0000007c) #define ADR_MTX_RESPFRM_RATE_TABLE_D8_F8 (MT_RESPFRM_REG_BASE+0x00000080) #define ADR_MTX_RESPFRM_RATE_TABLE_D9_F9 (MT_RESPFRM_REG_BASE+0x00000084) #define ADR_MTX_RESPFRM_RATE_TABLE_DA_FA (MT_RESPFRM_REG_BASE+0x00000088) #define ADR_MTX_RESPFRM_RATE_TABLE_DB_FB (MT_RESPFRM_REG_BASE+0x0000008c) #define ADR_MTX_RESPFRM_RATE_TABLE_DC_FC (MT_RESPFRM_REG_BASE+0x00000090) #define ADR_MTX_RESPFRM_RATE_TABLE_DD_FD (MT_RESPFRM_REG_BASE+0x00000094) #define ADR_MTX_RESPFRM_RATE_TABLE_DE_FE (MT_RESPFRM_REG_BASE+0x00000098) #define ADR_MTX_RESPFRM_RATE_TABLE_DF_FF (MT_RESPFRM_REG_BASE+0x0000009c) #define ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION (MT_RESPFRM_REG_BASE+0x000000a0) #define ADR_MTX_RESPFRM_INFO_00 (MT_RESPFRM_REG_BASE+0x000000a4) #define ADR_MTX_RESPFRM_INFO_01 (MT_RESPFRM_REG_BASE+0x000000a8) #define ADR_MTX_RESPFRM_INFO_02 (MT_RESPFRM_REG_BASE+0x000000ac) #define ADR_MTX_RESPFRM_INFO_03 (MT_RESPFRM_REG_BASE+0x000000b0) #define ADR_MTX_RESPFRM_INFO_11 (MT_RESPFRM_REG_BASE+0x000000b4) #define ADR_MTX_RESPFRM_INFO_12 (MT_RESPFRM_REG_BASE+0x000000b8) #define ADR_MTX_RESPFRM_INFO_13 (MT_RESPFRM_REG_BASE+0x000000bc) #define ADR_MTX_RESPFRM_INFO_90_B0 (MT_RESPFRM_REG_BASE+0x000000c0) #define ADR_MTX_RESPFRM_INFO_91_B1 (MT_RESPFRM_REG_BASE+0x000000c4) #define ADR_MTX_RESPFRM_INFO_92_B2 (MT_RESPFRM_REG_BASE+0x000000c8) #define ADR_MTX_RESPFRM_INFO_93_B3 (MT_RESPFRM_REG_BASE+0x000000cc) #define ADR_MTX_RESPFRM_INFO_94_B4 (MT_RESPFRM_REG_BASE+0x000000d0) #define ADR_MTX_RESPFRM_INFO_95_B5 (MT_RESPFRM_REG_BASE+0x000000d4) #define ADR_MTX_RESPFRM_INFO_96_B6 (MT_RESPFRM_REG_BASE+0x000000d8) #define ADR_MTX_RESPFRM_INFO_97_B7 (MT_RESPFRM_REG_BASE+0x000000dc) #define ADR_MTX_RESPFRM_INFO_C0 (MT_RESPFRM_REG_BASE+0x000000e0) #define ADR_MTX_RESPFRM_INFO_C1 (MT_RESPFRM_REG_BASE+0x000000e4) #define ADR_MTX_RESPFRM_INFO_C2 (MT_RESPFRM_REG_BASE+0x000000e8) #define ADR_MTX_RESPFRM_INFO_C3 (MT_RESPFRM_REG_BASE+0x000000ec) #define ADR_MTX_RESPFRM_INFO_C4 (MT_RESPFRM_REG_BASE+0x000000f0) #define ADR_MTX_RESPFRM_INFO_C5 (MT_RESPFRM_REG_BASE+0x000000f4) #define ADR_MTX_RESPFRM_INFO_C6 (MT_RESPFRM_REG_BASE+0x000000f8) #define ADR_MTX_RESPFRM_INFO_C7 (MT_RESPFRM_REG_BASE+0x000000fc) #define ADR_MTX_RESPFRM_INFO_D0 (MT_RESPFRM_REG_BASE+0x00000100) #define ADR_MTX_RESPFRM_INFO_D1 (MT_RESPFRM_REG_BASE+0x00000104) #define ADR_MTX_RESPFRM_INFO_D2 (MT_RESPFRM_REG_BASE+0x00000108) #define ADR_MTX_RESPFRM_INFO_D3 (MT_RESPFRM_REG_BASE+0x0000010c) #define ADR_MTX_RESPFRM_INFO_D4 (MT_RESPFRM_REG_BASE+0x00000110) #define ADR_MTX_RESPFRM_INFO_D5 (MT_RESPFRM_REG_BASE+0x00000114) #define ADR_MTX_RESPFRM_INFO_D6 (MT_RESPFRM_REG_BASE+0x00000118) #define ADR_MTX_RESPFRM_INFO_D7 (MT_RESPFRM_REG_BASE+0x0000011c) #define ADR_MTX_RESPFRM_INFO_D8 (MT_RESPFRM_REG_BASE+0x00000120) #define ADR_MTX_RESPFRM_INFO_D9 (MT_RESPFRM_REG_BASE+0x00000124) #define ADR_MTX_RESPFRM_INFO_DA (MT_RESPFRM_REG_BASE+0x00000128) #define ADR_MTX_RESPFRM_INFO_DB (MT_RESPFRM_REG_BASE+0x0000012c) #define ADR_MTX_RESPFRM_INFO_DC (MT_RESPFRM_REG_BASE+0x00000130) #define ADR_MTX_RESPFRM_INFO_DD (MT_RESPFRM_REG_BASE+0x00000134) #define ADR_MTX_RESPFRM_INFO_DE (MT_RESPFRM_REG_BASE+0x00000138) #define ADR_MTX_RESPFRM_INFO_DF (MT_RESPFRM_REG_BASE+0x0000013c) // HIF_INFO #define ADR_WSID0 (HIF_INFO_BASE+0x00000000) #define ADR_PEER_MAC0_0 (HIF_INFO_BASE+0x00000004) #define ADR_PEER_MAC0_1 (HIF_INFO_BASE+0x00000008) #define ADR_TX_ACK_POLICY_0_0 (HIF_INFO_BASE+0x0000000c) #define ADR_TX_SEQ_CTRL_0_0 (HIF_INFO_BASE+0x00000010) #define ADR_TX_ACK_POLICY_0_1 (HIF_INFO_BASE+0x00000014) #define ADR_TX_SEQ_CTRL_0_1 (HIF_INFO_BASE+0x00000018) #define ADR_TX_ACK_POLICY_0_2 (HIF_INFO_BASE+0x0000001c) #define ADR_TX_SEQ_CTRL_0_2 (HIF_INFO_BASE+0x00000020) #define ADR_TX_ACK_POLICY_0_3 (HIF_INFO_BASE+0x00000024) #define ADR_TX_SEQ_CTRL_0_3 (HIF_INFO_BASE+0x00000028) #define ADR_TX_ACK_POLICY_0_4 (HIF_INFO_BASE+0x0000002c) #define ADR_TX_SEQ_CTRL_0_4 (HIF_INFO_BASE+0x00000030) #define ADR_TX_ACK_POLICY_0_5 (HIF_INFO_BASE+0x00000034) #define ADR_TX_SEQ_CTRL_0_5 (HIF_INFO_BASE+0x00000038) #define ADR_TX_ACK_POLICY_0_6 (HIF_INFO_BASE+0x0000003c) #define ADR_TX_SEQ_CTRL_0_6 (HIF_INFO_BASE+0x00000040) #define ADR_TX_ACK_POLICY_0_7 (HIF_INFO_BASE+0x00000044) #define ADR_TX_SEQ_CTRL_0_7 (HIF_INFO_BASE+0x00000048) #define ADR_WSID1 (HIF_INFO_BASE+0x00000050) #define ADR_PEER_MAC1_0 (HIF_INFO_BASE+0x00000054) #define ADR_PEER_MAC1_1 (HIF_INFO_BASE+0x00000058) #define ADR_TX_ACK_POLICY_1_0 (HIF_INFO_BASE+0x0000005c) #define ADR_TX_SEQ_CTRL_1_0 (HIF_INFO_BASE+0x00000060) #define ADR_TX_ACK_POLICY_1_1 (HIF_INFO_BASE+0x00000064) #define ADR_TX_SEQ_CTRL_1_1 (HIF_INFO_BASE+0x00000068) #define ADR_TX_ACK_POLICY_1_2 (HIF_INFO_BASE+0x0000006c) #define ADR_TX_SEQ_CTRL_1_2 (HIF_INFO_BASE+0x00000070) #define ADR_TX_ACK_POLICY_1_3 (HIF_INFO_BASE+0x00000074) #define ADR_TX_SEQ_CTRL_1_3 (HIF_INFO_BASE+0x00000078) #define ADR_TX_ACK_POLICY_1_4 (HIF_INFO_BASE+0x0000007c) #define ADR_TX_SEQ_CTRL_1_4 (HIF_INFO_BASE+0x00000080) #define ADR_TX_ACK_POLICY_1_5 (HIF_INFO_BASE+0x00000084) #define ADR_TX_SEQ_CTRL_1_5 (HIF_INFO_BASE+0x00000088) #define ADR_TX_ACK_POLICY_1_6 (HIF_INFO_BASE+0x0000008c) #define ADR_TX_SEQ_CTRL_1_6 (HIF_INFO_BASE+0x00000090) #define ADR_TX_ACK_POLICY_1_7 (HIF_INFO_BASE+0x00000094) #define ADR_TX_SEQ_CTRL_1_7 (HIF_INFO_BASE+0x00000098) // PHY_RATE_INFO #define ADR_PACKET_ID_ALLOCATION_PRIORITY (PHY_RATE_INFO_BASE+0x00000000) // MAC_GLB_SET #define ADR_MAC_MODE (MAC_GLB_SET_BASE+0x00000000) #define ADR_ALL_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000004) #define ADR_ENG_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x00000008) #define ADR_CSR_SOFTWARE_RESET (MAC_GLB_SET_BASE+0x0000000c) #define ADR_MAC_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000010) #define ADR_MAC_ENGINE_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000014) #define ADR_MAC_CSR_CLOCK_ENABLE (MAC_GLB_SET_BASE+0x00000018) #define ADR_GLBLE_SET (MAC_GLB_SET_BASE+0x0000001c) #define ADR_REASON_TRAP0 (MAC_GLB_SET_BASE+0x00000020) #define ADR_REASON_TRAP1 (MAC_GLB_SET_BASE+0x00000024) #define ADR_BSSID_0 (MAC_GLB_SET_BASE+0x00000028) #define ADR_BSSID_1 (MAC_GLB_SET_BASE+0x0000002c) #define ADR_STA_MAC_0 (MAC_GLB_SET_BASE+0x00000030) #define ADR_STA_MAC_1 (MAC_GLB_SET_BASE+0x00000034) #define ADR_SCRT_SET (MAC_GLB_SET_BASE+0x00000038) #define ADR_SCRT_STATE (MAC_GLB_SET_BASE+0x0000003c) #define ADR_BSSID1_0 (MAC_GLB_SET_BASE+0x00000040) #define ADR_BSSID1_1 (MAC_GLB_SET_BASE+0x00000044) #define ADR_STA_MAC1_0 (MAC_GLB_SET_BASE+0x00000048) #define ADR_STA_MAC1_1 (MAC_GLB_SET_BASE+0x0000004c) #define ADR_OP_MODE1 (MAC_GLB_SET_BASE+0x00000050) // BTCX_REG #define ADR_BTCX0 (BTCX_REG_BASE+0x00000000) #define ADR_BTCX1 (BTCX_REG_BASE+0x00000004) #define ADR_SWITCH_CTL (BTCX_REG_BASE+0x00000008) #define ADR_RANDOM_CTL (BTCX_REG_BASE+0x0000000c) #define ADR_BTCX_MISC_CTL (BTCX_REG_BASE+0x00000010) // MIB_REG #define ADR_MIB_EN (MIB_REG_BASE+0x00000000) #define ADR_MTX_WSID0_SUCC (MIB_REG_BASE+0x00000118) #define ADR_MTX_WSID0_FRM (MIB_REG_BASE+0x00000128) #define ADR_MTX_WSID0_RETRY (MIB_REG_BASE+0x00000138) #define ADR_MTX_WSID0_TOTAL (MIB_REG_BASE+0x00000148) #define ADR_MTX_GROUP (MIB_REG_BASE+0x0000016c) #define ADR_MTX_FAIL (MIB_REG_BASE+0x00000170) #define ADR_MTX_RETRY (MIB_REG_BASE+0x00000174) #define ADR_MTX_MULTI_RETRY (MIB_REG_BASE+0x00000178) #define ADR_MTX_RTS_SUCCESS (MIB_REG_BASE+0x0000017c) #define ADR_MTX_RTS_FAIL (MIB_REG_BASE+0x00000180) #define ADR_MTX_ACK_FAIL (MIB_REG_BASE+0x00000184) #define ADR_MTX_FRM (MIB_REG_BASE+0x00000188) #define ADR_MTX_ACK_TX (MIB_REG_BASE+0x0000018c) #define ADR_MTX_CTS_TX (MIB_REG_BASE+0x00000190) #define ADR_MRX_DUP_FRM (MIB_REG_BASE+0x00000194) #define ADR_MRX_FRG_FRM (MIB_REG_BASE+0x00000198) #define ADR_MRX_GROUP_FRM (MIB_REG_BASE+0x0000019c) #define ADR_MRX_FCS_ERR (MIB_REG_BASE+0x000001a0) #define ADR_MRX_FCS_SUCC (MIB_REG_BASE+0x000001a4) #define ADR_MRX_MISS (MIB_REG_BASE+0x000001a8) #define ADR_MRX_ALC_FAIL (MIB_REG_BASE+0x000001ac) #define ADR_MRX_DAT_NTF (MIB_REG_BASE+0x000001b0) #define ADR_MRX_RTS_NTF (MIB_REG_BASE+0x000001b4) #define ADR_MRX_CTS_NTF (MIB_REG_BASE+0x000001b8) #define ADR_MRX_ACK_NTF (MIB_REG_BASE+0x000001bc) #define ADR_MRX_BA_NTF (MIB_REG_BASE+0x000001c0) #define ADR_MRX_DATA_NTF (MIB_REG_BASE+0x000001c4) #define ADR_MRX_MNG_NTF (MIB_REG_BASE+0x000001c8) #define ADR_MRX_DAT_CRC_NTF (MIB_REG_BASE+0x000001cc) #define ADR_MRX_BAR_NTF (MIB_REG_BASE+0x000001d0) #define ADR_MRX_MB_MISS (MIB_REG_BASE+0x000001d4) #define ADR_MRX_NIDLE_MISS (MIB_REG_BASE+0x000001d8) #define ADR_MRX_CSR_NTF (MIB_REG_BASE+0x000001dc) #define ADR_DBG_Q0_FRM_SUCCESS (MIB_REG_BASE+0x00000218) #define ADR_DBG_Q0_FRM_FAIL (MIB_REG_BASE+0x0000021c) #define ADR_DBG_Q0_ACK_SUCCESS (MIB_REG_BASE+0x00000220) #define ADR_DBG_Q0_ACK_FAIL (MIB_REG_BASE+0x00000224) #define ADR_DBG_Q1_FRM_SUCCESS (MIB_REG_BASE+0x00000268) #define ADR_DBG_Q1_FRM_FAIL (MIB_REG_BASE+0x0000026c) #define ADR_DBG_Q1_ACK_SUCCESS (MIB_REG_BASE+0x00000270) #define ADR_DBG_Q1_ACK_FAIL (MIB_REG_BASE+0x00000274) #define ADR_DBG_Q2_FRM_SUCCESS (MIB_REG_BASE+0x00000318) #define ADR_DBG_Q2_FRM_FAIL (MIB_REG_BASE+0x0000031c) #define ADR_DBG_Q2_ACK_SUCCESS (MIB_REG_BASE+0x00000320) #define ADR_DBG_Q2_ACK_FAIL (MIB_REG_BASE+0x00000324) #define ADR_DBG_Q3_FRM_SUCCESS (MIB_REG_BASE+0x00000368) #define ADR_DBG_Q3_FRM_FAIL (MIB_REG_BASE+0x0000036c) #define ADR_DBG_Q3_ACK_SUCCESS (MIB_REG_BASE+0x00000370) #define ADR_DBG_Q3_ACK_FAIL (MIB_REG_BASE+0x00000374) #define ADR_MIB_SCRT_TKIP0 (MIB_REG_BASE+0x00000418) #define ADR_MIB_SCRT_TKIP1 (MIB_REG_BASE+0x0000041c) #define ADR_MIB_SCRT_TKIP2 (MIB_REG_BASE+0x00000420) #define ADR_MIB_SCRT_CCMP0 (MIB_REG_BASE+0x00000424) #define ADR_MIB_SCRT_CCMP1 (MIB_REG_BASE+0x00000428) #define ADR_DBG_LEN_CRC_FAIL (MIB_REG_BASE+0x00000468) #define ADR_DBG_LEN_ALC_FAIL (MIB_REG_BASE+0x0000046c) #define ADR_DBG_AMPDU_PASS (MIB_REG_BASE+0x00000470) #define ADR_DBG_AMPDU_FAIL (MIB_REG_BASE+0x00000474) #define ADR_ID_ALC_FAIL1 (MIB_REG_BASE+0x00000478) #define ADR_ID_ALC_FAIL2 (MIB_REG_BASE+0x0000047c) // WSID_EXT #define ADR_WSID2 (WSID_EXT_BASE+0x00000000) #define ADR_PEER_MAC2_0 (WSID_EXT_BASE+0x00000004) #define ADR_PEER_MAC2_1 (WSID_EXT_BASE+0x00000008) #define ADR_TX_ACK_POLICY_2_0 (WSID_EXT_BASE+0x0000000c) #define ADR_TX_SEQ_CTRL_2_0 (WSID_EXT_BASE+0x00000010) #define ADR_TX_ACK_POLICY_2_1 (WSID_EXT_BASE+0x00000014) #define ADR_TX_SEQ_CTRL_2_1 (WSID_EXT_BASE+0x00000018) #define ADR_TX_ACK_POLICY_2_2 (WSID_EXT_BASE+0x0000001c) #define ADR_TX_SEQ_CTRL_2_2 (WSID_EXT_BASE+0x00000020) #define ADR_TX_ACK_POLICY_2_3 (WSID_EXT_BASE+0x00000024) #define ADR_TX_SEQ_CTRL_2_3 (WSID_EXT_BASE+0x00000028) #define ADR_TX_ACK_POLICY_2_4 (WSID_EXT_BASE+0x0000002c) #define ADR_TX_SEQ_CTRL_2_4 (WSID_EXT_BASE+0x00000030) #define ADR_TX_ACK_POLICY_2_5 (WSID_EXT_BASE+0x00000034) #define ADR_TX_SEQ_CTRL_2_5 (WSID_EXT_BASE+0x00000038) #define ADR_TX_ACK_POLICY_2_6 (WSID_EXT_BASE+0x0000003c) #define ADR_TX_SEQ_CTRL_2_6 (WSID_EXT_BASE+0x00000040) #define ADR_TX_ACK_POLICY_2_7 (WSID_EXT_BASE+0x00000044) #define ADR_TX_SEQ_CTRL_2_7 (WSID_EXT_BASE+0x00000048) #define ADR_WSID3 (WSID_EXT_BASE+0x00000050) #define ADR_PEER_MAC3_0 (WSID_EXT_BASE+0x00000054) #define ADR_PEER_MAC3_1 (WSID_EXT_BASE+0x00000058) #define ADR_TX_ACK_POLICY_3_0 (WSID_EXT_BASE+0x0000005c) #define ADR_TX_SEQ_CTRL_3_0 (WSID_EXT_BASE+0x00000060) #define ADR_TX_ACK_POLICY_3_1 (WSID_EXT_BASE+0x00000064) #define ADR_TX_SEQ_CTRL_3_1 (WSID_EXT_BASE+0x00000068) #define ADR_TX_ACK_POLICY_3_2 (WSID_EXT_BASE+0x0000006c) #define ADR_TX_SEQ_CTRL_3_2 (WSID_EXT_BASE+0x00000070) #define ADR_TX_ACK_POLICY_3_3 (WSID_EXT_BASE+0x00000074) #define ADR_TX_SEQ_CTRL_3_3 (WSID_EXT_BASE+0x00000078) #define ADR_TX_ACK_POLICY_3_4 (WSID_EXT_BASE+0x0000007c) #define ADR_TX_SEQ_CTRL_3_4 (WSID_EXT_BASE+0x00000080) #define ADR_TX_ACK_POLICY_3_5 (WSID_EXT_BASE+0x00000084) #define ADR_TX_SEQ_CTRL_3_5 (WSID_EXT_BASE+0x00000088) #define ADR_TX_ACK_POLICY_3_6 (WSID_EXT_BASE+0x0000008c) #define ADR_TX_SEQ_CTRL_3_6 (WSID_EXT_BASE+0x00000090) #define ADR_TX_ACK_POLICY_3_7 (WSID_EXT_BASE+0x00000094) #define ADR_TX_SEQ_CTRL_3_7 (WSID_EXT_BASE+0x00000098) #define ADR_WSID4 (WSID_EXT_BASE+0x000000a0) #define ADR_PEER_MAC4_0 (WSID_EXT_BASE+0x000000a4) #define ADR_PEER_MAC4_1 (WSID_EXT_BASE+0x000000a8) #define ADR_TX_ACK_POLICY_4_0 (WSID_EXT_BASE+0x000000ac) #define ADR_TX_SEQ_CTRL_4_0 (WSID_EXT_BASE+0x000000b0) #define ADR_TX_ACK_POLICY_4_1 (WSID_EXT_BASE+0x000000b4) #define ADR_TX_SEQ_CTRL_4_1 (WSID_EXT_BASE+0x000000b8) #define ADR_TX_ACK_POLICY_4_2 (WSID_EXT_BASE+0x000000bc) #define ADR_TX_SEQ_CTRL_4_2 (WSID_EXT_BASE+0x000000c0) #define ADR_TX_ACK_POLICY_4_3 (WSID_EXT_BASE+0x000000c4) #define ADR_TX_SEQ_CTRL_4_3 (WSID_EXT_BASE+0x000000c8) #define ADR_TX_ACK_POLICY_4_4 (WSID_EXT_BASE+0x000000cc) #define ADR_TX_SEQ_CTRL_4_4 (WSID_EXT_BASE+0x000000d0) #define ADR_TX_ACK_POLICY_4_5 (WSID_EXT_BASE+0x000000d4) #define ADR_TX_SEQ_CTRL_4_5 (WSID_EXT_BASE+0x000000d8) #define ADR_TX_ACK_POLICY_4_6 (WSID_EXT_BASE+0x000000dc) #define ADR_TX_SEQ_CTRL_4_6 (WSID_EXT_BASE+0x000000e0) #define ADR_TX_ACK_POLICY_4_7 (WSID_EXT_BASE+0x000000e4) #define ADR_TX_SEQ_CTRL_4_7 (WSID_EXT_BASE+0x000000e8) #define ADR_WSID5 (WSID_EXT_BASE+0x000000f0) #define ADR_PEER_MAC5_0 (WSID_EXT_BASE+0x000000f4) #define ADR_PEER_MAC5_1 (WSID_EXT_BASE+0x000000f8) #define ADR_TX_ACK_POLICY_5_0 (WSID_EXT_BASE+0x000000fc) #define ADR_TX_SEQ_CTRL_5_0 (WSID_EXT_BASE+0x00000100) #define ADR_TX_ACK_POLICY_5_1 (WSID_EXT_BASE+0x00000104) #define ADR_TX_SEQ_CTRL_5_1 (WSID_EXT_BASE+0x00000108) #define ADR_TX_ACK_POLICY_5_2 (WSID_EXT_BASE+0x0000010c) #define ADR_TX_SEQ_CTRL_5_2 (WSID_EXT_BASE+0x00000110) #define ADR_TX_ACK_POLICY_5_3 (WSID_EXT_BASE+0x00000114) #define ADR_TX_SEQ_CTRL_5_3 (WSID_EXT_BASE+0x00000118) #define ADR_TX_ACK_POLICY_5_4 (WSID_EXT_BASE+0x0000011c) #define ADR_TX_SEQ_CTRL_5_4 (WSID_EXT_BASE+0x00000120) #define ADR_TX_ACK_POLICY_5_5 (WSID_EXT_BASE+0x00000124) #define ADR_TX_SEQ_CTRL_5_5 (WSID_EXT_BASE+0x00000128) #define ADR_TX_ACK_POLICY_5_6 (WSID_EXT_BASE+0x0000012c) #define ADR_TX_SEQ_CTRL_5_6 (WSID_EXT_BASE+0x00000130) #define ADR_TX_ACK_POLICY_5_7 (WSID_EXT_BASE+0x00000134) #define ADR_TX_SEQ_CTRL_5_7 (WSID_EXT_BASE+0x00000138) #define ADR_WSID6 (WSID_EXT_BASE+0x00000140) #define ADR_PEER_MAC6_0 (WSID_EXT_BASE+0x00000144) #define ADR_PEER_MAC6_1 (WSID_EXT_BASE+0x00000148) #define ADR_TX_ACK_POLICY_6_0 (WSID_EXT_BASE+0x0000014c) #define ADR_TX_SEQ_CTRL_6_0 (WSID_EXT_BASE+0x00000150) #define ADR_TX_ACK_POLICY_6_1 (WSID_EXT_BASE+0x00000154) #define ADR_TX_SEQ_CTRL_6_1 (WSID_EXT_BASE+0x00000158) #define ADR_TX_ACK_POLICY_6_2 (WSID_EXT_BASE+0x0000015c) #define ADR_TX_SEQ_CTRL_6_2 (WSID_EXT_BASE+0x00000160) #define ADR_TX_ACK_POLICY_6_3 (WSID_EXT_BASE+0x00000164) #define ADR_TX_SEQ_CTRL_6_3 (WSID_EXT_BASE+0x00000168) #define ADR_TX_ACK_POLICY_6_4 (WSID_EXT_BASE+0x0000016c) #define ADR_TX_SEQ_CTRL_6_4 (WSID_EXT_BASE+0x00000170) #define ADR_TX_ACK_POLICY_6_5 (WSID_EXT_BASE+0x00000174) #define ADR_TX_SEQ_CTRL_6_5 (WSID_EXT_BASE+0x00000178) #define ADR_TX_ACK_POLICY_6_6 (WSID_EXT_BASE+0x0000017c) #define ADR_TX_SEQ_CTRL_6_6 (WSID_EXT_BASE+0x00000180) #define ADR_TX_ACK_POLICY_6_7 (WSID_EXT_BASE+0x00000184) #define ADR_TX_SEQ_CTRL_6_7 (WSID_EXT_BASE+0x00000188) #define ADR_WSID7 (WSID_EXT_BASE+0x00000190) #define ADR_PEER_MAC7_0 (WSID_EXT_BASE+0x00000194) #define ADR_PEER_MAC7_1 (WSID_EXT_BASE+0x00000198) #define ADR_TX_ACK_POLICY_7_0 (WSID_EXT_BASE+0x0000019c) #define ADR_TX_SEQ_CTRL_7_0 (WSID_EXT_BASE+0x000001a0) #define ADR_TX_ACK_POLICY_7_1 (WSID_EXT_BASE+0x000001a4) #define ADR_TX_SEQ_CTRL_7_1 (WSID_EXT_BASE+0x000001a8) #define ADR_TX_ACK_POLICY_7_2 (WSID_EXT_BASE+0x000001ac) #define ADR_TX_SEQ_CTRL_7_2 (WSID_EXT_BASE+0x000001b0) #define ADR_TX_ACK_POLICY_7_3 (WSID_EXT_BASE+0x000001b4) #define ADR_TX_SEQ_CTRL_7_3 (WSID_EXT_BASE+0x000001b8) #define ADR_TX_ACK_POLICY_7_4 (WSID_EXT_BASE+0x000001bc) #define ADR_TX_SEQ_CTRL_7_4 (WSID_EXT_BASE+0x000001c0) #define ADR_TX_ACK_POLICY_7_5 (WSID_EXT_BASE+0x000001c4) #define ADR_TX_SEQ_CTRL_7_5 (WSID_EXT_BASE+0x000001c8) #define ADR_TX_ACK_POLICY_7_6 (WSID_EXT_BASE+0x000001cc) #define ADR_TX_SEQ_CTRL_7_6 (WSID_EXT_BASE+0x000001d0) #define ADR_TX_ACK_POLICY_7_7 (WSID_EXT_BASE+0x000001d4) #define ADR_TX_SEQ_CTRL_7_7 (WSID_EXT_BASE+0x000001d8) // RF_REG #define ADR_GEMINIA_3_WIRE_REGISTER (RF_REG_BASE+0x00b0a000) #define ADR_GEMINIA_MANUAL_ENABLE_REGISTER (RF_REG_BASE+0x00b0a004) #define ADR_GEMINIA_CALIBRATION_TEST_REGISTER (RF_REG_BASE+0x00b0a008) #define ADR_GEMINIA_LDO_REGISTER (RF_REG_BASE+0x00b0a00c) #define ADR_GEMINIA_WIFI_RX_FILTER_REGISTER (RF_REG_BASE+0x00b0a010) #define ADR_GEMINIA_BT_RX_FILTER_REGISTER (RF_REG_BASE+0x00b0a014) #define ADR_GEMINIA_RX_REGISTER (RF_REG_BASE+0x00b0a018) #define ADR_GEMINIA_WBT_TX_FE_REGISTER (RF_REG_BASE+0x00b0a01c) #define ADR_GEMINIA_WBT_TX_PA_REGISTER (RF_REG_BASE+0x00b0a020) #define ADR_GEMINIA_TX_REGISTER (RF_REG_BASE+0x00b0a024) #define ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER (RF_REG_BASE+0x00b0a028) #define ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER (RF_REG_BASE+0x00b0a02c) #define ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER (RF_REG_BASE+0x00b0a030) #define ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00b0a034) #define ADR_GEMINIA_BT_RX_FE_HG_REGISTER (RF_REG_BASE+0x00b0a038) #define ADR_GEMINIA_BT_RX_FE_MG_REGISTER (RF_REG_BASE+0x00b0a03c) #define ADR_GEMINIA_BT_RX_FE_LG_REGISTER (RF_REG_BASE+0x00b0a040) #define ADR_GEMINIA_BT_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00b0a044) #define ADR_GEMINIA_RX_ADC_REGISTER (RF_REG_BASE+0x00b0a048) #define ADR_GEMINIA_WIFI_TX_DAC_REGISTER (RF_REG_BASE+0x00b0a04c) #define ADR_GEMINIA_BT_TX_DAC_REGISTER (RF_REG_BASE+0x00b0a050) #define ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER (RF_REG_BASE+0x00b0a054) #define ADR_GEMINIA_SX_LDO_REGISTER (RF_REG_BASE+0x00b0a058) #define ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS (RF_REG_BASE+0x00b0a05c) #define ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE (RF_REG_BASE+0x00b0a060) #define ADR_GEMINIA_SYN_PFD_CHP_ (RF_REG_BASE+0x00b0a064) #define ADR_GEMINIA_SYN_LPF (RF_REG_BASE+0x00b0a068) #define ADR_GEMINIA_SYN_VCO (RF_REG_BASE+0x00b0a06c) #define ADR_GEMINIA_SYN_VCOBF (RF_REG_BASE+0x00b0a070) #define ADR_GEMINIA_SYN_DIV_SDM (RF_REG_BASE+0x00b0a074) #define ADR_GEMINIA_SYN_SBCAL (RF_REG_BASE+0x00b0a078) #define ADR_GEMINIA_SYN_AAC (RF_REG_BASE+0x00b0a07c) #define ADR_GEMINIA_SYN_TTL (RF_REG_BASE+0x00b0a080) #define ADR_GEMINIA_DPLL_TOP_REGISTER (RF_REG_BASE+0x00b0a084) #define ADR_GEMINIA_DPLL_CKT_REGISTER (RF_REG_BASE+0x00b0a088) #define ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS (RF_REG_BASE+0x00b0a08c) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00b0a090) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00b0a094) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00b0a098) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00b0a09c) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00b0a0a0) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00b0a0a4) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00b0a0a8) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00b0a0ac) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00b0a0b0) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00b0a0b4) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00b0a0b8) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00b0a0bc) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00b0a0c0) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00b0a0c4) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00b0a0c8) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00b0a0cc) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17 (RF_REG_BASE+0x00b0a0d0) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18 (RF_REG_BASE+0x00b0a0d4) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19 (RF_REG_BASE+0x00b0a0d8) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20 (RF_REG_BASE+0x00b0a0dc) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21 (RF_REG_BASE+0x00b0a0e0) #define ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22 (RF_REG_BASE+0x00b0a0e4) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00b0a0e8) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00b0a0ec) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00b0a0f0) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00b0a0f4) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00b0a0f8) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00b0a0fc) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00b0a100) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00b0a104) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00b0a108) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00b0a10c) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00b0a110) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00b0a114) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00b0a118) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00b0a11c) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00b0a120) #define ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00b0a124) #define ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1 (RF_REG_BASE+0x00b0a128) #define ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER (RF_REG_BASE+0x00b0a12c) #define ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER (RF_REG_BASE+0x00b0a130) #define ADR_GEMINIA_CALIBRATION_TIMER_REGISTER (RF_REG_BASE+0x00b0a134) #define ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0 (RF_REG_BASE+0x00b0a138) #define ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1 (RF_REG_BASE+0x00b0a13c) #define ADR_GEMINIA_TRX_DUMMY_REGISTER (RF_REG_BASE+0x00b0a140) #define ADR_GEMINIA_SX_DUMMY_REGISTER (RF_REG_BASE+0x00b0a144) #define ADR_GEMINIA_READ_ONLY_FLAGS_ADC (RF_REG_BASE+0x00b0a148) #define ADR_GEMINIA_READ_ONLY_FLAGS_SX1 (RF_REG_BASE+0x00b0a14c) #define ADR_GEMINIA_READ_ONLY_FLAGS_SX2 (RF_REG_BASE+0x00b0a150) #define ADR_GEMINIA_DIGITAL_ADD_ON_R0 (RF_REG_BASE+0x00b0a540) #define ADR_GEMINIA_DIGITAL_ADD_ON_R1 (RF_REG_BASE+0x00b0a544) #define ADR_GEMINIA_DIGITAL_ADD_ON_R2 (RF_REG_BASE+0x00b0a548) #define ADR_GEMINIA_DIGITAL_ADD_ON_R3 (RF_REG_BASE+0x00b0a54c) #define ADR_GEMINIA_DIGITAL_ADD_ON_R4 (RF_REG_BASE+0x00b0a550) #define ADR_GEMINIA_DIGITAL_ADD_ON_R5 (RF_REG_BASE+0x00b0a554) #define ADR_GEMINIA_DIGITAL_ADD_ON_R6 (RF_REG_BASE+0x00b0a558) #define ADR_GEMINIA_TX_UP8X_COEF_R0 (RF_REG_BASE+0x00b0a55c) #define ADR_GEMINIA_TX_UP8X_COEF_R1 (RF_REG_BASE+0x00b0a560) #define ADR_GEMINIA_TX_UP8X_COEF_R2 (RF_REG_BASE+0x00b0a564) #define ADR_GEMINIA_TX_UP8X_COEF_R3 (RF_REG_BASE+0x00b0a568) #define ADR_GEMINIA_TX_UP8X_COEF_R4 (RF_REG_BASE+0x00b0a56c) #define ADR_GEMINIA_TX_UP8X_COEF_R5 (RF_REG_BASE+0x00b0a570) #define ADR_GEMINIA_RF_D_CAL_TOP_R0 (RF_REG_BASE+0x00b0a574) #define ADR_GEMINIA_RF_D_CAL_TOP_R1 (RF_REG_BASE+0x00b0a578) #define ADR_GEMINIA_RF_D_CAL_TOP_R2 (RF_REG_BASE+0x00b0a57c) #define ADR_GEMINIA_RF_D_CAL_TOP_R3 (RF_REG_BASE+0x00b0a580) #define ADR_GEMINIA_PMU_REG_1 (RF_REG_BASE+0x00b0b000) #define ADR_GEMINIA_PMU_REG_2 (RF_REG_BASE+0x00b0b004) #define ADR_GEMINIA_PMU_REG_3 (RF_REG_BASE+0x00b0b008) #define ADR_GEMINIA_PMU_REG_4 (RF_REG_BASE+0x00b0b00c) #define ADR_GEMINIA_PMU_REG_5 (RF_REG_BASE+0x00b0b010) #define ADR_GEMINIA_PMU_REG_6 (RF_REG_BASE+0x00b0b014) #define ADR_GEMINIA_PMU_BT_CLK (RF_REG_BASE+0x00b0b018) #define ADR_GEMINIA_PMU_SLEEP_REG (RF_REG_BASE+0x00b0b01c) #define ADR_GEMINIA_PMU_RTC_REG_0 (RF_REG_BASE+0x00b0b020) #define ADR_GEMINIA_PMU_RTC_REG_1 (RF_REG_BASE+0x00b0b024) #define ADR_GEMINIA_PMU_RTC_REG_2 (RF_REG_BASE+0x00b0b028) #define ADR_GEMINIA_PMU_RTC_REG_3 (RF_REG_BASE+0x00b0b02c) #define ADR_GEMINIA_PMU_FDB_REG_0 (RF_REG_BASE+0x00b0b040) #define ADR_GEMINIA_IO_REG_0 (RF_REG_BASE+0x00b0b060) #define ADR_GEMINIA_IO_REG_1 (RF_REG_BASE+0x00b0b064) #define ADR_GEMINIA_IO_REG_2 (RF_REG_BASE+0x00b0b068) #define ADR_GEMINIA_MCU_REG_0 (RF_REG_BASE+0x00b0b06c) #define ADR_GEMINIA_PMU_RAM_00 (RF_REG_BASE+0x00b0b080) #define ADR_GEMINIA_PMU_RAM_01 (RF_REG_BASE+0x00b0b084) #define ADR_GEMINIA_PMU_RAM_02 (RF_REG_BASE+0x00b0b088) #define ADR_GEMINIA_PMU_RAM_03 (RF_REG_BASE+0x00b0b08c) #define ADR_GEMINIA_PMU_RAM_04 (RF_REG_BASE+0x00b0b090) #define ADR_GEMINIA_PMU_RAM_05 (RF_REG_BASE+0x00b0b094) #define ADR_GEMINIA_PMU_RAM_06 (RF_REG_BASE+0x00b0b098) #define ADR_GEMINIA_PMU_RAM_07 (RF_REG_BASE+0x00b0b09c) #define ADR_GEMINIA_PMU_RAM_08 (RF_REG_BASE+0x00b0b0a0) #define ADR_GEMINIA_PMU_RAM_09 (RF_REG_BASE+0x00b0b0a4) #define ADR_GEMINIA_PMU_RAM_10 (RF_REG_BASE+0x00b0b0a8) #define ADR_GEMINIA_PMU_RAM_11 (RF_REG_BASE+0x00b0b0ac) #define ADR_GEMINIA_PMU_RAM_12 (RF_REG_BASE+0x00b0b0b0) #define ADR_GEMINIA_PMU_RAM_13 (RF_REG_BASE+0x00b0b0b4) #define ADR_GEMINIA_PMU_RAM_14 (RF_REG_BASE+0x00b0b0b8) #define ADR_GEMINIA_PMU_RAM_15 (RF_REG_BASE+0x00b0b0bc) #define ADR_GEMINIA_PMU_RAM_16 (RF_REG_BASE+0x00b0b0c0) #define ADR_GEMINIA_PMU_RAM_17 (RF_REG_BASE+0x00b0b0c4) #define ADR_GEMINIA_PMU_RAM_18 (RF_REG_BASE+0x00b0b0c8) #define ADR_GEMINIA_PMU_RAM_19 (RF_REG_BASE+0x00b0b0cc) #define ADR_GEMINIA_PMU_RAM_20 (RF_REG_BASE+0x00b0b0d0) #define ADR_GEMINIA_PMU_RAM_21 (RF_REG_BASE+0x00b0b0d4) #define ADR_GEMINIA_PMU_RAM_22 (RF_REG_BASE+0x00b0b0d8) #define ADR_GEMINIA_PMU_RAM_23 (RF_REG_BASE+0x00b0b0dc) #define ADR_GEMINIA_PMU_RAM_24 (RF_REG_BASE+0x00b0b0e0) #define ADR_GEMINIA_PMU_RAM_25 (RF_REG_BASE+0x00b0b0e4) #define ADR_GEMINIA_PMU_RAM_26 (RF_REG_BASE+0x00b0b0e8) #define ADR_GEMINIA_PMU_RAM_27 (RF_REG_BASE+0x00b0b0ec) #define ADR_GEMINIA_PMU_RAM_28 (RF_REG_BASE+0x00b0b0f0) #define ADR_GEMINIA_PMU_RAM_29 (RF_REG_BASE+0x00b0b0f4) #define ADR_GEMINIA_PMU_RAM_30 (RF_REG_BASE+0x00b0b0f8) #define ADR_GEMINIA_PMU_RAM_31 (RF_REG_BASE+0x00b0b0fc) #define ADR_TURISMO_TRX_MODE_REGISTER (RF_REG_BASE+0x00c0a400) #define ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER (RF_REG_BASE+0x00c0a404) #define ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER (RF_REG_BASE+0x00c0a408) #define ADR_TURISMO_TRX_2_4G_LDO_REGISTER (RF_REG_BASE+0x00c0a40c) #define ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER (RF_REG_BASE+0x00c0a410) #define ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER (RF_REG_BASE+0x00c0a414) #define ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER (RF_REG_BASE+0x00c0a418) #define ADR_TURISMO_TRX_2_4G_RX_REGISTER (RF_REG_BASE+0x00c0a41c) #define ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER (RF_REG_BASE+0x00c0a420) #define ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER (RF_REG_BASE+0x00c0a424) #define ADR_TURISMO_TRX_2_4G_TX_REGISTER (RF_REG_BASE+0x00c0a428) #define ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER (RF_REG_BASE+0x00c0a42c) #define ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER (RF_REG_BASE+0x00c0a430) #define ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER (RF_REG_BASE+0x00c0a434) #define ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00c0a438) #define ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER (RF_REG_BASE+0x00c0a43c) #define ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER (RF_REG_BASE+0x00c0a440) #define ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER (RF_REG_BASE+0x00c0a444) #define ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00c0a448) #define ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER (RF_REG_BASE+0x00c0a44c) #define ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER (RF_REG_BASE+0x00c0a450) #define ADR_TURISMO_TRX_BT_TX_DAC_REGISTER (RF_REG_BASE+0x00c0a454) #define ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER (RF_REG_BASE+0x00c0a458) #define ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER (RF_REG_BASE+0x00c0a45c) #define ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS (RF_REG_BASE+0x00c0a460) #define ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE (RF_REG_BASE+0x00c0a464) #define ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_ (RF_REG_BASE+0x00c0a468) #define ADR_TURISMO_TRX_SX_2_4GB_LPF (RF_REG_BASE+0x00c0a46c) #define ADR_TURISMO_TRX_SX_2_4GB_VCO (RF_REG_BASE+0x00c0a470) #define ADR_TURISMO_TRX_SX_2_4GB_VCOBF (RF_REG_BASE+0x00c0a474) #define ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM (RF_REG_BASE+0x00c0a478) #define ADR_TURISMO_TRX_SX_2_4GB_SBCAL (RF_REG_BASE+0x00c0a47c) #define ADR_TURISMO_TRX_SX_2_4GB_AAC (RF_REG_BASE+0x00c0a480) #define ADR_TURISMO_TRX_SX_2_4GB_TTL (RF_REG_BASE+0x00c0a484) #define ADR_TURISMO_TRX_DPLL_TOP_REGISTER (RF_REG_BASE+0x00c0a488) #define ADR_TURISMO_TRX_DPLL_CKT_REGISTER (RF_REG_BASE+0x00c0a48c) #define ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS (RF_REG_BASE+0x00c0a490) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00c0a494) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00c0a498) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00c0a49c) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00c0a4a0) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00c0a4a4) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00c0a4a8) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00c0a4ac) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00c0a4b0) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00c0a4b4) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00c0a4b8) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00c0a4bc) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00c0a4c0) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00c0a4c4) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00c0a4c8) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00c0a4cc) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00c0a4d0) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17 (RF_REG_BASE+0x00c0a4d4) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18 (RF_REG_BASE+0x00c0a4d8) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19 (RF_REG_BASE+0x00c0a4dc) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20 (RF_REG_BASE+0x00c0a4e0) #define ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21 (RF_REG_BASE+0x00c0a4e4) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00c0a4e8) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00c0a4ec) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00c0a4f0) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00c0a4f4) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00c0a4f8) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00c0a4fc) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00c0a500) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00c0a504) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00c0a508) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00c0a50c) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00c0a510) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00c0a514) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00c0a518) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00c0a51c) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00c0a520) #define ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00c0a524) #define ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1 (RF_REG_BASE+0x00c0a528) #define ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER (RF_REG_BASE+0x00c0a52c) #define ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER (RF_REG_BASE+0x00c0a530) #define ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER (RF_REG_BASE+0x00c0a534) #define ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0 (RF_REG_BASE+0x00c0a538) #define ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1 (RF_REG_BASE+0x00c0a53c) #define ADR_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER (RF_REG_BASE+0x00c0a540) #define ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC (RF_REG_BASE+0x00c0a544) #define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1 (RF_REG_BASE+0x00c0a548) #define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2 (RF_REG_BASE+0x00c0a54c) #define ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER (RF_REG_BASE+0x00c0a550) #define ADR_TURISMO_TRX_5G_LDO_REGISTER (RF_REG_BASE+0x00c0a554) #define ADR_TURISMO_TRX_5G_RX_REGISTER1 (RF_REG_BASE+0x00c0a558) #define ADR_TURISMO_TRX_5G_RX_REGISTER2 (RF_REG_BASE+0x00c0a55c) #define ADR_TURISMO_TRX_5G_TX_FE_REGISTER (RF_REG_BASE+0x00c0a560) #define ADR_TURISMO_TRX_5G_TX_REGISTER (RF_REG_BASE+0x00c0a564) #define ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER (RF_REG_BASE+0x00c0a568) #define ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER (RF_REG_BASE+0x00c0a56c) #define ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER (RF_REG_BASE+0x00c0a570) #define ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER (RF_REG_BASE+0x00c0a574) #define ADR_TURISMO_TRX_5G_TX_DAC_REGISTER (RF_REG_BASE+0x00c0a578) #define ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS (RF_REG_BASE+0x00c0a57c) #define ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE (RF_REG_BASE+0x00c0a580) #define ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER (RF_REG_BASE+0x00c0a584) #define ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER (RF_REG_BASE+0x00c0a588) #define ADR_TURISMO_TRX_SX_5GB_PFD_CHP_ (RF_REG_BASE+0x00c0a58c) #define ADR_TURISMO_TRX_SX_5GB_LPF_TTL (RF_REG_BASE+0x00c0a590) #define ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN (RF_REG_BASE+0x00c0a594) #define ADR_TURISMO_TRX_SX_5GB_DIV_SDM (RF_REG_BASE+0x00c0a598) #define ADR_TURISMO_TRX_SX_5GB_SBCAL (RF_REG_BASE+0x00c0a59c) #define ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION (RF_REG_BASE+0x00c0a5a0) #define ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION (RF_REG_BASE+0x00c0a5a4) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1 (RF_REG_BASE+0x00c0a5a8) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2 (RF_REG_BASE+0x00c0a5ac) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3 (RF_REG_BASE+0x00c0a5b0) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4 (RF_REG_BASE+0x00c0a5b4) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5 (RF_REG_BASE+0x00c0a5b8) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6 (RF_REG_BASE+0x00c0a5bc) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7 (RF_REG_BASE+0x00c0a5c0) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8 (RF_REG_BASE+0x00c0a5c4) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9 (RF_REG_BASE+0x00c0a5c8) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10 (RF_REG_BASE+0x00c0a5cc) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11 (RF_REG_BASE+0x00c0a5d0) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12 (RF_REG_BASE+0x00c0a5d4) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13 (RF_REG_BASE+0x00c0a5d8) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14 (RF_REG_BASE+0x00c0a5dc) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15 (RF_REG_BASE+0x00c0a5e0) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16 (RF_REG_BASE+0x00c0a5e4) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17 (RF_REG_BASE+0x00c0a5e8) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18 (RF_REG_BASE+0x00c0a5ec) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19 (RF_REG_BASE+0x00c0a5f0) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20 (RF_REG_BASE+0x00c0a5f4) #define ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21 (RF_REG_BASE+0x00c0a5f8) #define ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1 (RF_REG_BASE+0x00c0a5fc) #define ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER (RF_REG_BASE+0x00c0a600) #define ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER (RF_REG_BASE+0x00c0a604) #define ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER (RF_REG_BASE+0x00c0a608) #define ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1 (RF_REG_BASE+0x00c0a60c) #define ADR_TURISMO_TRX_5G_TRX_DUMMY_REGISTER (RF_REG_BASE+0x00c0a610) #define ADR_TURISMO_TRX_SX_5GB_DUMMY_REGISTER (RF_REG_BASE+0x00c0a614) #define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1 (RF_REG_BASE+0x00c0a618) #define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2 (RF_REG_BASE+0x00c0a61c) #define ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3 (RF_REG_BASE+0x00c0a620) #define ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL (RF_REG_BASE+0x00c0a624) #define ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL (RF_REG_BASE+0x00c0a628) #define ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL (RF_REG_BASE+0x00c0a62c) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_0 (RF_REG_BASE+0x00c0a800) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_1 (RF_REG_BASE+0x00c0a804) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_2 (RF_REG_BASE+0x00c0a808) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_3 (RF_REG_BASE+0x00c0a80c) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_4 (RF_REG_BASE+0x00c0a810) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_5 (RF_REG_BASE+0x00c0a814) #define ADR_TURISMO_TRX_DIGITAL_ADD_ON_6 (RF_REG_BASE+0x00c0a818) #define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00 (RF_REG_BASE+0x00c0a81c) #define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01 (RF_REG_BASE+0x00c0a820) #define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02 (RF_REG_BASE+0x00c0a824) #define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03 (RF_REG_BASE+0x00c0a828) #define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04 (RF_REG_BASE+0x00c0a82c) #define ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05 (RF_REG_BASE+0x00c0a830) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_0 (RF_REG_BASE+0x00c0a834) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_1 (RF_REG_BASE+0x00c0a838) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_2 (RF_REG_BASE+0x00c0a83c) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_3 (RF_REG_BASE+0x00c0a840) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_4 (RF_REG_BASE+0x00c0a844) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_5 (RF_REG_BASE+0x00c0a848) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_6 (RF_REG_BASE+0x00c0a84c) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_7 (RF_REG_BASE+0x00c0a850) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_8 (RF_REG_BASE+0x00c0a854) #define ADR_TURISMO_TRX_RF_D_CAL_TOP_9 (RF_REG_BASE+0x00c0a858) #define ADR_TURISMO_TRX_HS3W_CTRL1 (RF_REG_BASE+0x00c0a880) #define ADR_TURISMO_TRX_HS3W_CTRL2 (RF_REG_BASE+0x00c0a884) #define ADR_TURISMO_TRX_HS3W_CTRL3 (RF_REG_BASE+0x00c0a888) #define ADR_TURISMO_TRX_RF_D_MODE_CTRL (RF_REG_BASE+0x00c0a88c) #define ADR_TURISMO_TRX_RX_DC_CAL_RESULT (RF_REG_BASE+0x00c0a8c0) #define ADR_TURISMO_TRX_PMU_REG_1 (RF_REG_BASE+0x00c0b000) #define ADR_TURISMO_TRX_PMU_REG_2 (RF_REG_BASE+0x00c0b004) #define ADR_TURISMO_TRX_PMU_REG_3 (RF_REG_BASE+0x00c0b008) #define ADR_TURISMO_TRX_PMU_REG_4 (RF_REG_BASE+0x00c0b00c) #define ADR_TURISMO_TRX_PMU_REG_5 (RF_REG_BASE+0x00c0b010) #define ADR_TURISMO_TRX_PMU_REG_6 (RF_REG_BASE+0x00c0b014) #define ADR_TURISMO_TRX_PMU_SLEEP_REG_1 (RF_REG_BASE+0x00c0b018) #define ADR_TURISMO_TRX_PMU_SLEEP_REG_2 (RF_REG_BASE+0x00c0b01c) #define ADR_TURISMO_TRX_PMU_RTC_REG_0 (RF_REG_BASE+0x00c0b020) #define ADR_TURISMO_TRX_PMU_RTC_REG_1 (RF_REG_BASE+0x00c0b024) #define ADR_TURISMO_TRX_PMU_RTC_REG_2 (RF_REG_BASE+0x00c0b028) #define ADR_TURISMO_TRX_PMU_RTC_REG_3 (RF_REG_BASE+0x00c0b02c) #define ADR_TURISMO_TRX_PMU_CTRL_REG (RF_REG_BASE+0x00c0b03c) #define ADR_TURISMO_TRX_PMU_STATE_REG (RF_REG_BASE+0x00c0b044) #define ADR_TURISMO_TRX_PMU_BT_CLK (RF_REG_BASE+0x00c0b048) #define ADR_TURISMO_TRX_IO_REG_0 (RF_REG_BASE+0x00c0b060) #define ADR_TURISMO_TRX_IO_REG_1 (RF_REG_BASE+0x00c0b064) #define ADR_TURISMO_TRX_IO_REG_2 (RF_REG_BASE+0x00c0b068) #define ADR_TURISMO_TRX_MCU_REG_0 (RF_REG_BASE+0x00c0b06c) #define ADR_TURISMO_TRX_PMU_RAM_00 (RF_REG_BASE+0x00c0b080) #define ADR_TURISMO_TRX_PMU_RAM_01 (RF_REG_BASE+0x00c0b084) #define ADR_TURISMO_TRX_PMU_RAM_02 (RF_REG_BASE+0x00c0b088) #define ADR_TURISMO_TRX_PMU_RAM_03 (RF_REG_BASE+0x00c0b08c) #define ADR_TURISMO_TRX_PMU_RAM_04 (RF_REG_BASE+0x00c0b090) #define ADR_TURISMO_TRX_PMU_RAM_05 (RF_REG_BASE+0x00c0b094) #define ADR_TURISMO_TRX_PMU_RAM_06 (RF_REG_BASE+0x00c0b098) #define ADR_TURISMO_TRX_PMU_RAM_07 (RF_REG_BASE+0x00c0b09c) #define ADR_TURISMO_TRX_PMU_RAM_08 (RF_REG_BASE+0x00c0b0a0) #define ADR_TURISMO_TRX_PMU_RAM_09 (RF_REG_BASE+0x00c0b0a4) #define ADR_TURISMO_TRX_PMU_RAM_10 (RF_REG_BASE+0x00c0b0a8) #define ADR_TURISMO_TRX_PMU_RAM_11 (RF_REG_BASE+0x00c0b0ac) #define ADR_TURISMO_TRX_PMU_RAM_12 (RF_REG_BASE+0x00c0b0b0) #define ADR_TURISMO_TRX_PMU_RAM_13 (RF_REG_BASE+0x00c0b0b4) #define ADR_TURISMO_TRX_PMU_RAM_14 (RF_REG_BASE+0x00c0b0b8) #define ADR_TURISMO_TRX_PMU_RAM_15 (RF_REG_BASE+0x00c0b0bc) #define ADR_TURISMO_TRX_PMU_RAM_16 (RF_REG_BASE+0x00c0b0c0) #define ADR_TURISMO_TRX_PMU_RAM_17 (RF_REG_BASE+0x00c0b0c4) #define ADR_TURISMO_TRX_PMU_RAM_18 (RF_REG_BASE+0x00c0b0c8) #define ADR_TURISMO_TRX_PMU_RAM_19 (RF_REG_BASE+0x00c0b0cc) #define ADR_TURISMO_TRX_PMU_RAM_20 (RF_REG_BASE+0x00c0b0d0) #define ADR_TURISMO_TRX_PMU_RAM_21 (RF_REG_BASE+0x00c0b0d4) #define ADR_TURISMO_TRX_PMU_RAM_22 (RF_REG_BASE+0x00c0b0d8) #define ADR_TURISMO_TRX_PMU_RAM_23 (RF_REG_BASE+0x00c0b0dc) #define ADR_TURISMO_TRX_PMU_RAM_24 (RF_REG_BASE+0x00c0b0e0) #define ADR_TURISMO_TRX_PMU_RAM_25 (RF_REG_BASE+0x00c0b0e4) #define ADR_TURISMO_TRX_PMU_RAM_26 (RF_REG_BASE+0x00c0b0e8) #define ADR_TURISMO_TRX_PMU_RAM_27 (RF_REG_BASE+0x00c0b0ec) #define ADR_TURISMO_TRX_PMU_RAM_28 (RF_REG_BASE+0x00c0b0f0) #define ADR_TURISMO_TRX_PMU_RAM_29 (RF_REG_BASE+0x00c0b0f4) #define ADR_TURISMO_TRX_PMU_RAM_30 (RF_REG_BASE+0x00c0b0f8) #define ADR_TURISMO_TRX_PMU_RAM_31 (RF_REG_BASE+0x00c0b0fc) // CSR_TU_RF #define ADR_MODE_REGISTER (CSR_TU_RF_BASE+0x00000400) #define ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER (CSR_TU_RF_BASE+0x00000404) #define ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER (CSR_TU_RF_BASE+0x00000408) #define ADR_2_4G_LDO_REGISTER (CSR_TU_RF_BASE+0x0000040c) #define ADR_WIFI_HT20_RX_FILTER_REGISTER (CSR_TU_RF_BASE+0x00000410) #define ADR_WIFI_HT40_RX_FILTER_REGISTER (CSR_TU_RF_BASE+0x00000414) #define ADR_BT_RX_FILTER_REGISTER (CSR_TU_RF_BASE+0x00000418) #define ADR_2_4G_RX_REGISTER (CSR_TU_RF_BASE+0x0000041c) #define ADR_2_4G_TX_FE_REGISTER (CSR_TU_RF_BASE+0x00000420) #define ADR_2_4G_TX_PA_REGISTER (CSR_TU_RF_BASE+0x00000424) #define ADR_2_4G_TX_REGISTER (CSR_TU_RF_BASE+0x00000428) #define ADR_2_4G_RX_FE_HG_REGISTER (CSR_TU_RF_BASE+0x0000042c) #define ADR_2_4G_RX_FE_MG_REGISTER (CSR_TU_RF_BASE+0x00000430) #define ADR_2_4G_RX_FE_LG_REGISTER (CSR_TU_RF_BASE+0x00000434) #define ADR_2_4G_RX_FE_ULG_REGISTER (CSR_TU_RF_BASE+0x00000438) #define ADR_BT_RX_FE_HG_REGISTER (CSR_TU_RF_BASE+0x0000043c) #define ADR_BT_RX_FE_MG_REGISTER (CSR_TU_RF_BASE+0x00000440) #define ADR_BT_RX_FE_LG_REGISTER (CSR_TU_RF_BASE+0x00000444) #define ADR_BT_RX_FE_ULG_REGISTER (CSR_TU_RF_BASE+0x00000448) #define ADR_WBT_RX_ADC_REGISTER (CSR_TU_RF_BASE+0x0000044c) #define ADR_WIFI_TX_DAC_REGISTER (CSR_TU_RF_BASE+0x00000450) #define ADR_BT_TX_DAC_REGISTER (CSR_TU_RF_BASE+0x00000454) #define ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER (CSR_TU_RF_BASE+0x00000458) #define ADR_SX_2_4G_LDO_REGISTER (CSR_TU_RF_BASE+0x0000045c) #define ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS (CSR_TU_RF_BASE+0x00000460) #define ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE (CSR_TU_RF_BASE+0x00000464) #define ADR_SX_2_4GB_PFD_CHP_ (CSR_TU_RF_BASE+0x00000468) #define ADR_SX_2_4GB_LPF (CSR_TU_RF_BASE+0x0000046c) #define ADR_SX_2_4GB_VCO (CSR_TU_RF_BASE+0x00000470) #define ADR_SX_2_4GB_VCOBF (CSR_TU_RF_BASE+0x00000474) #define ADR_SX_2_4GB_DIV_SDM (CSR_TU_RF_BASE+0x00000478) #define ADR_SX_2_4GB_SBCAL (CSR_TU_RF_BASE+0x0000047c) #define ADR_SX_2_4GB_AAC (CSR_TU_RF_BASE+0x00000480) #define ADR_SX_2_4GB_TTL (CSR_TU_RF_BASE+0x00000484) #define ADR_DPLL_TOP_REGISTER (CSR_TU_RF_BASE+0x00000488) #define ADR_DPLL_CKT_REGISTER (CSR_TU_RF_BASE+0x0000048c) #define ADR_DPLL_FB_DIVISION__REGISTERS (CSR_TU_RF_BASE+0x00000490) #define ADR_WF_DCOC_IDAC_REGISTER1 (CSR_TU_RF_BASE+0x00000494) #define ADR_WF_DCOC_IDAC_REGISTER2 (CSR_TU_RF_BASE+0x00000498) #define ADR_WF_DCOC_IDAC_REGISTER3 (CSR_TU_RF_BASE+0x0000049c) #define ADR_WF_DCOC_IDAC_REGISTER4 (CSR_TU_RF_BASE+0x000004a0) #define ADR_WF_DCOC_IDAC_REGISTER5 (CSR_TU_RF_BASE+0x000004a4) #define ADR_WF_DCOC_IDAC_REGISTER6 (CSR_TU_RF_BASE+0x000004a8) #define ADR_WF_DCOC_IDAC_REGISTER7 (CSR_TU_RF_BASE+0x000004ac) #define ADR_WF_DCOC_IDAC_REGISTER8 (CSR_TU_RF_BASE+0x000004b0) #define ADR_WF_DCOC_IDAC_REGISTER9 (CSR_TU_RF_BASE+0x000004b4) #define ADR_WF_DCOC_IDAC_REGISTER10 (CSR_TU_RF_BASE+0x000004b8) #define ADR_WF_DCOC_IDAC_REGISTER11 (CSR_TU_RF_BASE+0x000004bc) #define ADR_WF_DCOC_IDAC_REGISTER12 (CSR_TU_RF_BASE+0x000004c0) #define ADR_WF_DCOC_IDAC_REGISTER13 (CSR_TU_RF_BASE+0x000004c4) #define ADR_WF_DCOC_IDAC_REGISTER14 (CSR_TU_RF_BASE+0x000004c8) #define ADR_WF_DCOC_IDAC_REGISTER15 (CSR_TU_RF_BASE+0x000004cc) #define ADR_WF_DCOC_IDAC_REGISTER16 (CSR_TU_RF_BASE+0x000004d0) #define ADR_WF_DCOC_IDAC_REGISTER17 (CSR_TU_RF_BASE+0x000004d4) #define ADR_WF_DCOC_IDAC_REGISTER18 (CSR_TU_RF_BASE+0x000004d8) #define ADR_WF_DCOC_IDAC_REGISTER19 (CSR_TU_RF_BASE+0x000004dc) #define ADR_WF_DCOC_IDAC_REGISTER20 (CSR_TU_RF_BASE+0x000004e0) #define ADR_WF_DCOC_IDAC_REGISTER21 (CSR_TU_RF_BASE+0x000004e4) #define ADR_BT_DCOC_IDAC_REGISTER1 (CSR_TU_RF_BASE+0x000004e8) #define ADR_BT_DCOC_IDAC_REGISTER2 (CSR_TU_RF_BASE+0x000004ec) #define ADR_BT_DCOC_IDAC_REGISTER3 (CSR_TU_RF_BASE+0x000004f0) #define ADR_BT_DCOC_IDAC_REGISTER4 (CSR_TU_RF_BASE+0x000004f4) #define ADR_BT_DCOC_IDAC_REGISTER5 (CSR_TU_RF_BASE+0x000004f8) #define ADR_BT_DCOC_IDAC_REGISTER6 (CSR_TU_RF_BASE+0x000004fc) #define ADR_BT_DCOC_IDAC_REGISTER7 (CSR_TU_RF_BASE+0x00000500) #define ADR_BT_DCOC_IDAC_REGISTER8 (CSR_TU_RF_BASE+0x00000504) #define ADR_BT_DCOC_IDAC_REGISTER9 (CSR_TU_RF_BASE+0x00000508) #define ADR_BT_DCOC_IDAC_REGISTER10 (CSR_TU_RF_BASE+0x0000050c) #define ADR_BT_DCOC_IDAC_REGISTER11 (CSR_TU_RF_BASE+0x00000510) #define ADR_BT_DCOC_IDAC_REGISTER12 (CSR_TU_RF_BASE+0x00000514) #define ADR_BT_DCOC_IDAC_REGISTER13 (CSR_TU_RF_BASE+0x00000518) #define ADR_BT_DCOC_IDAC_REGISTER14 (CSR_TU_RF_BASE+0x0000051c) #define ADR_BT_DCOC_IDAC_REGISTER15 (CSR_TU_RF_BASE+0x00000520) #define ADR_BT_DCOC_IDAC_REGISTER16 (CSR_TU_RF_BASE+0x00000524) #define ADR_MODE_DECODER_TIMER_REGISTER1 (CSR_TU_RF_BASE+0x00000528) #define ADR_WIFI_T2R_TIMER_REGISTER (CSR_TU_RF_BASE+0x0000052c) #define ADR_WIFI_R2T_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000530) #define ADR_CALIBRATION_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000534) #define ADR_CALIBRATION_GAIN_REGISTER0 (CSR_TU_RF_BASE+0x00000538) #define ADR_CALIBRATION_GAIN_REGISTER1 (CSR_TU_RF_BASE+0x0000053c) #define ADR_2_4G_TRX_DUMMY_REGISTER (CSR_TU_RF_BASE+0x00000540) #define ADR_READ_ONLY_FLAGS_ADC (CSR_TU_RF_BASE+0x00000544) #define ADR_READ_ONLY_FLAGS_SX_2_4GB_1 (CSR_TU_RF_BASE+0x00000548) #define ADR_READ_ONLY_FLAGS_SX_2_4GB_2 (CSR_TU_RF_BASE+0x0000054c) #define ADR_5G_TRX_MANUAL_ENABLE_REGISTER (CSR_TU_RF_BASE+0x00000550) #define ADR_5G_LDO_REGISTER (CSR_TU_RF_BASE+0x00000554) #define ADR_5G_RX_REGISTER1 (CSR_TU_RF_BASE+0x00000558) #define ADR_5G_RX_REGISTER2 (CSR_TU_RF_BASE+0x0000055c) #define ADR_5G_TX_FE_REGISTER (CSR_TU_RF_BASE+0x00000560) #define ADR_5G_TX_REGISTER (CSR_TU_RF_BASE+0x00000564) #define ADR_5G_RX_FE_HG_REGISTER (CSR_TU_RF_BASE+0x00000568) #define ADR_5G_RX_FE_MG_REGISTER (CSR_TU_RF_BASE+0x0000056c) #define ADR_5G_RX_FE_LG_REGISTER (CSR_TU_RF_BASE+0x00000570) #define ADR_5G_RX_FE_ULG_REGISTER (CSR_TU_RF_BASE+0x00000574) #define ADR_5G_TX_DAC_REGISTER (CSR_TU_RF_BASE+0x00000578) #define ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS (CSR_TU_RF_BASE+0x0000057c) #define ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE (CSR_TU_RF_BASE+0x00000580) #define ADR_SX_5GB_ENABLE_TOP_CONTROLLER (CSR_TU_RF_BASE+0x00000584) #define ADR_SX_5GB_LDO_REGISTER (CSR_TU_RF_BASE+0x00000588) #define ADR_SX_5GB_PFD_CHP_ (CSR_TU_RF_BASE+0x0000058c) #define ADR_SX_5GB_LPF_TTL (CSR_TU_RF_BASE+0x00000590) #define ADR_SX_5GB_VCO_LOGEN (CSR_TU_RF_BASE+0x00000594) #define ADR_SX_5GB_DIV_SDM (CSR_TU_RF_BASE+0x00000598) #define ADR_SX_5GB_SBCAL (CSR_TU_RF_BASE+0x0000059c) #define ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION (CSR_TU_RF_BASE+0x000005a0) #define ADR_SX_5GB_LOGEN_CALIBRATION (CSR_TU_RF_BASE+0x000005a4) #define ADR_5G_DCOC_IDAC_REGISTER1 (CSR_TU_RF_BASE+0x000005a8) #define ADR_5G_DCOC_IDAC_REGISTER2 (CSR_TU_RF_BASE+0x000005ac) #define ADR_5G_DCOC_IDAC_REGISTER3 (CSR_TU_RF_BASE+0x000005b0) #define ADR_5G_DCOC_IDAC_REGISTER4 (CSR_TU_RF_BASE+0x000005b4) #define ADR_5G_DCOC_IDAC_REGISTER5 (CSR_TU_RF_BASE+0x000005b8) #define ADR_5G_DCOC_IDAC_REGISTER6 (CSR_TU_RF_BASE+0x000005bc) #define ADR_5G_DCOC_IDAC_REGISTER7 (CSR_TU_RF_BASE+0x000005c0) #define ADR_5G_DCOC_IDAC_REGISTER8 (CSR_TU_RF_BASE+0x000005c4) #define ADR_5G_DCOC_IDAC_REGISTER9 (CSR_TU_RF_BASE+0x000005c8) #define ADR_5G_DCOC_IDAC_REGISTER10 (CSR_TU_RF_BASE+0x000005cc) #define ADR_5G_DCOC_IDAC_REGISTER11 (CSR_TU_RF_BASE+0x000005d0) #define ADR_5G_DCOC_IDAC_REGISTER12 (CSR_TU_RF_BASE+0x000005d4) #define ADR_5G_DCOC_IDAC_REGISTER13 (CSR_TU_RF_BASE+0x000005d8) #define ADR_5G_DCOC_IDAC_REGISTER14 (CSR_TU_RF_BASE+0x000005dc) #define ADR_5G_DCOC_IDAC_REGISTER15 (CSR_TU_RF_BASE+0x000005e0) #define ADR_5G_DCOC_IDAC_REGISTER16 (CSR_TU_RF_BASE+0x000005e4) #define ADR_5G_DCOC_IDAC_REGISTER17 (CSR_TU_RF_BASE+0x000005e8) #define ADR_5G_DCOC_IDAC_REGISTER18 (CSR_TU_RF_BASE+0x000005ec) #define ADR_5G_DCOC_IDAC_REGISTER19 (CSR_TU_RF_BASE+0x000005f0) #define ADR_5G_DCOC_IDAC_REGISTER20 (CSR_TU_RF_BASE+0x000005f4) #define ADR_5G_DCOC_IDAC_REGISTER21 (CSR_TU_RF_BASE+0x000005f8) #define ADR_5G_MODE_DECODER_TIMER_REGISTER1 (CSR_TU_RF_BASE+0x000005fc) #define ADR_5G_T2R_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000600) #define ADR_5G_R2T_TIMER_REGISTER (CSR_TU_RF_BASE+0x00000604) #define ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER (CSR_TU_RF_BASE+0x00000608) #define ADR_5G_CALIBRATION_GAIN_REGISTER1 (CSR_TU_RF_BASE+0x0000060c) #define ADR_5G_TRX_DUMMY_REGISTER (CSR_TU_RF_BASE+0x00000610) #define ADR_SX_5GB_DUMMY_REGISTER (CSR_TU_RF_BASE+0x00000614) #define ADR_READ_ONLY_FLAGS_SX_5GB_1 (CSR_TU_RF_BASE+0x00000618) #define ADR_READ_ONLY_FLAGS_SX_5GB_2 (CSR_TU_RF_BASE+0x0000061c) #define ADR_READ_ONLY_FLAGS_SX_5GB_3 (CSR_TU_RF_BASE+0x00000620) #define ADR_5G_RX_LNA_MATCHING_SCA_CONTROL (CSR_TU_RF_BASE+0x00000624) #define ADR_5G_RX_LNA_LOAD_SCA_CONTROL (CSR_TU_RF_BASE+0x00000628) #define ADR_5G_TX_PGA_CAPSW_CONTROL_I (CSR_TU_RF_BASE+0x0000062c) #define ADR_5G_TX_PGA_CAPSW_CONTROL_II (CSR_TU_RF_BASE+0x00000630) #define ADR_5G_TX_GAIN_PAFB_CONTROL (CSR_TU_RF_BASE+0x00000634) #define ADR_DIGITAL_ADD_ON_0 (CSR_TU_RF_BASE+0x00000800) #define ADR_DIGITAL_ADD_ON_1 (CSR_TU_RF_BASE+0x00000804) #define ADR_DIGITAL_ADD_ON_2 (CSR_TU_RF_BASE+0x00000808) #define ADR_DIGITAL_ADD_ON_3 (CSR_TU_RF_BASE+0x0000080c) #define ADR_DIGITAL_ADD_ON_4 (CSR_TU_RF_BASE+0x00000810) #define ADR_DIGITAL_ADD_ON_5 (CSR_TU_RF_BASE+0x00000814) #define ADR_DIGITAL_ADD_ON_6 (CSR_TU_RF_BASE+0x00000818) #define ADR_RX_RC_VALUE_TUNE (CSR_TU_RF_BASE+0x0000081c) #define ADR_TRX_IQ_COMP_2G (CSR_TU_RF_BASE+0x00000820) #define ADR_TRX_IQ_COMP_5G_0 (CSR_TU_RF_BASE+0x00000824) #define ADR_TRX_IQ_COMP_5G_1 (CSR_TU_RF_BASE+0x00000828) #define ADR_TRX_IQ_COMP_5G_2 (CSR_TU_RF_BASE+0x0000082c) #define ADR_TRX_IQ_COMP_5G_3 (CSR_TU_RF_BASE+0x00000830) #define ADR_RF_D_CAL_TOP_0 (CSR_TU_RF_BASE+0x00000834) #define ADR_RF_D_CAL_TOP_1 (CSR_TU_RF_BASE+0x00000838) #define ADR_RF_D_CAL_TOP_2 (CSR_TU_RF_BASE+0x0000083c) #define ADR_RF_D_CAL_TOP_3 (CSR_TU_RF_BASE+0x00000840) #define ADR_RF_D_CAL_TOP_4 (CSR_TU_RF_BASE+0x00000844) #define ADR_RF_D_CAL_TOP_5 (CSR_TU_RF_BASE+0x00000848) #define ADR_RF_D_CAL_TOP_6 (CSR_TU_RF_BASE+0x0000084c) #define ADR_RF_D_CAL_TOP_7 (CSR_TU_RF_BASE+0x00000850) #define ADR_RF_D_CAL_TOP_8 (CSR_TU_RF_BASE+0x00000854) #define ADR_RF_D_CAL_TOP_9 (CSR_TU_RF_BASE+0x00000858) #define ADR_HS3W_CTRL1 (CSR_TU_RF_BASE+0x00000880) #define ADR_HS3W_CTRL2 (CSR_TU_RF_BASE+0x00000884) #define ADR_HS3W_CTRL3 (CSR_TU_RF_BASE+0x00000888) #define ADR_RF_D_MODE_CTRL (CSR_TU_RF_BASE+0x0000088c) #define ADR_HS3W_READ_OUT_1 (CSR_TU_RF_BASE+0x00000890) #define ADR_HS3W_READ_OUT_2_ (CSR_TU_RF_BASE+0x00000894) #define ADR_HS3W_READ_OUT_3 (CSR_TU_RF_BASE+0x00000898) #define ADR_SX_LOCK_FREQ_1 (CSR_TU_RF_BASE+0x0000089c) #define ADR_SX_LOCK_FREQ_2 (CSR_TU_RF_BASE+0x000008a0) #define ADR_RX_DC_CAL_RESULT (CSR_TU_RF_BASE+0x000008c0) #define ADR_AUDIO_CTRL_REG (CSR_TU_RF_BASE+0x000008c4) #define ADR_AUDIO_PDM_REG (CSR_TU_RF_BASE+0x000008c8) #define ADR_RF_5G_TX_PARTITION_BAND1 (CSR_TU_RF_BASE+0x000008cc) #define ADR_RF_5G_TX_PARTITION_BAND2 (CSR_TU_RF_BASE+0x000008d0) #define ADR_WIFI_PADPD_5100_GAIN_REG0 (CSR_TU_RF_BASE+0x00000900) #define ADR_WIFI_PADPD_5100_GAIN_REG1 (CSR_TU_RF_BASE+0x00000904) #define ADR_WIFI_PADPD_5100_GAIN_REG2 (CSR_TU_RF_BASE+0x00000908) #define ADR_WIFI_PADPD_5100_GAIN_REG3 (CSR_TU_RF_BASE+0x0000090c) #define ADR_WIFI_PADPD_5100_GAIN_REG4 (CSR_TU_RF_BASE+0x00000910) #define ADR_WIFI_PADPD_5100_GAIN_REG5 (CSR_TU_RF_BASE+0x00000914) #define ADR_WIFI_PADPD_5100_GAIN_REG6 (CSR_TU_RF_BASE+0x00000918) #define ADR_WIFI_PADPD_5100_GAIN_REG7 (CSR_TU_RF_BASE+0x0000091c) #define ADR_WIFI_PADPD_5100_GAIN_REG8 (CSR_TU_RF_BASE+0x00000920) #define ADR_WIFI_PADPD_5100_GAIN_REG9 (CSR_TU_RF_BASE+0x00000924) #define ADR_WIFI_PADPD_5100_GAIN_REGA (CSR_TU_RF_BASE+0x00000928) #define ADR_WIFI_PADPD_5100_GAIN_REGB (CSR_TU_RF_BASE+0x0000092c) #define ADR_WIFI_PADPD_5100_GAIN_REGC (CSR_TU_RF_BASE+0x00000930) #define ADR_WIFI_PADPD_5100_PHASE_REG0 (CSR_TU_RF_BASE+0x00000940) #define ADR_WIFI_PADPD_5100_PHASE_REG1 (CSR_TU_RF_BASE+0x00000944) #define ADR_WIFI_PADPD_5100_PHASE_REG2 (CSR_TU_RF_BASE+0x00000948) #define ADR_WIFI_PADPD_5100_PHASE_REG3 (CSR_TU_RF_BASE+0x0000094c) #define ADR_WIFI_PADPD_5100_PHASE_REG4 (CSR_TU_RF_BASE+0x00000950) #define ADR_WIFI_PADPD_5100_PHASE_REG5 (CSR_TU_RF_BASE+0x00000954) #define ADR_WIFI_PADPD_5100_PHASE_REG6 (CSR_TU_RF_BASE+0x00000958) #define ADR_WIFI_PADPD_5100_PHASE_REG7 (CSR_TU_RF_BASE+0x0000095c) #define ADR_WIFI_PADPD_5100_PHASE_REG8 (CSR_TU_RF_BASE+0x00000960) #define ADR_WIFI_PADPD_5100_PHASE_REG9 (CSR_TU_RF_BASE+0x00000964) #define ADR_WIFI_PADPD_5100_PHASE_REGA (CSR_TU_RF_BASE+0x00000968) #define ADR_WIFI_PADPD_5100_PHASE_REGB (CSR_TU_RF_BASE+0x0000096c) #define ADR_WIFI_PADPD_5100_PHASE_REGC (CSR_TU_RF_BASE+0x00000970) #define ADR_WIFI_PADPD_5500_GAIN_REG0 (CSR_TU_RF_BASE+0x00000980) #define ADR_WIFI_PADPD_5500_GAIN_REG1 (CSR_TU_RF_BASE+0x00000984) #define ADR_WIFI_PADPD_5500_GAIN_REG2 (CSR_TU_RF_BASE+0x00000988) #define ADR_WIFI_PADPD_5500_GAIN_REG3 (CSR_TU_RF_BASE+0x0000098c) #define ADR_WIFI_PADPD_5500_GAIN_REG4 (CSR_TU_RF_BASE+0x00000990) #define ADR_WIFI_PADPD_5500_GAIN_REG5 (CSR_TU_RF_BASE+0x00000994) #define ADR_WIFI_PADPD_5500_GAIN_REG6 (CSR_TU_RF_BASE+0x00000998) #define ADR_WIFI_PADPD_5500_GAIN_REG7 (CSR_TU_RF_BASE+0x0000099c) #define ADR_WIFI_PADPD_5500_GAIN_REG8 (CSR_TU_RF_BASE+0x000009a0) #define ADR_WIFI_PADPD_5500_GAIN_REG9 (CSR_TU_RF_BASE+0x000009a4) #define ADR_WIFI_PADPD_5500_GAIN_REGA (CSR_TU_RF_BASE+0x000009a8) #define ADR_WIFI_PADPD_5500_GAIN_REGB (CSR_TU_RF_BASE+0x000009ac) #define ADR_WIFI_PADPD_5500_GAIN_REGC (CSR_TU_RF_BASE+0x000009b0) #define ADR_WIFI_PADPD_5500_PHASE_REG0 (CSR_TU_RF_BASE+0x000009c0) #define ADR_WIFI_PADPD_5500_PHASE_REG1 (CSR_TU_RF_BASE+0x000009c4) #define ADR_WIFI_PADPD_5500_PHASE_REG2 (CSR_TU_RF_BASE+0x000009c8) #define ADR_WIFI_PADPD_5500_PHASE_REG3 (CSR_TU_RF_BASE+0x000009cc) #define ADR_WIFI_PADPD_5500_PHASE_REG4 (CSR_TU_RF_BASE+0x000009d0) #define ADR_WIFI_PADPD_5500_PHASE_REG5 (CSR_TU_RF_BASE+0x000009d4) #define ADR_WIFI_PADPD_5500_PHASE_REG6 (CSR_TU_RF_BASE+0x000009d8) #define ADR_WIFI_PADPD_5500_PHASE_REG7 (CSR_TU_RF_BASE+0x000009dc) #define ADR_WIFI_PADPD_5500_PHASE_REG8 (CSR_TU_RF_BASE+0x000009e0) #define ADR_WIFI_PADPD_5500_PHASE_REG9 (CSR_TU_RF_BASE+0x000009e4) #define ADR_WIFI_PADPD_5500_PHASE_REGA (CSR_TU_RF_BASE+0x000009e8) #define ADR_WIFI_PADPD_5500_PHASE_REGB (CSR_TU_RF_BASE+0x000009ec) #define ADR_WIFI_PADPD_5500_PHASE_REGC (CSR_TU_RF_BASE+0x000009f0) #define ADR_WIFI_PADPD_5700_GAIN_REG0 (CSR_TU_RF_BASE+0x00000a00) #define ADR_WIFI_PADPD_5700_GAIN_REG1 (CSR_TU_RF_BASE+0x00000a04) #define ADR_WIFI_PADPD_5700_GAIN_REG2 (CSR_TU_RF_BASE+0x00000a08) #define ADR_WIFI_PADPD_5700_GAIN_REG3 (CSR_TU_RF_BASE+0x00000a0c) #define ADR_WIFI_PADPD_5700_GAIN_REG4 (CSR_TU_RF_BASE+0x00000a10) #define ADR_WIFI_PADPD_5700_GAIN_REG5 (CSR_TU_RF_BASE+0x00000a14) #define ADR_WIFI_PADPD_5700_GAIN_REG6 (CSR_TU_RF_BASE+0x00000a18) #define ADR_WIFI_PADPD_5700_GAIN_REG7 (CSR_TU_RF_BASE+0x00000a1c) #define ADR_WIFI_PADPD_5700_GAIN_REG8 (CSR_TU_RF_BASE+0x00000a20) #define ADR_WIFI_PADPD_5700_GAIN_REG9 (CSR_TU_RF_BASE+0x00000a24) #define ADR_WIFI_PADPD_5700_GAIN_REGA (CSR_TU_RF_BASE+0x00000a28) #define ADR_WIFI_PADPD_5700_GAIN_REGB (CSR_TU_RF_BASE+0x00000a2c) #define ADR_WIFI_PADPD_5700_GAIN_REGC (CSR_TU_RF_BASE+0x00000a30) #define ADR_WIFI_PADPD_5700_PHASE_REG0 (CSR_TU_RF_BASE+0x00000a40) #define ADR_WIFI_PADPD_5700_PHASE_REG1 (CSR_TU_RF_BASE+0x00000a44) #define ADR_WIFI_PADPD_5700_PHASE_REG2 (CSR_TU_RF_BASE+0x00000a48) #define ADR_WIFI_PADPD_5700_PHASE_REG3 (CSR_TU_RF_BASE+0x00000a4c) #define ADR_WIFI_PADPD_5700_PHASE_REG4 (CSR_TU_RF_BASE+0x00000a50) #define ADR_WIFI_PADPD_5700_PHASE_REG5 (CSR_TU_RF_BASE+0x00000a54) #define ADR_WIFI_PADPD_5700_PHASE_REG6 (CSR_TU_RF_BASE+0x00000a58) #define ADR_WIFI_PADPD_5700_PHASE_REG7 (CSR_TU_RF_BASE+0x00000a5c) #define ADR_WIFI_PADPD_5700_PHASE_REG8 (CSR_TU_RF_BASE+0x00000a60) #define ADR_WIFI_PADPD_5700_PHASE_REG9 (CSR_TU_RF_BASE+0x00000a64) #define ADR_WIFI_PADPD_5700_PHASE_REGA (CSR_TU_RF_BASE+0x00000a68) #define ADR_WIFI_PADPD_5700_PHASE_REGB (CSR_TU_RF_BASE+0x00000a6c) #define ADR_WIFI_PADPD_5700_PHASE_REGC (CSR_TU_RF_BASE+0x00000a70) #define ADR_WIFI_PADPD_5900_GAIN_REG0 (CSR_TU_RF_BASE+0x00000a80) #define ADR_WIFI_PADPD_5900_GAIN_REG1 (CSR_TU_RF_BASE+0x00000a84) #define ADR_WIFI_PADPD_5900_GAIN_REG2 (CSR_TU_RF_BASE+0x00000a88) #define ADR_WIFI_PADPD_5900_GAIN_REG3 (CSR_TU_RF_BASE+0x00000a8c) #define ADR_WIFI_PADPD_5900_GAIN_REG4 (CSR_TU_RF_BASE+0x00000a90) #define ADR_WIFI_PADPD_5900_GAIN_REG5 (CSR_TU_RF_BASE+0x00000a94) #define ADR_WIFI_PADPD_5900_GAIN_REG6 (CSR_TU_RF_BASE+0x00000a98) #define ADR_WIFI_PADPD_5900_GAIN_REG7 (CSR_TU_RF_BASE+0x00000a9c) #define ADR_WIFI_PADPD_5900_GAIN_REG8 (CSR_TU_RF_BASE+0x00000aa0) #define ADR_WIFI_PADPD_5900_GAIN_REG9 (CSR_TU_RF_BASE+0x00000aa4) #define ADR_WIFI_PADPD_5900_GAIN_REGA (CSR_TU_RF_BASE+0x00000aa8) #define ADR_WIFI_PADPD_5900_GAIN_REGB (CSR_TU_RF_BASE+0x00000aac) #define ADR_WIFI_PADPD_5900_GAIN_REGC (CSR_TU_RF_BASE+0x00000ab0) #define ADR_WIFI_PADPD_5900_PHASE_REG0 (CSR_TU_RF_BASE+0x00000ac0) #define ADR_WIFI_PADPD_5900_PHASE_REG1 (CSR_TU_RF_BASE+0x00000ac4) #define ADR_WIFI_PADPD_5900_PHASE_REG2 (CSR_TU_RF_BASE+0x00000ac8) #define ADR_WIFI_PADPD_5900_PHASE_REG3 (CSR_TU_RF_BASE+0x00000acc) #define ADR_WIFI_PADPD_5900_PHASE_REG4 (CSR_TU_RF_BASE+0x00000ad0) #define ADR_WIFI_PADPD_5900_PHASE_REG5 (CSR_TU_RF_BASE+0x00000ad4) #define ADR_WIFI_PADPD_5900_PHASE_REG6 (CSR_TU_RF_BASE+0x00000ad8) #define ADR_WIFI_PADPD_5900_PHASE_REG7 (CSR_TU_RF_BASE+0x00000adc) #define ADR_WIFI_PADPD_5900_PHASE_REG8 (CSR_TU_RF_BASE+0x00000ae0) #define ADR_WIFI_PADPD_5900_PHASE_REG9 (CSR_TU_RF_BASE+0x00000ae4) #define ADR_WIFI_PADPD_5900_PHASE_REGA (CSR_TU_RF_BASE+0x00000ae8) #define ADR_WIFI_PADPD_5900_PHASE_REGB (CSR_TU_RF_BASE+0x00000aec) #define ADR_WIFI_PADPD_5900_PHASE_REGC (CSR_TU_RF_BASE+0x00000af0) #define ADR_WIFI_PADPD_CAL_TONEGEN_REG (CSR_TU_RF_BASE+0x00000c08) #define ADR_WIFI_PADPD_CAL_RX_PADPD_REG (CSR_TU_RF_BASE+0x00000c0c) #define ADR_WIFI_PADPD_CAL_RX_RO (CSR_TU_RF_BASE+0x00000c10) #define ADR_WIFI_PADPD_CFR (CSR_TU_RF_BASE+0x00000c14) #define ADR_WIFI_PADPD_DC_RM (CSR_TU_RF_BASE+0x00000c18) #define ADR_WIFI_PADPD_TXIQ_CLIP_REG (CSR_TU_RF_BASE+0x00000c40) #define ADR_WIFI_PADPD_TXIQ_CONTROL_REG (CSR_TU_RF_BASE+0x00000c44) #define ADR_WIFI_PADPD_TXIQ_DPD_DC_REG (CSR_TU_RF_BASE+0x00000c48) #define ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG (CSR_TU_RF_BASE+0x00000c4c) #define ADR_WIFI_PADPD_2G_CONTROL_REG (CSR_TU_RF_BASE+0x00000d1c) #define ADR_WIFI_PADPD_2G_GAIN_REG0 (CSR_TU_RF_BASE+0x00000d20) #define ADR_WIFI_PADPD_2G_GAIN_REG1 (CSR_TU_RF_BASE+0x00000d24) #define ADR_WIFI_PADPD_2G_GAIN_REG2 (CSR_TU_RF_BASE+0x00000d28) #define ADR_WIFI_PADPD_2G_GAIN_REG3 (CSR_TU_RF_BASE+0x00000d30) #define ADR_WIFI_PADPD_2G_GAIN_REG4 (CSR_TU_RF_BASE+0x00000d34) #define ADR_WIFI_PADPD_2G_GAIN_REG5 (CSR_TU_RF_BASE+0x00000d38) #define ADR_WIFI_PADPD_2G_GAIN_REG6 (CSR_TU_RF_BASE+0x00000d3c) #define ADR_WIFI_PADPD_2G_GAIN_REG7 (CSR_TU_RF_BASE+0x00000d40) #define ADR_WIFI_PADPD_2G_GAIN_REG8 (CSR_TU_RF_BASE+0x00000d44) #define ADR_WIFI_PADPD_2G_GAIN_REG9 (CSR_TU_RF_BASE+0x00000d48) #define ADR_WIFI_PADPD_2G_GAIN_REGA (CSR_TU_RF_BASE+0x00000d4c) #define ADR_WIFI_PADPD_2G_GAIN_REGB (CSR_TU_RF_BASE+0x00000d50) #define ADR_WIFI_PADPD_2G_GAIN_REGC (CSR_TU_RF_BASE+0x00000d54) #define ADR_WIFI_PADPD_2G_PHASE_REG0 (CSR_TU_RF_BASE+0x00000d70) #define ADR_WIFI_PADPD_2G_PHASE_REG1 (CSR_TU_RF_BASE+0x00000d74) #define ADR_WIFI_PADPD_2G_PHASE_REG2 (CSR_TU_RF_BASE+0x00000d78) #define ADR_WIFI_PADPD_2G_PHASE_REG3 (CSR_TU_RF_BASE+0x00000d80) #define ADR_WIFI_PADPD_2G_PHASE_REG4 (CSR_TU_RF_BASE+0x00000d84) #define ADR_WIFI_PADPD_2G_PHASE_REG5 (CSR_TU_RF_BASE+0x00000d88) #define ADR_WIFI_PADPD_2G_PHASE_REG6 (CSR_TU_RF_BASE+0x00000d8c) #define ADR_WIFI_PADPD_2G_PHASE_REG7 (CSR_TU_RF_BASE+0x00000d90) #define ADR_WIFI_PADPD_2G_PHASE_REG8 (CSR_TU_RF_BASE+0x00000d94) #define ADR_WIFI_PADPD_2G_PHASE_REG9 (CSR_TU_RF_BASE+0x00000d98) #define ADR_WIFI_PADPD_2G_PHASE_REGA (CSR_TU_RF_BASE+0x00000d9c) #define ADR_WIFI_PADPD_2G_PHASE_REGB (CSR_TU_RF_BASE+0x00000da0) #define ADR_WIFI_PADPD_2G_PHASE_REGC (CSR_TU_RF_BASE+0x00000da4) #define ADR_WIFI_PADPD_5G_BB_GAIN_REG (CSR_TU_RF_BASE+0x00000da8) #define ADR_WIFI_PADPD_2G_BB_GAIN_REG (CSR_TU_RF_BASE+0x00000dac) #define ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG (CSR_TU_RF_BASE+0x00000dbc) #define ADR_HS5W_MD_EN (CSR_TU_RF_BASE+0x00000dc0) #define ADR_HS5W_MAN (CSR_TU_RF_BASE+0x00000dc4) #define ADR_HS5W_MAN_SET_ADD0 (CSR_TU_RF_BASE+0x00000dc8) #define ADR_HS5W_MAN_SET_ADD1 (CSR_TU_RF_BASE+0x00000dcc) #define ADR_HS5W_MAN_SET_ADD2 (CSR_TU_RF_BASE+0x00000dd0) #define ADR_HS5W_MAN_SET_ADD3 (CSR_TU_RF_BASE+0x00000dd4) #define ADR_HS5W_MAN_SET_ADD4_CH (CSR_TU_RF_BASE+0x00000dd8) #define ADR_HS5W_MAN_SET_ADD4_CH_5GB (CSR_TU_RF_BASE+0x00000ddc) #define ADR_HS5W_MAN_SET_ADD4_F (CSR_TU_RF_BASE+0x00000de0) #define ADR_HS5W_MAN_SET_ADD4_F_5GB (CSR_TU_RF_BASE+0x00000de4) #define ADR_HS5W_MAN_SET_ADD5 (CSR_TU_RF_BASE+0x00000de8) #define ADR_HS5W_MAN_SET_ADD5_5GB (CSR_TU_RF_BASE+0x00000dec) #define ADR_HS5W_MAN_SET_ADD6 (CSR_TU_RF_BASE+0x00000df0) #define ADR_WIFI_PADPD_RESERVED_REG (CSR_TU_RF_BASE+0x00000ffc) // CSR_TU_PMU #define ADR_PMU_REG_1 (CSR_TU_PMU_BASE+0x00000000) #define ADR_PMU_REG_2 (CSR_TU_PMU_BASE+0x00000004) #define ADR_PMU_REG_3 (CSR_TU_PMU_BASE+0x00000008) #define ADR_PMU_REG_4 (CSR_TU_PMU_BASE+0x0000000c) #define ADR_PMU_REG_5 (CSR_TU_PMU_BASE+0x00000010) #define ADR_PMU_REG_6 (CSR_TU_PMU_BASE+0x00000014) #define ADR_PMU_SLEEP_REG_1 (CSR_TU_PMU_BASE+0x00000018) #define ADR_PMU_SLEEP_REG_2 (CSR_TU_PMU_BASE+0x0000001c) #define ADR_PMU_RTC_REG_0 (CSR_TU_PMU_BASE+0x00000020) #define ADR_PMU_RTC_REG_1 (CSR_TU_PMU_BASE+0x00000024) #define ADR_PMU_RTC_REG_2 (CSR_TU_PMU_BASE+0x00000028) #define ADR_PMU_RTC_REG_3 (CSR_TU_PMU_BASE+0x0000002c) #define ADR_PMU_CTRL_REG (CSR_TU_PMU_BASE+0x0000003c) #define ADR_PMU_STATE_REG (CSR_TU_PMU_BASE+0x00000044) #define ADR_PMU_DPLL_REG_0 (CSR_TU_PMU_BASE+0x00000080) #define ADR_PMU_DPLL_REG_1 (CSR_TU_PMU_BASE+0x00000084) #define ADR_PMU_DPLL_REG_2 (CSR_TU_PMU_BASE+0x00000088) #define ADR_PMU_DPLL_REG_3 (CSR_TU_PMU_BASE+0x0000008c) #define ADR_PMU_SLEEP_MODE_REG (CSR_TU_PMU_BASE+0x00000090) #define ADR_PMU_RAM_00 (CSR_TU_PMU_BASE+0x000000c0) #define ADR_PMU_RAM_01 (CSR_TU_PMU_BASE+0x000000c4) #define ADR_PMU_RAM_02 (CSR_TU_PMU_BASE+0x000000c8) #define ADR_PMU_RAM_03 (CSR_TU_PMU_BASE+0x000000cc) #define ADR_PMU_RAM_04 (CSR_TU_PMU_BASE+0x000000d0) #define ADR_PMU_RAM_05 (CSR_TU_PMU_BASE+0x000000d4) #define ADR_PMU_RAM_06 (CSR_TU_PMU_BASE+0x000000d8) #define ADR_PMU_RAM_07 (CSR_TU_PMU_BASE+0x000000dc) #define ADR_PMU_RAM_08 (CSR_TU_PMU_BASE+0x000000e0) #define ADR_PMU_RAM_09 (CSR_TU_PMU_BASE+0x000000e4) #define ADR_PMU_RAM_10 (CSR_TU_PMU_BASE+0x000000e8) #define ADR_PMU_RAM_11 (CSR_TU_PMU_BASE+0x000000ec) #define ADR_PMU_RAM_12 (CSR_TU_PMU_BASE+0x000000f0) #define ADR_PMU_RAM_13 (CSR_TU_PMU_BASE+0x000000f4) #define ADR_PMU_RAM_14 (CSR_TU_PMU_BASE+0x000000f8) #define ADR_PMU_RAM_15 (CSR_TU_PMU_BASE+0x000000fc) // CSR_TU_PHY #define ADR_WIFI_PHY_COMMON_SYS_REG (CSR_TU_PHY_BASE+0x00000000) #define ADR_WIFI_PHY_COMMON_ENABLE_REG (CSR_TU_PHY_BASE+0x00000004) #define ADR_WIFI_PHY_COMMON_VERSION_REG (CSR_TU_PHY_BASE+0x00000008) #define ADR_WIFI_PHY_COMMON_DES_REG0 (CSR_TU_PHY_BASE+0x0000000c) #define ADR_WIFI_PHY_COMMON_DES_REG1 (CSR_TU_PHY_BASE+0x00000010) #define ADR_WIFI_PHY_COMMON_DES_REG2 (CSR_TU_PHY_BASE+0x00000014) #define ADR_WIFI_PHY_COMMON_DES_REG3 (CSR_TU_PHY_BASE+0x00000018) #define ADR_WIFI_PHY_COMMON_DES_REG4 (CSR_TU_PHY_BASE+0x0000001c) #define ADR_WIFI_PHY_COMMON_TX_CONTROL (CSR_TU_PHY_BASE+0x00000020) #define ADR_WIFI_PHY_COMMON_DES_REG5 (CSR_TU_PHY_BASE+0x00000024) #define ADR_WIFI_PHY_COMMON_DES_REG6 (CSR_TU_PHY_BASE+0x00000028) #define ADR_WIFI_PHY_COMMON_RFAGC_REG0 (CSR_TU_PHY_BASE+0x0000002c) #define ADR_WIFI_PHY_COMMON_RFAGC_REG1 (CSR_TU_PHY_BASE+0x00000030) #define ADR_WIFI_PHY_COMMON_RFAGC_REG2 (CSR_TU_PHY_BASE+0x00000034) #define ADR_WIFI_PHY_COMMON_RFAGC_REG3 (CSR_TU_PHY_BASE+0x00000038) #define ADR_WIFI_PHY_COMMON_RFAGC_REG4 (CSR_TU_PHY_BASE+0x0000003c) #define ADR_WIFI_PHY_COMMON_11B_DAGC_REG0 (CSR_TU_PHY_BASE+0x00000040) #define ADR_WIFI_PHY_COMMON_11B_DAGC_REG1 (CSR_TU_PHY_BASE+0x00000044) #define ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0 (CSR_TU_PHY_BASE+0x00000048) #define ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1 (CSR_TU_PHY_BASE+0x0000004c) #define ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG (CSR_TU_PHY_BASE+0x00000050) #define ADR_WIFI_PHY_COMMON_RFAGC_RO00 (CSR_TU_PHY_BASE+0x00000054) #define ADR_WIFI_PHY_COMMON_RFAGC_RO01 (CSR_TU_PHY_BASE+0x00000058) #define ADR_WIFI_PHY_COMMON_RFAGC_RO02 (CSR_TU_PHY_BASE+0x0000005c) #define ADR_WIFI_PHY_COMMON_RXDC (CSR_TU_PHY_BASE+0x00000060) #define ADR_WIFI_PHY_COMMON_RXDC_RO (CSR_TU_PHY_BASE+0x00000064) #define ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG (CSR_TU_PHY_BASE+0x00000080) #define ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG (CSR_TU_PHY_BASE+0x00000088) #define ADR_WIFI_PHY_COMMON_EDCCA_0 (CSR_TU_PHY_BASE+0x0000008c) #define ADR_WIFI_PHY_COMMON_EDCCA_1 (CSR_TU_PHY_BASE+0x00000090) #define ADR_WIFI_PHY_COMMON_EDCCA_2 (CSR_TU_PHY_BASE+0x00000094) #define ADR_WIFI_PHY_AGC_RELOCK_1 (CSR_TU_PHY_BASE+0x00000098) #define ADR_WIFI_PHY_AGC_RELOCK_2 (CSR_TU_PHY_BASE+0x0000009c) #define ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0 (CSR_TU_PHY_BASE+0x000000a0) #define ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1 (CSR_TU_PHY_BASE+0x000000a4) #define ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0 (CSR_TU_PHY_BASE+0x000000a8) #define ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1 (CSR_TU_PHY_BASE+0x000000ac) #define ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO (CSR_TU_PHY_BASE+0x000000b0) #define ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO (CSR_TU_PHY_BASE+0x000000b4) #define ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG (CSR_TU_PHY_BASE+0x000000fc) #define ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO (CSR_TU_PHY_BASE+0x00000100) #define ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0 (CSR_TU_PHY_BASE+0x0000012c) #define ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1 (CSR_TU_PHY_BASE+0x00000130) #define ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG (CSR_TU_PHY_BASE+0x00000134) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0 (CSR_TU_PHY_BASE+0x00000140) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1 (CSR_TU_PHY_BASE+0x00000144) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2 (CSR_TU_PHY_BASE+0x00000148) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3 (CSR_TU_PHY_BASE+0x0000014c) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4 (CSR_TU_PHY_BASE+0x00000150) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5 (CSR_TU_PHY_BASE+0x00000154) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6 (CSR_TU_PHY_BASE+0x00000158) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7 (CSR_TU_PHY_BASE+0x0000015c) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8 (CSR_TU_PHY_BASE+0x00000160) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9 (CSR_TU_PHY_BASE+0x00000164) #define ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A (CSR_TU_PHY_BASE+0x00000168) #define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0 (CSR_TU_PHY_BASE+0x00000180) #define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1 (CSR_TU_PHY_BASE+0x00000184) #define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2 (CSR_TU_PHY_BASE+0x00000188) #define ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3 (CSR_TU_PHY_BASE+0x0000018c) #define ADR_WIFI_PHY_COMMON_RF_PWR_REG_0 (CSR_TU_PHY_BASE+0x00000190) #define ADR_WIFI_PHY_COMMON_RF_PWR_REG_1 (CSR_TU_PHY_BASE+0x00000194) #define ADR_WIFI_PHY_COMMON_RF_PWR_REG_2 (CSR_TU_PHY_BASE+0x00000198) #define ADR_WIFI_PHY_COMMON_RF_PWR_REG_3 (CSR_TU_PHY_BASE+0x0000019c) #define ADR_WIFI_PHY_COMMON_RX_MON_0 (CSR_TU_PHY_BASE+0x000001c0) #define ADR_WIFI_PHY_COMMON_RX_MON_1 (CSR_TU_PHY_BASE+0x000001c4) #define ADR_WIFI_PHY_COMMON_RX_MON_2 (CSR_TU_PHY_BASE+0x000001c8) #define ADR_WIFI_PHY_COMMON_RX_MON_3 (CSR_TU_PHY_BASE+0x000001cc) #define ADR_WIFI_PHY_COMMON_RX_MON_4 (CSR_TU_PHY_BASE+0x000001d0) #define ADR_WIFI_PHY_COMMON_RX_MON_5 (CSR_TU_PHY_BASE+0x000001d4) #define ADR_WIFI_PHY_COMMON_RX_MON_6 (CSR_TU_PHY_BASE+0x000001d8) #define ADR_WIFI_PHY_COMMON_RX_MON_7 (CSR_TU_PHY_BASE+0x000001dc) #define ADR_WIFI_PHY_COMMON_RX_MON_8 (CSR_TU_PHY_BASE+0x000001e0) #define ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO (CSR_TU_PHY_BASE+0x000001e4) #define ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO (CSR_TU_PHY_BASE+0x000001e8) #define ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL (CSR_TU_PHY_BASE+0x00000200) #define ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO (CSR_TU_PHY_BASE+0x00000204) #define ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG (CSR_TU_PHY_BASE+0x00000220) #define ADR_WIFI_PHY_AUDIO_CLK_CTRL (CSR_TU_PHY_BASE+0x00000240) #define ADR_WIFI_PHY_COMMON_TOP_STATUS_RO (CSR_TU_PHY_BASE+0x000003c0) #define ADR_WIFI_PHY_COMMON_RESERVED_REG (CSR_TU_PHY_BASE+0x000003fc) #define ADR_WIFI_11B_TX_BB_RAMP_REG (CSR_TU_PHY_BASE+0x000004b4) #define ADR_WIFI_11B_TX_PKT_CNT_SENT_REG (CSR_TU_PHY_BASE+0x000007c0) #define ADR_WIFI_11B_TX_DEBUG_SEL_REG (CSR_TU_PHY_BASE+0x000007f8) #define ADR_WIFI_11B_TX_RESERVED_REG (CSR_TU_PHY_BASE+0x000007fc) #define ADR_WIFI_11B_RX_REG_000 (CSR_TU_PHY_BASE+0x00000800) #define ADR_WIFI_11B_RX_REG_001 (CSR_TU_PHY_BASE+0x00000804) #define ADR_WIFI_11B_RX_REG_002 (CSR_TU_PHY_BASE+0x00000808) #define ADR_WIFI_11B_RX_REG_003 (CSR_TU_PHY_BASE+0x0000080c) #define ADR_WIFI_11B_RX_REG_004 (CSR_TU_PHY_BASE+0x00000810) #define ADR_WIFI_11B_RX_REG_005 (CSR_TU_PHY_BASE+0x00000814) #define ADR_WIFI_11B_RX_REG_006 (CSR_TU_PHY_BASE+0x00000818) #define ADR_WIFI_11B_RX_REG_007 (CSR_TU_PHY_BASE+0x0000081c) #define ADR_WIFI_11B_RX_REG_008 (CSR_TU_PHY_BASE+0x00000820) #define ADR_WIFI_11B_RX_REG_009 (CSR_TU_PHY_BASE+0x00000824) #define ADR_WIFI_11B_RX_REG_010 (CSR_TU_PHY_BASE+0x00000828) #define ADR_WIFI_11B_RX_REG_011 (CSR_TU_PHY_BASE+0x0000082c) #define ADR_WIFI_11B_RX_REG_012 (CSR_TU_PHY_BASE+0x00000830) #define ADR_WIFI_11B_RX_REG_013 (CSR_TU_PHY_BASE+0x00000834) #define ADR_WIFI_11B_RX_REG_014 (CSR_TU_PHY_BASE+0x00000838) #define ADR_WIFI_11B_RX_REG_039 (CSR_TU_PHY_BASE+0x0000089c) #define ADR_WIFI_11B_RX_REG_040 (CSR_TU_PHY_BASE+0x000008a0) #define ADR_WIFI_11B_RX_REG_041 (CSR_TU_PHY_BASE+0x000008a4) #define ADR_WIFI_11B_RX_REG_240 (CSR_TU_PHY_BASE+0x00000bc0) #define ADR_WIFI_11B_RX_REG_241 (CSR_TU_PHY_BASE+0x00000bc4) #define ADR_WIFI_11B_RX_REG_244 (CSR_TU_PHY_BASE+0x00000bd0) #define ADR_WIFI_11B_RX_REG_245 (CSR_TU_PHY_BASE+0x00000bd4) #define ADR_WIFI_11B_RX_REG_246 (CSR_TU_PHY_BASE+0x00000bd8) #define ADR_WIFI_11B_RX_REG_249 (CSR_TU_PHY_BASE+0x00000be4) #define ADR_WIFI_11B_RX_REG_250 (CSR_TU_PHY_BASE+0x00000be8) #define ADR_WIFI_11B_RX_REG_251 (CSR_TU_PHY_BASE+0x00000bec) #define ADR_WIFI_11B_RX_REG_252 (CSR_TU_PHY_BASE+0x00000bf0) #define ADR_WIFI_11B_RX_REG_253 (CSR_TU_PHY_BASE+0x00000bf4) #define ADR_WIFI_11B_RX_REG_254 (CSR_TU_PHY_BASE+0x00000bf8) #define ADR_WIFI_11B_RX_REG_255 (CSR_TU_PHY_BASE+0x00000bfc) #define ADR_WIFI_11GN_TX_MEM_BIST_REG (CSR_TU_PHY_BASE+0x00000c80) #define ADR_WIFI_11GN_TX_BB_RAMP_REG (CSR_TU_PHY_BASE+0x00000ca4) #define ADR_WIFI_11GN_TX_CONTROL_REG (CSR_TU_PHY_BASE+0x00000ca8) #define ADR_WIFI_11GN_TX_STS_SCALE_REG (CSR_TU_PHY_BASE+0x00000cb0) #define ADR_WIFI_11GN_TX_FFT_SCALE_REG0 (CSR_TU_PHY_BASE+0x00000cb4) #define ADR_WIFI_11GN_TX_FFT_SCALE_REG1 (CSR_TU_PHY_BASE+0x00000cb8) #define ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG (CSR_TU_PHY_BASE+0x00000fc0) #define ADR_WIFI_11GN_TX_DEBUG_SEL_REG (CSR_TU_PHY_BASE+0x00000ff8) #define ADR_WIFI_11GN_TX_RESERVED_REG (CSR_TU_PHY_BASE+0x00000ffc) #define ADR_WIFI_11GN_RX_REG_000 (CSR_TU_PHY_BASE+0x00001000) #define ADR_WIFI_11GN_RX_REG_001 (CSR_TU_PHY_BASE+0x00001004) #define ADR_WIFI_11GN_RX_REG_002 (CSR_TU_PHY_BASE+0x00001008) #define ADR_WIFI_11GN_RX_REG_003 (CSR_TU_PHY_BASE+0x0000100c) #define ADR_WIFI_11GN_RX_REG_004_ (CSR_TU_PHY_BASE+0x00001010) #define ADR_WIFI_11GN_RX_REG_005 (CSR_TU_PHY_BASE+0x00001014) #define ADR_WIFI_11GN_RX_REG_006_ (CSR_TU_PHY_BASE+0x00001018) #define ADR_WIFI_11GN_RX_REG_007_ (CSR_TU_PHY_BASE+0x0000101c) #define ADR_WIFI_11GN_RX_REG_008 (CSR_TU_PHY_BASE+0x00001020) #define ADR_WIFI_11GN_RX_REG_009 (CSR_TU_PHY_BASE+0x00001024) #define ADR_WIFI_11GN_RX_REG_010_ (CSR_TU_PHY_BASE+0x00001028) #define ADR_WIFI_11GN_RX_REG_011 (CSR_TU_PHY_BASE+0x0000102c) #define ADR_WIFI_11GN_RX_REG_012 (CSR_TU_PHY_BASE+0x00001030) #define ADR_WIFI_11GN_RX_REG_013 (CSR_TU_PHY_BASE+0x00001034) #define ADR_WIFI_11GN_RX_REG_014 (CSR_TU_PHY_BASE+0x00001038) #define ADR_WIFI_11GN_RX_REG_015 (CSR_TU_PHY_BASE+0x0000103c) #define ADR_WIFI_11GN_RX_REG_016 (CSR_TU_PHY_BASE+0x00001040) #define ADR_WIFI_11GN_RX_REG_017 (CSR_TU_PHY_BASE+0x00001044) #define ADR_WIFI_11GN_RX_REG_032 (CSR_TU_PHY_BASE+0x00001080) #define ADR_WIFI_11GN_RX_REG_033 (CSR_TU_PHY_BASE+0x00001084) #define ADR_WIFI_11GN_RX_REG_039 (CSR_TU_PHY_BASE+0x0000109c) #define ADR_WIFI_11GN_RX_REG_040 (CSR_TU_PHY_BASE+0x000010a0) #define ADR_WIFI_11GN_RX_REG_048 (CSR_TU_PHY_BASE+0x000010c0) #define ADR_WIFI_11GN_RX_REG_049 (CSR_TU_PHY_BASE+0x000010c4) #define ADR_WIFI_11GN_RX_REG_050 (CSR_TU_PHY_BASE+0x000010c8) #define ADR_WIFI_11GN_RX_REG_051 (CSR_TU_PHY_BASE+0x000010cc) #define ADR_WIFI_11GN_RX_REG_052 (CSR_TU_PHY_BASE+0x000010d0) #define ADR_WIFI_11GN_RX_REG_076 (CSR_TU_PHY_BASE+0x00001130) #define ADR_WIFI_11GN_RX_REG_087 (CSR_TU_PHY_BASE+0x0000115c) #define ADR_WIFI_11GN_RX_REG_088 (CSR_TU_PHY_BASE+0x00001160) #define ADR_WIFI_11GN_RX_REG_089 (CSR_TU_PHY_BASE+0x00001164) #define ADR_WIFI_11GN_RX_REG_096 (CSR_TU_PHY_BASE+0x00001180) #define ADR_WIFI_11GN_RX_REG_098 (CSR_TU_PHY_BASE+0x00001188) #define ADR_WIFI_11GN_RX_REG_100 (CSR_TU_PHY_BASE+0x00001190) #define ADR_WIFI_11GN_RX_REG_101 (CSR_TU_PHY_BASE+0x00001194) #define ADR_WIFI_11GN_RX_REG_102 (CSR_TU_PHY_BASE+0x00001198) #define ADR_WIFI_11GN_RX_REG_103 (CSR_TU_PHY_BASE+0x0000119c) #define ADR_WIFI_11GN_RX_REG_241 (CSR_TU_PHY_BASE+0x000013c4) #define ADR_WIFI_11GN_RX_REG_244 (CSR_TU_PHY_BASE+0x000013d0) #define ADR_WIFI_11GN_RX_REG_245 (CSR_TU_PHY_BASE+0x000013d4) #define ADR_WIFI_11GN_RX_REG_246 (CSR_TU_PHY_BASE+0x000013d8) #define ADR_WIFI_11GN_RX_REG_247 (CSR_TU_PHY_BASE+0x000013dc) #define ADR_WIFI_11GN_RX_REG_248 (CSR_TU_PHY_BASE+0x000013e0) #define ADR_WIFI_11GN_RX_REG_249 (CSR_TU_PHY_BASE+0x000013e4) #define ADR_WIFI_11GN_RX_REG_250 (CSR_TU_PHY_BASE+0x000013e8) #define ADR_WIFI_11GN_RX_REG_251 (CSR_TU_PHY_BASE+0x000013ec) #define ADR_WIFI_11GN_RX_REG_252 (CSR_TU_PHY_BASE+0x000013f0) #define ADR_WIFI_11GN_RX_REG_253 (CSR_TU_PHY_BASE+0x000013f4) #define ADR_WIFI_11GN_RX_REG_254 (CSR_TU_PHY_BASE+0x000013f8) #define ADR_WIFI_11GN_RX_REG_255 (CSR_TU_PHY_BASE+0x000013fc) #define ADR_WIFI_RADAR_REG_00 (CSR_TU_PHY_BASE+0x00001400) #define ADR_WIFI_RADAR_REG_01 (CSR_TU_PHY_BASE+0x00001404) #define ADR_WIFI_RADAR_REG_02 (CSR_TU_PHY_BASE+0x00001408) #define ADR_WIFI_RADAR_REG_03 (CSR_TU_PHY_BASE+0x0000140c) #define ADR_WIFI_RADAR_REG_04 (CSR_TU_PHY_BASE+0x00001410) #define ADR_WIFI_RADAR_REG_RO (CSR_TU_PHY_BASE+0x00001414) #define ADR_WIFI_RADAR_REG_DB_A0_RO (CSR_TU_PHY_BASE+0x00001418) #define ADR_WIFI_RADAR_REG_DB_A1_RO (CSR_TU_PHY_BASE+0x0000141c) #define ADR_WIFI_RADAR_REG_DB_A2_RO (CSR_TU_PHY_BASE+0x00001420) #define ADR_WIFI_RADAR_REG_DB_P0_RO (CSR_TU_PHY_BASE+0x00001424) #define ADR_WIFI_RADAR_REG_DB_P1_RO (CSR_TU_PHY_BASE+0x00001428) #define ADR_WIFI_RADAR_REG_DB_P2_RO (CSR_TU_PHY_BASE+0x0000142c) #define ADR_WIFI_RADAR_CHIRP_REG (CSR_TU_PHY_BASE+0x00001430) // MB_REG #define ADR_MB_CPU_INT_ALT (MB_REG_BASE+0x00000000) #define ADR_MB_CPU_INT (MB_REG_BASE+0x00000004) #define ADR_CPU_ID_TB0 (MB_REG_BASE+0x00000008) #define ADR_CPU_ID_TB1 (MB_REG_BASE+0x0000000c) #define ADR_CH0_TRIG_1 (MB_REG_BASE+0x00000010) #define ADR_CH0_TRIG_0 (MB_REG_BASE+0x00000010) #define ADR_CH0_PRI_TRIG (MB_REG_BASE+0x00000014) #define ADR_MCU_STATUS (MB_REG_BASE+0x00000018) #define ADR_RD_IN_FFCNT1 (MB_REG_BASE+0x0000001c) #define ADR_RD_IN_FFCNT2 (MB_REG_BASE+0x00000020) #define ADR_RD_FFIN_FULL (MB_REG_BASE+0x00000024) #define ADR_CH2_TRIG_ALT (MB_REG_BASE+0x00000028) #define ADR_CH2_INT_ADDR_ALT (MB_REG_BASE+0x00000028) #define ADR_MBOX_HALT_CFG (MB_REG_BASE+0x0000002c) #define ADR_MBOX_HALT_STS (MB_REG_BASE+0x0000002c) #define ADR_MB_DBG_CFG1 (MB_REG_BASE+0x00000030) #define ADR_MB_DBG_CFG2 (MB_REG_BASE+0x00000034) #define ADR_MB_DBG_CFG3 (MB_REG_BASE+0x00000038) #define ADR_MB_DBG_CFG4 (MB_REG_BASE+0x0000003c) #define ADR_MB_OUT_QUEUE_CFG (MB_REG_BASE+0x00000040) #define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044) #define ADR_MB_OUT_QUEUE_FLUSH (MB_REG_BASE+0x00000044) #define ADR_RD_FFOUT_CNT1 (MB_REG_BASE+0x00000048) #define ADR_RD_FFOUT_CNT2 (MB_REG_BASE+0x0000004c) #define ADR_RD_FFOUT_CNT3 (MB_REG_BASE+0x00000050) #define ADR_RD_FFOUT_FULL (MB_REG_BASE+0x00000054) #define ADR_MB_THRESHOLD6 (MB_REG_BASE+0x0000006c) #define ADR_MB_THRESHOLD7 (MB_REG_BASE+0x00000070) #define ADR_MB_THRESHOLD8 (MB_REG_BASE+0x00000074) #define ADR_MB_THRESHOLD9 (MB_REG_BASE+0x00000078) #define ADR_MB_THRESHOLD10 (MB_REG_BASE+0x0000007c) #define ADR_MB_TRASH_CFG (MB_REG_BASE+0x00000080) #define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084) #define ADR_MB_IN_FF_FLUSH (MB_REG_BASE+0x00000084) #define ADR_CPU_ID_TB2 (MB_REG_BASE+0x00000088) #define ADR_CPU_ID_TB3 (MB_REG_BASE+0x0000008c) #define ADR_PHY_IQ_LOG_CFG0 (MB_REG_BASE+0x00000090) #define ADR_PHY_IQ_LOG_CFG1 (MB_REG_BASE+0x00000094) #define ADR_PHY_IQ_LOG_LEN (MB_REG_BASE+0x00000098) #define ADR_PHY_IQ_LOG_PTR (MB_REG_BASE+0x0000009c) // ID_MNG_REG #define ADR_WR_ALC (ID_MNG_REG_BASE+0x00000000) #define ADR_GETID (ID_MNG_REG_BASE+0x00000000) #define ADR_CH_STA_PRI (ID_MNG_REG_BASE+0x00000004) #define ADR_RD_ID0 (ID_MNG_REG_BASE+0x00000008) #define ADR_RD_ID1 (ID_MNG_REG_BASE+0x0000000c) #define ADR_IMD_CFG (ID_MNG_REG_BASE+0x00000010) #define ADR_IMD_STA (ID_MNG_REG_BASE+0x00000014) #define ADR_ALC_STA (ID_MNG_REG_BASE+0x00000018) #define ADR_TRX_ID_COUNT (ID_MNG_REG_BASE+0x0000001c) #define ADR_TRX_ID_THRESHOLD (ID_MNG_REG_BASE+0x00000020) #define ADR_TX_ID0 (ID_MNG_REG_BASE+0x00000024) #define ADR_TX_ID1 (ID_MNG_REG_BASE+0x00000028) #define ADR_RX_ID0 (ID_MNG_REG_BASE+0x0000002c) #define ADR_RX_ID1 (ID_MNG_REG_BASE+0x00000030) #define ADR_RTN_STA (ID_MNG_REG_BASE+0x00000034) #define ADR_ID_LEN_THREADSHOLD1 (ID_MNG_REG_BASE+0x00000038) #define ADR_ID_LEN_THREADSHOLD2 (ID_MNG_REG_BASE+0x0000003c) #define ADR_CH_ARB_PRI (ID_MNG_REG_BASE+0x00000040) #define ADR_TX_ID_REMAIN_STATUS (ID_MNG_REG_BASE+0x00000044) #define ADR_ID_INFO_STA (ID_MNG_REG_BASE+0x00000048) #define ADR_TX_LIMIT_INTR (ID_MNG_REG_BASE+0x0000004c) #define ADR_TX_ID_ALL_INFO (ID_MNG_REG_BASE+0x00000050) #define ADR_RD_ID2 (ID_MNG_REG_BASE+0x00000054) #define ADR_RD_ID3 (ID_MNG_REG_BASE+0x00000058) #define ADR_TX_ID2 (ID_MNG_REG_BASE+0x0000005c) #define ADR_TX_ID3 (ID_MNG_REG_BASE+0x00000060) #define ADR_RX_ID2 (ID_MNG_REG_BASE+0x00000064) #define ADR_RX_ID3 (ID_MNG_REG_BASE+0x00000068) #define ADR_TX_ID_ALL_INFO2 (ID_MNG_REG_BASE+0x0000006c) #define ADR_TX_ID_ALL_INFO_A (ID_MNG_REG_BASE+0x00000070) #define ADR_TX_ID_ALL_INFO_B (ID_MNG_REG_BASE+0x00000074) #define ADR_TX_ID_REMAIN_STATUS2 (ID_MNG_REG_BASE+0x00000078) #define ADR_ALC_ID_INFO (ID_MNG_REG_BASE+0x0000007c) #define ADR_ALC_ID_INF1 (ID_MNG_REG_BASE+0x00000080) // MMU_REG #define ADR_ALC_ABORT (MMU_REG_BASE+0x00000004) #define ADR_ALC_RLS_STATUS (MMU_REG_BASE+0x00000008) #define ADR_DMN_STATUS (MMU_REG_BASE+0x0000000c) #define ADR_TAG_STATUS (MMU_REG_BASE+0x00000010) #define ADR_REQ_STATUS (MMU_REG_BASE+0x00000014) #define ADR_PAGE_TAG_STATUS_0 (MMU_REG_BASE+0x00000018) #define ADR_PAGE_TAG_STATUS_1 (MMU_REG_BASE+0x0000001c) #define ADR_PAGE_TAG_STATUS_2 (MMU_REG_BASE+0x00000020) #define ADR_PAGE_TAG_STATUS_3 (MMU_REG_BASE+0x00000024) #define ADR_PAGE_TAG_STATUS_4 (MMU_REG_BASE+0x00000028) #define ADR_PAGE_TAG_STATUS_5 (MMU_REG_BASE+0x0000002c) #define ADR_PAGE_TAG_STATUS_6 (MMU_REG_BASE+0x00000030) #define ADR_PAGE_TAG_STATUS_7 (MMU_REG_BASE+0x00000034) // CSR_TEMP_REG #define ADR_FPGA_GEMINIARF_SWITCH (CSR_TEMP_REG_BASE+0x00000030) // the following is for getting CSR fields #define GET_FBUS_DMAC_SAR0 (((REG32(ADR_FBUS_SAR0)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_DAR0 (((REG32(ADR_FBUS_DAR0)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_INTR_EN0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000001 ) >> 0) #define GET_FBUS_DMAC_DST_TR_WIDTH0 (((REG32(ADR_FBUS_CTL0_1)) & 0x0000000e ) >> 1) #define GET_FBUS_DMAC_SRC_TR_WIDTH0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000070 ) >> 4) #define GET_FBUS_DMAC_DINC0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000180 ) >> 7) #define GET_FBUS_DMAC_SINC0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00000600 ) >> 9) #define GET_FBUS_DMAC_DST_MSIZE0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00003800 ) >> 11) #define GET_FBUS_DMAC_SRC_MSIZE0 (((REG32(ADR_FBUS_CTL0_1)) & 0x0001c000 ) >> 14) #define GET_FBUS_DMAC_FC_MODE0 (((REG32(ADR_FBUS_CTL0_1)) & 0x00700000 ) >> 20) #define GET_FBUS_DMAC_BLOCK0 (((REG32(ADR_FBUS_CTL0_2)) & 0x00000fff ) >> 0) #define GET_FBUS_DMAC_CH0_PRIOR (((REG32(ADR_FBUS_CFG0_1)) & 0x00000020 ) >> 5) #define GET_FBUS_DMAC_HS_SEL_DST0 (((REG32(ADR_FBUS_CFG0_1)) & 0x00000400 ) >> 10) #define GET_FBUS_DMAC_HS_SEL_SRC0 (((REG32(ADR_FBUS_CFG0_1)) & 0x00000800 ) >> 11) #define GET_FBUS_DMAC_SRC_HS_BUS_SEL0 (((REG32(ADR_FBUS_CFG0_2)) & 0x00000380 ) >> 7) #define GET_FBUS_DMAC_DST_HS_BUS_SEL0 (((REG32(ADR_FBUS_CFG0_2)) & 0x00003800 ) >> 11) #define GET_FBUS_DMAC_SAR1 (((REG32(ADR_FBUS_SAR1)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_DAR1 (((REG32(ADR_FBUS_DAR1)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_INTR_EN1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000001 ) >> 0) #define GET_FBUS_DMAC_DST_TR_WIDTH1 (((REG32(ADR_FBUS_CTL1_1)) & 0x0000000e ) >> 1) #define GET_FBUS_DMAC_SRC_TR_WIDTH1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000070 ) >> 4) #define GET_FBUS_DMAC_DINC1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000180 ) >> 7) #define GET_FBUS_DMAC_SINC1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00000600 ) >> 9) #define GET_FBUS_DMAC_DST_MSIZE1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00003800 ) >> 11) #define GET_FBUS_DMAC_SRC_MSIZE1 (((REG32(ADR_FBUS_CTL1_1)) & 0x0001c000 ) >> 14) #define GET_FBUS_DMAC_FC_MODE1 (((REG32(ADR_FBUS_CTL1_1)) & 0x00700000 ) >> 20) #define GET_FBUS_DMAC_BLOCK1 (((REG32(ADR_FBUS_CTL1_2)) & 0x00000fff ) >> 0) #define GET_FBUS_DMAC_CH1_PRIOR (((REG32(ADR_FBUS_CFG1_1)) & 0x00000020 ) >> 5) #define GET_FBUS_DMAC_HS_SEL_DST1 (((REG32(ADR_FBUS_CFG1_1)) & 0x00000400 ) >> 10) #define GET_FBUS_DMAC_HS_SEL_SRC1 (((REG32(ADR_FBUS_CFG1_1)) & 0x00000800 ) >> 11) #define GET_FBUS_DMAC_SRC_HS_BUS_SEL1 (((REG32(ADR_FBUS_CFG1_2)) & 0x00000380 ) >> 7) #define GET_FBUS_DMAC_DST_HS_BUS_SEL1 (((REG32(ADR_FBUS_CFG1_2)) & 0x00003800 ) >> 11) #define GET_FBUS_DMAC_CH_RAW_TR (((REG32(ADR_FBUS_RAWTR)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_CH_ERR_TR (((REG32(ADR_FBUS_RAWERR)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_CH_STATUSTR_TR (((REG32(ADR_FBUS_STATUSTR)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_CH_STATUSERR_TR (((REG32(ADR_FBUS_STATUSERR)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_CH_DEMASK_TR (((REG32(ADR_FBUS_MASKTR)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_CH_DEMASK_ERR (((REG32(ADR_FBUS_MASKERR)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_CH0_CLR_TR (((REG32(ADR_FBUS_CLRTR)) & 0x00000001 ) >> 0) #define GET_FBUS_DMAC_CH1_CLR_TR (((REG32(ADR_FBUS_CLRTR)) & 0x00000002 ) >> 1) #define GET_FBUS_DMAC_CH0_CLR_ERR (((REG32(ADR_FBUS_CLRERR)) & 0x00000001 ) >> 0) #define GET_FBUS_DMAC_CH1_CLR_ERR (((REG32(ADR_FBUS_CLRERR)) & 0x00000002 ) >> 1) #define GET_FBUS_COMBINED_INT_STATUS (((REG32(ADR_FBUS_COMBINED_INT_STATUS)) & 0xffffffff ) >> 0) #define GET_FBUS_DMAC_DISEN_SHS_SRC_REQ (((REG32(ADR_FBUS_SHS_SRC_REQ_CFG)) & 0x0000ffff ) >> 0) #define GET_FBUS_DMAC_DISEN_SHS_DST_REQ (((REG32(ADR_FBUS_SHS_DST_REQ_CFG)) & 0x0000ffff ) >> 0) #define GET_FBUS_DMAC_DISEN_SHS_SRC_SREQ (((REG32(ADR_FBUS_SHS_SRC_SREQ_CFG)) & 0x0000ffff ) >> 0) #define GET_FBUS_DMAC_DISEN_SHS_DST_SREQ (((REG32(ADR_FBUS_SHS_DST_SREQ_CFG)) & 0x0000ffff ) >> 0) #define GET_FBUS_DMAC_EN (((REG32(ADR_FBUS_DMA_EN)) & 0x00000001 ) >> 0) #define GET_FBUS_DMAC_CH_EN (((REG32(ADR_FBUS_CH_EN)) & 0x0000ffff ) >> 0) #define GET_FBUS_CHANNEL_NO (((REG32(ADR_FBUS_DMAC_INFO)) & 0x00000700 ) >> 8) #define GET_SBUS_DMAC_SAR0 (((REG32(ADR_SBUS_SAR0)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_DAR0 (((REG32(ADR_SBUS_DAR0)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_INTR_EN0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000001 ) >> 0) #define GET_SBUS_DMAC_DST_TR_WIDTH0 (((REG32(ADR_SBUS_CTL0_1)) & 0x0000000e ) >> 1) #define GET_SBUS_DMAC_SRC_TR_WIDTH0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000070 ) >> 4) #define GET_SBUS_DMAC_DINC0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000180 ) >> 7) #define GET_SBUS_DMAC_SINC0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00000600 ) >> 9) #define GET_SBUS_DMAC_DST_MSIZE0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00003800 ) >> 11) #define GET_SBUS_DMAC_SRC_MSIZE0 (((REG32(ADR_SBUS_CTL0_1)) & 0x0001c000 ) >> 14) #define GET_SBUS_DMAC_FC_MODE0 (((REG32(ADR_SBUS_CTL0_1)) & 0x00700000 ) >> 20) #define GET_SBUS_DMAC_BLOCK0 (((REG32(ADR_SBUS_CTL0_2)) & 0x00000fff ) >> 0) #define GET_SBUS_DMAC_CH0_PRIOR (((REG32(ADR_SBUS_CFG0_1)) & 0x00000020 ) >> 5) #define GET_SBUS_DMAC_HS_SEL_DST0 (((REG32(ADR_SBUS_CFG0_1)) & 0x00000400 ) >> 10) #define GET_SBUS_DMAC_HS_SEL_SRC0 (((REG32(ADR_SBUS_CFG0_1)) & 0x00000800 ) >> 11) #define GET_SBUS_DMAC_SRC_HS_BUS_SEL0 (((REG32(ADR_SBUS_CFG0_2)) & 0x00000380 ) >> 7) #define GET_SBUS_DMAC_DST_HS_BUS_SEL0 (((REG32(ADR_SBUS_CFG0_2)) & 0x00003800 ) >> 11) #define GET_SBUS_DMAC_SAR1 (((REG32(ADR_SBUS_SAR1)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_DAR1 (((REG32(ADR_SBUS_DAR1)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_INTR_EN1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000001 ) >> 0) #define GET_SBUS_DMAC_DST_TR_WIDTH1 (((REG32(ADR_SBUS_CTL1_1)) & 0x0000000e ) >> 1) #define GET_SBUS_DMAC_SRC_TR_WIDTH1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000070 ) >> 4) #define GET_SBUS_DMAC_DINC1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000180 ) >> 7) #define GET_SBUS_DMAC_SINC1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00000600 ) >> 9) #define GET_SBUS_DMAC_DST_MSIZE1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00003800 ) >> 11) #define GET_SBUS_DMAC_SRC_MSIZE1 (((REG32(ADR_SBUS_CTL1_1)) & 0x0001c000 ) >> 14) #define GET_SBUS_DMAC_FC_MODE1 (((REG32(ADR_SBUS_CTL1_1)) & 0x00700000 ) >> 20) #define GET_SBUS_DMAC_BLOCK1 (((REG32(ADR_SBUS_CTL1_2)) & 0x00000fff ) >> 0) #define GET_SBUS_DMAC_CH1_PRIOR (((REG32(ADR_SBUS_CFG1_1)) & 0x00000020 ) >> 5) #define GET_SBUS_DMAC_HS_SEL_DST1 (((REG32(ADR_SBUS_CFG1_1)) & 0x00000400 ) >> 10) #define GET_SBUS_DMAC_HS_SEL_SRC1 (((REG32(ADR_SBUS_CFG1_1)) & 0x00000800 ) >> 11) #define GET_SBUS_DMAC_SRC_HS_BUS_SEL1 (((REG32(ADR_SBUS_CFG1_2)) & 0x00000380 ) >> 7) #define GET_SBUS_DMAC_DST_HS_BUS_SEL1 (((REG32(ADR_SBUS_CFG1_2)) & 0x00003800 ) >> 11) #define GET_SBUS_DMAC_CH_RAW_TR (((REG32(ADR_SBUS_RAWTR)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_CH_ERR_TR (((REG32(ADR_SBUS_RAWERR)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_CH_STATUSTR_TR (((REG32(ADR_SBUS_STATUSTR)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_CH_STATUSERR_TR (((REG32(ADR_SBUS_STATUSERR)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_CH_DEMASK_TR (((REG32(ADR_SBUS_MASKTR)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_CH_DEMASK_ERR (((REG32(ADR_SBUS_MASKERR)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_CH0_CLR_TR (((REG32(ADR_SBUS_CLRTR)) & 0x00000001 ) >> 0) #define GET_SBUS_DMAC_CH1_CLR_TR (((REG32(ADR_SBUS_CLRTR)) & 0x00000002 ) >> 1) #define GET_SBUS_DMAC_CH0_CLR_ERR (((REG32(ADR_SBUS_CLRERR)) & 0x00000001 ) >> 0) #define GET_SBUS_DMAC_CH1_CLR_ERR (((REG32(ADR_SBUS_CLRERR)) & 0x00000002 ) >> 1) #define GET_SBUS_COMBINED_INT_STATUS (((REG32(ADR_SBUS_COMBINED_INT_STATUS)) & 0xffffffff ) >> 0) #define GET_SBUS_DMAC_DISEN_SHS_SRC_REQ (((REG32(ADR_SBUS_SHS_SRC_REQ_CFG)) & 0x0000ffff ) >> 0) #define GET_SBUS_DMAC_DISEN_SHS_DST_REQ (((REG32(ADR_SBUS_SHS_DST_REQ_CFG)) & 0x0000ffff ) >> 0) #define GET_SBUS_DMAC_DISEN_SHS_SRC_SREQ (((REG32(ADR_SBUS_SHS_SRC_SREQ_CFG)) & 0x0000ffff ) >> 0) #define GET_SBUS_DMAC_DISEN_SHS_DST_SREQ (((REG32(ADR_SBUS_SHS_DST_SREQ_CFG)) & 0x0000ffff ) >> 0) #define GET_SBUS_DMAC_EN (((REG32(ADR_SBUS_DMA_EN)) & 0x00000001 ) >> 0) #define GET_SBUS_DMAC_CH_EN (((REG32(ADR_SBUS_CH_EN)) & 0x0000ffff ) >> 0) #define GET_SBUS_CHANNEL_NO (((REG32(ADR_SBUS_DMAC_INFO)) & 0x00000700 ) >> 8) #define GET_I2S_ENABLE (((REG32(ADR_I2S_EN)) & 0x00000001 ) >> 0) #define GET_I2S_RX_ENABLE (((REG32(ADR_I2S_RX_EN)) & 0x00000001 ) >> 0) #define GET_I2S_TX_ENABLE (((REG32(ADR_I2S_TX_EN)) & 0x00000001 ) >> 0) #define GET_I2S_SCLK_SOURCE_ENABLE (((REG32(ADR_I2S_SCLK_SCR_EN)) & 0x00000001 ) >> 0) #define GET_I2S_SCLK_GATE (((REG32(ADR_I2S_WS_DEF)) & 0x00000007 ) >> 0) #define GET_I2S_WS_LENGTH (((REG32(ADR_I2S_WS_DEF)) & 0x00000018 ) >> 3) #define GET_I2S_RST_RXFIFO (((REG32(ADR_RESET_RX_FIFO)) & 0x00000001 ) >> 0) #define GET_I2S_RST_TXFIFO (((REG32(ADR_RESET_TX_FIFO)) & 0x00000001 ) >> 0) #define GET_I2S_L_TRX_DATA (((REG32(ADR_L_TRX_DATA)) & 0xffffffff ) >> 0) #define GET_I2S_R_TRX_DATA (((REG32(ADR_R_TRX_DATA)) & 0xffffffff ) >> 0) #define GET_I2S_RX_CH_ENABLE (((REG32(ADR_I2S_RX_CH_EN)) & 0x00000001 ) >> 0) #define GET_I2S_TX_CH_ENABLE (((REG32(ADR_I2S_TX_CH_EN)) & 0x00000001 ) >> 0) #define GET_I2S_RX_WD_RES (((REG32(ADR_I2S_RX_WORD_RES)) & 0x00000007 ) >> 0) #define GET_I2S_TX_WD_RES (((REG32(ADR_I2S_TX_WORD_RES)) & 0x00000007 ) >> 0) #define GET_I2S_INTR_RXDA (((REG32(ADR_I2S_INTR)) & 0x00000001 ) >> 0) #define GET_I2S_INTR_RXFO (((REG32(ADR_I2S_INTR)) & 0x00000002 ) >> 1) #define GET_I2S_INTR_RXFE (((REG32(ADR_I2S_INTR)) & 0x00000010 ) >> 4) #define GET_I2S_INTR_TXFO (((REG32(ADR_I2S_INTR)) & 0x00000020 ) >> 5) #define GET_I2S_INTR_RXFA_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000001 ) >> 0) #define GET_I2S_INTR_RXFO_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000002 ) >> 1) #define GET_I2S_INTR_TXFE_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000010 ) >> 4) #define GET_I2S_INTR_TXFO_MASK (((REG32(ADR_I2S_INTR_MASK)) & 0x00000020 ) >> 5) #define GET_I2S_RXFO (((REG32(ADR_I2S_RXFO)) & 0x00000001 ) >> 0) #define GET_I2S_TXFO (((REG32(ADR_I2S_TXFO)) & 0x00000001 ) >> 0) #define GET_I2S_RX_FIFO_TH (((REG32(ADR_I2S_RX_FIFO_TH)) & 0x00000007 ) >> 0) #define GET_I2S_TX_FIFO_TH (((REG32(ADR_I2S_TX_FIFO_TH)) & 0x00000007 ) >> 0) #define GET_I2S_RX_FIFO_FLUSH (((REG32(ADR_I2S_RX_FIFO_FLUSH)) & 0x00000001 ) >> 0) #define GET_I2S_TX_FIFO_FLUSH (((REG32(ADR_I2S_TX_FIFO_FLUSH)) & 0x00000001 ) >> 0) #define GET_I2S_RX_DMA (((REG32(ADR_I2S_RX_DMA)) & 0xffffffff ) >> 0) #define GET_I2S_TX_DMA (((REG32(ADR_I2S_TX_DMA)) & 0xffffffff ) >> 0) #define GET_I2CMST_ENABLE_MASTER (((REG32(ADR_I2CMST_CFG0)) & 0x00000001 ) >> 0) #define GET_I2CMST_SPEED (((REG32(ADR_I2CMST_CFG0)) & 0x00000006 ) >> 1) #define GET_I2CMST_RESTART_EN (((REG32(ADR_I2CMST_CFG0)) & 0x00000020 ) >> 5) #define GET_I2CMST_DISABLE_SLAVE (((REG32(ADR_I2CMST_CFG0)) & 0x00000040 ) >> 6) #define GET_I2CMST_TAR (((REG32(ADR_I2CMST_TAR)) & 0x000003ff ) >> 0) #define GET_I2CMST_TRX_DATA (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x000000ff ) >> 0) #define GET_I2CMST_TRX_CMDW (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000100 ) >> 8) #define GET_I2CMST_TRX_STOPW (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000200 ) >> 9) #define GET_I2CMST_TRX_RESTARTW (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000400 ) >> 10) #define GET_I2CMST_RX_1STBRDYR (((REG32(ADR_I2CMST_TRX_CMD_DATA)) & 0x00000800 ) >> 11) #define GET_I2CMST_SCLK_H_WIDTH (((REG32(ADR_I2CMST_SCLK_H_WIDTH)) & 0x0000ffff ) >> 0) #define GET_I2CMST_SCLK_L_WIDTH (((REG32(ADR_I2CMST_SCLK_L_WIDTH)) & 0x0000ffff ) >> 0) #define GET_I2CMST_RXU_INT (((REG32(ADR_I2CMST_INT)) & 0x00000001 ) >> 0) #define GET_I2CMST_RXO_INT (((REG32(ADR_I2CMST_INT)) & 0x00000002 ) >> 1) #define GET_I2CMST_RXF_INT (((REG32(ADR_I2CMST_INT)) & 0x00000004 ) >> 2) #define GET_I2CMST_TXO_INT (((REG32(ADR_I2CMST_INT)) & 0x00000008 ) >> 3) #define GET_I2CMST_TXE_INT (((REG32(ADR_I2CMST_INT)) & 0x00000010 ) >> 4) #define GET_I2CMST_RXDONE_INT (((REG32(ADR_I2CMST_INT)) & 0x00000080 ) >> 7) #define GET_I2CMST_RXU_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000001 ) >> 0) #define GET_I2CMST_RXO_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000002 ) >> 1) #define GET_I2CMST_RXF_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000004 ) >> 2) #define GET_I2CMST_TXO_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000008 ) >> 3) #define GET_I2CMST_TXE_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000010 ) >> 4) #define GET_I2CMST_RXDONE_INT_MASK (((REG32(ADR_I2CMST_INT_MASK)) & 0x00000080 ) >> 7) #define GET_I2CMST_RXU_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000001 ) >> 0) #define GET_I2CMST_RXO_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000002 ) >> 1) #define GET_I2CMST_RXF_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000004 ) >> 2) #define GET_I2CMST_TXO_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000008 ) >> 3) #define GET_I2CMST_TXE_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000010 ) >> 4) #define GET_I2CMST_RXDONE_INT_STAR (((REG32(ADR_I2CMST_INT_STA)) & 0x00000080 ) >> 7) #define GET_I2CMST_RX_FIFO_TH (((REG32(ADR_I2CMST_RX_FIFO_TH)) & 0x0000ffff ) >> 0) #define GET_I2CMST_TX_FIFO_TH (((REG32(ADR_I2CMST_TX_FIFO_TH)) & 0x0000ffff ) >> 0) #define GET_I2CMST_EN (((REG32(ADR_I2CMST_ENABLE)) & 0x00000001 ) >> 0) #define GET_SPIMST_DATA_LEN (((REG32(ADR_SPIMST_CFG0)) & 0x0000000f ) >> 0) #define GET_SPIMST_CPHA (((REG32(ADR_SPIMST_CFG0)) & 0x00000040 ) >> 6) #define GET_SPIMST_CPOL (((REG32(ADR_SPIMST_CFG0)) & 0x00000080 ) >> 7) #define GET_TRX_MODE (((REG32(ADR_SPIMST_CFG0)) & 0x00000300 ) >> 8) #define GET_DATA_FRAMES (((REG32(ADR_SPIMST_CFG1)) & 0x0000ffff ) >> 0) #define GET_SPIMST_ENABLE (((REG32(ADR_SPIMST_EN)) & 0x00000001 ) >> 0) #define GET_SPIMST_CEN_ENABLE (((REG32(ADR_SPIMST_CEN)) & 0x00000001 ) >> 0) #define GET_SPIMST_SCLK_RATE (((REG32(ADR_SPIMST_SCLK_RATE)) & 0x0000ffff ) >> 0) #define GET_SPIMST_TXFIFO_TH (((REG32(ADR_SPIMST_TXFIFO_TH)) & 0x0000000f ) >> 0) #define GET_SPIMST_RXFIFO_TH (((REG32(ADR_SPIMST_RXFIFO_TH)) & 0x0000000f ) >> 0) #define GET_TRXBUSYFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000001 ) >> 0) #define GET_TXNOTFULLFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000002 ) >> 1) #define GET_TXEMPTYFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000004 ) >> 2) #define GET_RXNOTEMPTYFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000008 ) >> 3) #define GET_RXFULLFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000010 ) >> 4) #define GET_TXERRORFLAG (((REG32(ADR_SPIMST_STATUS)) & 0x00000020 ) >> 5) #define GET_SPIMST_TXE_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000001 ) >> 0) #define GET_SPIMST_TXO_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000002 ) >> 1) #define GET_SPIMST_RXU_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000004 ) >> 2) #define GET_SPIMST_RXO_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000008 ) >> 3) #define GET_SPIMST_RXF_INT_UNMASK (((REG32(ADR_SPIMST_INT_MASK)) & 0x00000010 ) >> 4) #define GET_SPIMST_TXE_INT (((REG32(ADR_SPIMST_INT)) & 0x00000001 ) >> 0) #define GET_SPIMST_TXO_INT (((REG32(ADR_SPIMST_INT)) & 0x00000002 ) >> 1) #define GET_SPIMST_RXU_INT (((REG32(ADR_SPIMST_INT)) & 0x00000004 ) >> 2) #define GET_SPIMST_RXO_INT (((REG32(ADR_SPIMST_INT)) & 0x00000008 ) >> 3) #define GET_SPIMST_RXF_INT (((REG32(ADR_SPIMST_INT)) & 0x00000010 ) >> 4) #define GET_SPIMST_TRX_DATA (((REG32(ADR_SPIMST_TRX_DATA)) & 0xffffffff ) >> 0) #define GET_SPIMST_RX_SAMPLE_DLY (((REG32(ADR_SPIMST_RX_SAMPLE_DLY)) & 0x000000ff ) >> 0) #define GET_ACR_INPRESEL (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00000001 ) >> 0) #define GET_ACR_QUERYACK (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00000002 ) >> 1) #define GET_ACR_RX_0_IRQ_ENABLE (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00000008 ) >> 3) #define GET_ACR_DMAENABLE (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00000030 ) >> 4) #define GET_ACR_DATATOKEN (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x000000c0 ) >> 6) #define GET_ACR_TXBUFSEL (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00000f00 ) >> 8) #define GET_ACR_SGDMAENABLE (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00003000 ) >> 12) #define GET_ACR_LPM_CLK_STOP (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00004000 ) >> 14) #define GET_ACR_REQERROR (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x00008000 ) >> 15) #define GET_ACR_REQLENGTH (((REG32(ADR_APPLICATION_CONTROL_REG)) & 0x07ff0000 ) >> 16) #define GET_MDAR_MEMADDR (((REG32(ADR_MEMORY_DESTINATION_ADDRESS_REG)) & 0xffffffff ) >> 0) #define GET_UDCR_MCE (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000001 ) >> 0) #define GET_UDCR_MTMS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x0000000e ) >> 1) #define GET_UDCR_LTE (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000010 ) >> 4) #define GET_UDCR_SOFTCONN (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000020 ) >> 5) #define GET_UDCR_SOFTDIS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000040 ) >> 6) #define GET_UDCR_SPI (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000100 ) >> 8) #define GET_UDCR_RWS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000200 ) >> 9) #define GET_UDCR_HNPS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000400 ) >> 10) #define GET_UDCR_LPMS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00000800 ) >> 11) #define GET_UDCR_GET_STS_CTRL (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00002000 ) >> 13) #define GET_UDCR_SET_INTF_CTRL (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00004000 ) >> 14) #define GET_UDCR_SET_CONF_CTRL (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00008000 ) >> 15) #define GET_UDCR_SYNCFRAME (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00010000 ) >> 16) #define GET_UDCR_UTD (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00020000 ) >> 17) #define GET_UDCR_DSI (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00040000 ) >> 18) #define GET_UDCR_AAHNPS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00080000 ) >> 19) #define GET_UDCR_TM_HNPR_DIS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00100000 ) >> 20) #define GET_UDCR_TM_OSRPR_DIS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x00200000 ) >> 21) #define GET_UDCR_USBTESTMODE (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x07000000 ) >> 24) #define GET_UDCR_UTME (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x08000000 ) >> 27) #define GET_UDCR_UTMS (((REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) & 0x10000000 ) >> 28) #define GET_HHR_HANDSHAKE (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00000003 ) >> 0) #define GET_HHR_ENDPOINT0_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00010000 ) >> 16) #define GET_HHR_ENDPOINT1_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00020000 ) >> 17) #define GET_HHR_ENDPOINT2_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00040000 ) >> 18) #define GET_HHR_ENDPOINT3_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00080000 ) >> 19) #define GET_HHR_ENDPOINT4_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00100000 ) >> 20) #define GET_HHR_ENDPOINT5_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00200000 ) >> 21) #define GET_HHR_ENDPOINT6_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00400000 ) >> 22) #define GET_HHR_ENDPOINT7_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x00800000 ) >> 23) #define GET_HHR_ENDPOINT8_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x01000000 ) >> 24) #define GET_HHR_ENDPOINT9_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x02000000 ) >> 25) #define GET_HHR_ENDPOINT10_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x04000000 ) >> 26) #define GET_HHR_ENDPOINT11_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x08000000 ) >> 27) #define GET_HHR_ENDPOINT12_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x10000000 ) >> 28) #define GET_HHR_ENDPOINT13_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x20000000 ) >> 29) #define GET_HHR_ENDPOINT14_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x40000000 ) >> 30) #define GET_HHR_ENDPOINT15_HALT (((REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) & 0x80000000 ) >> 31) #define GET_STR0_BMREQUSETTYPE (((REG32(ADR_SETUP_TRANSACTION_REG_0)) & 0x000000ff ) >> 0) #define GET_STR0_BREQUEST (((REG32(ADR_SETUP_TRANSACTION_REG_0)) & 0x0000ff00 ) >> 8) #define GET_STR0_WVALUE (((REG32(ADR_SETUP_TRANSACTION_REG_0)) & 0xffff0000 ) >> 16) #define GET_STR1_WINDEX (((REG32(ADR_SETUP_TRANSACTION_REG_1)) & 0x0000ffff ) >> 0) #define GET_STR1_WLENGTH (((REG32(ADR_SETUP_TRANSACTION_REG_1)) & 0xffff0000 ) >> 16) #define GET_TBCR0_BUFFEROFFSET (((REG32(ADR_TXBUFFER_CONTROL_REG_0)) & 0x000003ff ) >> 0) #define GET_TBCR0_PREINQUEUE (((REG32(ADR_TXBUFFER_CONTROL_REG_0)) & 0x00007000 ) >> 12) #define GET_TBCR0_BUFFERRESIDUE (((REG32(ADR_TXBUFFER_CONTROL_REG_0)) & 0x0fff0000 ) >> 16) #define GET_TBCR1_BUFFEROFFSET (((REG32(ADR_TXBUFFER_CONTROL_REG_1)) & 0x000003ff ) >> 0) #define GET_TBCR1_PREINQUEUE (((REG32(ADR_TXBUFFER_CONTROL_REG_1)) & 0x00007000 ) >> 12) #define GET_TBCR1_BUFFERRESIDUE (((REG32(ADR_TXBUFFER_CONTROL_REG_1)) & 0x0fff0000 ) >> 16) #define GET_TBCR2_BUFFEROFFSET (((REG32(ADR_TXBUFFER_CONTROL_REG_2)) & 0x000003ff ) >> 0) #define GET_TBCR2_PREINQUEUE (((REG32(ADR_TXBUFFER_CONTROL_REG_2)) & 0x00007000 ) >> 12) #define GET_TBCR2_BUFFERRESIDUE (((REG32(ADR_TXBUFFER_CONTROL_REG_2)) & 0x0fff0000 ) >> 16) #define GET_TBCR3_BUFFEROFFSET (((REG32(ADR_TXBUFFER_CONTROL_REG_3)) & 0x000003ff ) >> 0) #define GET_TBCR3_PREINQUEUE (((REG32(ADR_TXBUFFER_CONTROL_REG_3)) & 0x00007000 ) >> 12) #define GET_TBCR3_BUFFERRESIDUE (((REG32(ADR_TXBUFFER_CONTROL_REG_3)) & 0x0fff0000 ) >> 16) #define GET_IER_CONNECT (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000001 ) >> 0) #define GET_IER_DISCONNECT (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000002 ) >> 1) #define GET_IER_RESET (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000004 ) >> 2) #define GET_IER_SUSPEND (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000008 ) >> 3) #define GET_IER_RESUME (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000010 ) >> 4) #define GET_IER_SOF (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000020 ) >> 5) #define GET_IER_DMA_DONE (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000100 ) >> 8) #define GET_IER_DMA_ERROR (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00000200 ) >> 9) #define GET_IER_CONTROL_ENDPOINT_SETUP_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00010000 ) >> 16) #define GET_IER_CONTROL_ENDPOINT_OUT_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00020000 ) >> 17) #define GET_IER_CONTROL_ENDPOINT_IN_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00040000 ) >> 18) #define GET_IER_CONTROL_ENDPOINT_QUERY_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x00080000 ) >> 19) #define GET_IER_PEP1_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x01000000 ) >> 24) #define GET_IER_PEP2_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x02000000 ) >> 25) #define GET_IER_PEP3_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x04000000 ) >> 26) #define GET_IER_PEP4_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x08000000 ) >> 27) #define GET_IER_PEP5_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x10000000 ) >> 28) #define GET_IER_PEP6_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x20000000 ) >> 29) #define GET_IER_PEP7_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x40000000 ) >> 30) #define GET_IER_PEP8_TRANSACTION (((REG32(ADR_INTERRUPT_ENABLE_REG)) & 0x80000000 ) >> 31) #define GET_IDR_CONNECT (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000001 ) >> 0) #define GET_IDR_DISCONNECT (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000002 ) >> 1) #define GET_IDR_RESET (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000004 ) >> 2) #define GET_IDR_SUSPEND (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000008 ) >> 3) #define GET_IDR_RESUME (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000010 ) >> 4) #define GET_IDR_SOF (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000020 ) >> 5) #define GET_IDR_DMA_DONE (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000100 ) >> 8) #define GET_IDR_DMA_ERROR (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00000200 ) >> 9) #define GET_IDR_CONTROL_ENDPOINT_SETUP_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00010000 ) >> 16) #define GET_IDR_CONTROL_ENDPOINT_OUT_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00020000 ) >> 17) #define GET_IDR_CONTROL_ENDPOINT_IN_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00040000 ) >> 18) #define GET_IDR_CONTROL_ENDPOINT_QUERY_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x00080000 ) >> 19) #define GET_IDR_PEP1_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x01000000 ) >> 24) #define GET_IDR_PEP2_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x02000000 ) >> 25) #define GET_IDR_PEP3_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x04000000 ) >> 26) #define GET_IDR_PEP4_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x08000000 ) >> 27) #define GET_IDR_PEP5_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x10000000 ) >> 28) #define GET_IDR_PEP6_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x20000000 ) >> 29) #define GET_IDR_PEP7_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x40000000 ) >> 30) #define GET_IDR_PEP8_TRANSACTION (((REG32(ADR_INTERRUPT_DISABLE_REG)) & 0x80000000 ) >> 31) #define GET_ISR_CONNECT (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000001 ) >> 0) #define GET_ISR_DISCONNECT (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000002 ) >> 1) #define GET_ISR_RESET (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000004 ) >> 2) #define GET_ISR_SUSPEND (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000008 ) >> 3) #define GET_ISR_RESUME (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000010 ) >> 4) #define GET_ISR_SOF (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000020 ) >> 5) #define GET_ISR_DMA_DONE (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000100 ) >> 8) #define GET_ISR_DMA_ERROR (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00000200 ) >> 9) #define GET_ISR_CONTROL_ENDPOINT_SETUP_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00010000 ) >> 16) #define GET_ISR_CONTROL_ENDPOINT_OUT_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00020000 ) >> 17) #define GET_ISR_CONTROL_ENDPOINT_IN_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00040000 ) >> 18) #define GET_ISR_CONTROL_ENDPOINT_QUERY_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x00080000 ) >> 19) #define GET_ISR_PEP1_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x01000000 ) >> 24) #define GET_ISR_PEP2_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x02000000 ) >> 25) #define GET_ISR_PEP3_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x04000000 ) >> 26) #define GET_ISR_PEP4_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x08000000 ) >> 27) #define GET_ISR_PEP5_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x10000000 ) >> 28) #define GET_ISR_PEP6_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x20000000 ) >> 29) #define GET_ISR_PEP7_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x40000000 ) >> 30) #define GET_ISR_PEP8_TRANSACTION (((REG32(ADR_INTERRUPT_STATUS_REG)) & 0x80000000 ) >> 31) #define GET_PIR0_CURRENTACTIVEALT0 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x0000000f ) >> 0) #define GET_PIR0_LOGICALINTERFACENUM0 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x000000f0 ) >> 4) #define GET_PIR0_CONFIGURATIONNUM0 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x00000f00 ) >> 8) #define GET_PIR0_MAXALTNUM0 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x0000f000 ) >> 12) #define GET_PIR0_CURRENTACTIVEALT1 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x000f0000 ) >> 16) #define GET_PIR0_LOGICALINTERFACENUM1 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x00f00000 ) >> 20) #define GET_PIR0_CONFIGURATIONNUM1 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0x0f000000 ) >> 24) #define GET_PIR0_MAXALTNUM1 (((REG32(ADR_PHYSICAL_INTERFACE_REG_0)) & 0xf0000000 ) >> 28) #define GET_EDR0_EP_TYPE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x00000007 ) >> 0) #define GET_EDR0_EP_DIR (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x00000008 ) >> 3) #define GET_EDR0_EP_NO (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x000000f0 ) >> 4) #define GET_EDR0_EP_ALTER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x00000f00 ) >> 8) #define GET_EDR0_EP_PHYINTERFACE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x0000f000 ) >> 12) #define GET_EDR0_EP_MAXSIZE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x07ff0000 ) >> 16) #define GET_EDR0_EP_NAK (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0x08000000 ) >> 27) #define GET_EDR0_EP_INBUFFER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) & 0xf0000000 ) >> 28) #define GET_EDR1_EP_TYPE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x00000007 ) >> 0) #define GET_EDR1_EP_DIR (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x00000008 ) >> 3) #define GET_EDR1_EP_NO (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x000000f0 ) >> 4) #define GET_EDR1_EP_ALTER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x00000f00 ) >> 8) #define GET_EDR1_EP_PHYINTERFACE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x0000f000 ) >> 12) #define GET_EDR1_EP_MAXSIZE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x07ff0000 ) >> 16) #define GET_EDR1_EP_NAK (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0x08000000 ) >> 27) #define GET_EDR1_EP_INBUFFER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) & 0xf0000000 ) >> 28) #define GET_EDR2_EP_TYPE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x00000007 ) >> 0) #define GET_EDR2_EP_DIR (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x00000008 ) >> 3) #define GET_EDR2_EP_NO (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x000000f0 ) >> 4) #define GET_EDR2_EP_ALTER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x00000f00 ) >> 8) #define GET_EDR2_EP_PHYINTERFACE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x0000f000 ) >> 12) #define GET_EDR2_EP_MAXSIZE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x07ff0000 ) >> 16) #define GET_EDR2_EP_NAK (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0x08000000 ) >> 27) #define GET_EDR2_EP_INBUFFER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) & 0xf0000000 ) >> 28) #define GET_EDR3_EP_TYPE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x00000007 ) >> 0) #define GET_EDR3_EP_DIR (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x00000008 ) >> 3) #define GET_EDR3_EP_NO (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x000000f0 ) >> 4) #define GET_EDR3_EP_ALTER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x00000f00 ) >> 8) #define GET_EDR3_EP_PHYINTERFACE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x0000f000 ) >> 12) #define GET_EDR3_EP_MAXSIZE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x07ff0000 ) >> 16) #define GET_EDR3_EP_NAK (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0x08000000 ) >> 27) #define GET_EDR3_EP_INBUFFER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) & 0xf0000000 ) >> 28) #define GET_EDR4_EP_TYPE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x00000007 ) >> 0) #define GET_EDR4_EP_DIR (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x00000008 ) >> 3) #define GET_EDR4_EP_NO (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x000000f0 ) >> 4) #define GET_EDR4_EP_ALTER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x00000f00 ) >> 8) #define GET_EDR4_EP_PHYINTERFACE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x0000f000 ) >> 12) #define GET_EDR4_EP_MAXSIZE (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x07ff0000 ) >> 16) #define GET_EDR4_EP_NAK (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0x08000000 ) >> 27) #define GET_EDR4_EP_INBUFFER (((REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) & 0xf0000000 ) >> 28) #define GET_TIMER_COUNT_VALUE (((REG32(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_0)) & 0x0000ffff ) >> 0) #define GET_TIMER_RELOAD_VALUE (((REG32(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1)) & 0x0000ffff ) >> 0) #define GET_CORECLKIN_POWER_SAVING_MODE (((REG32(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1)) & 0x00010000 ) >> 16) #define GET_TIMER_PRE_SCALE_SELECTION (((REG32(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1)) & 0x000e0000 ) >> 17) #define GET_EP4_RX_AGGREGATION_ENABLE (((REG32(ADR_USB_EP4_AGGREGATION_REG)) & 0x00000001 ) >> 0) #define GET_EP4_RX_AGGREGATION_MAX_SIZE (((REG32(ADR_USB_EP4_AGGREGATION_REG)) & 0x01ffff00 ) >> 8) #define GET_EP_ENABLE_1 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000001 ) >> 0) #define GET_EP_ENABLE_2 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000002 ) >> 1) #define GET_EP_ENABLE_3 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000004 ) >> 2) #define GET_EP_ENABLE_4 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000008 ) >> 3) #define GET_EP_ENABLE_5 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000010 ) >> 4) #define GET_EP_ENABLE_6 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000020 ) >> 5) #define GET_EP_ENABLE_7 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000040 ) >> 6) #define GET_EP_ENABLE_8 (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000080 ) >> 7) #define GET_BULK_OUT_H_POR (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000100 ) >> 8) #define GET_HCI_CONCURRENT_EN (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000200 ) >> 9) #define GET_EP3_NAK_EN (((REG32(ADR_USB_ACC_CTRL_REG_0)) & 0x00000400 ) >> 10) #define GET_EP2_DATA0 (((REG32(ADR_USB_ACC_EP2_DATA_REG_0)) & 0xffffffff ) >> 0) #define GET_EP2_DATA1 (((REG32(ADR_USB_ACC_EP2_DATA_REG_1)) & 0xffffffff ) >> 0) #define GET_ACC_SUSPEND (((REG32(ADR_USB_ACC_CTRL_REG_1)) & 0x00000001 ) >> 0) #define GET_ACC_CTRL_CS (((REG32(ADR_USB_ACC_STATUS_REG)) & 0x0000000f ) >> 0) #define GET_CMD_REG0 (((REG32(ADR_EP1_DATA_REG_0)) & 0xffffffff ) >> 0) #define GET_CMD_REG1 (((REG32(ADR_EP1_DATA_REG_1)) & 0xffffffff ) >> 0) #define GET_CMD_REG2 (((REG32(ADR_EP1_DATA_REG_2)) & 0xffffffff ) >> 0) #define GET_LPM_ALIVE (((REG32(ADR_USB_CONTROLLER_LOW_POWER_STATUS_REG)) & 0x00000001 ) >> 0) #define GET_UTMI_SUSPENDM (((REG32(ADR_USB_CONTROLLER_LOW_POWER_STATUS_REG)) & 0x00000002 ) >> 1) #define GET_ID_DIG (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_0)) & 0x00000001 ) >> 0) #define GET_DEV_WAKEUP (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_0)) & 0x00000002 ) >> 1) #define GET_XTSEL (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_1)) & 0x00000003 ) >> 0) #define GET_XCFG_LOCK_RANGE_MIN (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2)) & 0x00000007 ) >> 0) #define GET_XCFG_LOCK_RANGE_MAX (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2)) & 0x00000038 ) >> 3) #define GET_XCFG_FINE_TUNE_NUM (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2)) & 0x000001c0 ) >> 6) #define GET_XCFG_COARSE_TUNE_NUM (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2)) & 0x00000e00 ) >> 9) #define GET_XCFGO (((REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_3)) & 0x0000ffff ) >> 0) #define GET_OUTCLKSEL (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00000001 ) >> 0) #define GET_UTMI_RESET (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00000002 ) >> 1) #define GET_PLL_EN (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00000004 ) >> 2) #define GET_UTMI_DATABUS16_8 (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00000008 ) >> 3) #define GET_DEBUG_SEL (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x000000f0 ) >> 4) #define GET_VCONTROL_REG (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00000f00 ) >> 8) #define GET_VCONTROL_LD (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00001000 ) >> 12) #define GET_HS_BIST_MODE (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00002000 ) >> 13) #define GET_OSCOUTEN (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00004000 ) >> 14) #define GET_LS_EN (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) & 0x00008000 ) >> 15) #define GET_XCFGI_L (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_1)) & 0xffffffff ) >> 0) #define GET_XCFGI_M (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_2)) & 0xffffffff ) >> 0) #define GET_XCFGI_H (((REG32(ADR_USB_PHY_CTRL_STATUS_REG_3)) & 0x0000001f ) >> 0) #define GET_BCWR_ID_PULLUP (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000001 ) >> 0) #define GET_BCWR_A_VBUS_REQ (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000002 ) >> 1) #define GET_BCWR_A_SRP_DET_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000004 ) >> 2) #define GET_BCWR_B_CONN_DET (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000008 ) >> 3) #define GET_BCWR_ID_DET_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000010 ) >> 4) #define GET_BCWR_A_HNP_EN (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000020 ) >> 5) #define GET_BCWR_A_HNP_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000040 ) >> 6) #define GET_BCWR_A_IDLE_REQ (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000080 ) >> 7) #define GET_BCWR_B_DSCHA_VBUS (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000100 ) >> 8) #define GET_BCWR_B_CHRG_DP (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000200 ) >> 9) #define GET_BCWR_B_CHRG_VBUS (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000400 ) >> 10) #define GET_BCWR_B_SESS_VLD_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00000800 ) >> 11) #define GET_BCWR_B_HNP_REQ (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00001000 ) >> 12) #define GET_BCWR_B_HNP_EN (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00002000 ) >> 13) #define GET_BCWR_B_HNP_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x00004000 ) >> 14) #define GET_BCWR_TEST_MODE (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x001f0000 ) >> 16) #define GET_BCWR_DP_TIMER (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x03000000 ) >> 24) #define GET_BCWR_VBUS_TIMER (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x0c000000 ) >> 26) #define GET_BCWR_B_CONN_LDB_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x10000000 ) >> 28) #define GET_BCWR_B_CONN_SDB_CHK (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x20000000 ) >> 29) #define GET_BCWR_EHC_EN (((REG32(ADR_OTG_LINK_WRITE_REG)) & 0x40000000 ) >> 30) #define GET_MCU_ENABLE (((REG32(ADR_BRG_SW_RST)) & 0x00000001 ) >> 0) #define GET_MAC_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000002 ) >> 1) #define GET_USB_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000004 ) >> 2) #define GET_SDIO_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000008 ) >> 3) #define GET_SPI_SLV_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000010 ) >> 4) #define GET_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000020 ) >> 5) #define GET_WDT_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000080 ) >> 7) #define GET_BTCX_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00000400 ) >> 10) #define GET_US0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00001000 ) >> 12) #define GET_US1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00002000 ) >> 13) #define GET_US2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00004000 ) >> 14) #define GET_US3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00008000 ) >> 15) #define GET_MS0TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00010000 ) >> 16) #define GET_MS1TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00020000 ) >> 17) #define GET_MS2TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00040000 ) >> 18) #define GET_MS3TMR_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00080000 ) >> 19) #define GET_PLF_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00100000 ) >> 20) #define GET_ALL_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00200000 ) >> 21) #define GET_DAT_UART_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00400000 ) >> 22) #define GET_I2C_MST_SW_RST (((REG32(ADR_BRG_SW_RST)) & 0x00800000 ) >> 23) #define GET_RG_REBOOT (((REG32(ADR_BOOT)) & 0x00000001 ) >> 0) #define GET_TRAP_IMG_FLS (((REG32(ADR_BOOT)) & 0x00010000 ) >> 16) #define GET_TRAP_REBOOT (((REG32(ADR_BOOT)) & 0x00020000 ) >> 17) #define GET_TRAP_BOOT_FLS (((REG32(ADR_BOOT)) & 0x00040000 ) >> 18) #define GET_CHIP_ID_31_0 (((REG32(ADR_CHIP_ID_0)) & 0xffffffff ) >> 0) #define GET_CHIP_ID_63_32 (((REG32(ADR_CHIP_ID_1)) & 0xffffffff ) >> 0) #define GET_CHIP_ID_95_64 (((REG32(ADR_CHIP_ID_2)) & 0xffffffff ) >> 0) #define GET_CHIP_ID_127_96 (((REG32(ADR_CHIP_ID_3)) & 0xffffffff ) >> 0) #define GET_CLK_DIGI_SEL (((REG32(ADR_CLOCK_SELECTION)) & 0x0000000f ) >> 0) #define GET_CLK_USB_PHY30M_SEL (((REG32(ADR_CLOCK_SELECTION)) & 0x00000010 ) >> 4) #define GET_SYS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000001 ) >> 0) #define GET_MAC_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000002 ) >> 1) #define GET_FLASH_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000004 ) >> 2) #define GET_SDIO_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000008 ) >> 3) #define GET_SPI_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000010 ) >> 4) #define GET_UART_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000020 ) >> 5) #define GET_DMA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000040 ) >> 6) #define GET_WDT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000080 ) >> 7) #define GET_I2C_SLV_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000100 ) >> 8) #define GET_INT_CTL_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000200 ) >> 9) #define GET_BTCX_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000400 ) >> 10) #define GET_EFS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00000800 ) >> 11) #define GET_US0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00001000 ) >> 12) #define GET_US1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00002000 ) >> 13) #define GET_US2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00004000 ) >> 14) #define GET_US3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00008000 ) >> 15) #define GET_MS0TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00010000 ) >> 16) #define GET_MS1TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00020000 ) >> 17) #define GET_MS2TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00040000 ) >> 18) #define GET_MS3TMR_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00080000 ) >> 19) #define GET_SPI_MST2CBRA_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00100000 ) >> 20) #define GET_AHB2PKT_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00200000 ) >> 21) #define GET_PWM_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00400000 ) >> 22) #define GET_I2C_MST_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x00800000 ) >> 23) #define GET_RESET_N_CPUN10 (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x01000000 ) >> 24) #define GET_USB_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x02000000 ) >> 25) #define GET_CLK_EN_USB_PHY30M (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x04000000 ) >> 26) #define GET_CLK_EN_USB_CTRLUTMI (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x08000000 ) >> 27) #define GET_PHY_IQ_LOG_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x10000000 ) >> 28) #define GET_SPIMAS_CLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x20000000 ) >> 29) #define GET_I2S_PCLK_EN (((REG32(ADR_PLATFORM_CLOCK_ENABLE)) & 0x40000000 ) >> 30) #define GET_CLK_EN_PHYRF40M (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000001 ) >> 0) #define GET_CLK_EN_PHYRF80M (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1) #define GET_CLK_EN_160M_PHY (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000004 ) >> 2) #define GET_BTCX_CSR_CLK_EN (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10) #define GET_CLK_EN_MBIST (((REG32(ADR_SYS_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11) #define GET_R_BOOTSTRAP_SAMPLE (((REG32(ADR_BOOTSTRAP_SAMPLE)) & 0x0000000f ) >> 0) #define GET_N10_CORE_CURRENT_PC (((REG32(ADR_N10_DBG1)) & 0xffffffff ) >> 0) #define GET_N10_STANDBY_REQ (((REG32(ADR_N10_DBG2)) & 0x08000000 ) >> 27) #define GET_N10_CORE_STANDBY_MODE (((REG32(ADR_N10_DBG2)) & 0x10000000 ) >> 28) #define GET_N10_CORE_DEBUG_MODE (((REG32(ADR_N10_DBG2)) & 0x20000000 ) >> 29) #define GET_N10_STANDBY (((REG32(ADR_N10_DBG2)) & 0x40000000 ) >> 30) #define GET_N10_WAKEUP_OK (((REG32(ADR_N10_DBG2)) & 0x80000000 ) >> 31) #define GET_SYS_CLOCK_STATE (((REG32(ADR_ROPMUSTATE)) & 0x00000007 ) >> 0) #define GET_ROM_READ_PROT (((REG32(ADR_ROM_READ_PROT)) & 0x00000001 ) >> 0) #define GET_GPIO_STOP_SEL (((REG32(ADR_GPIO_IQ_LOG_STOP)) & 0x007fffff ) >> 0) #define GET_GPIO_STOP_POL (((REG32(ADR_GPIO_IQ_LOG_STOP)) & 0x40000000 ) >> 30) #define GET_GPIO_STOP_EN (((REG32(ADR_GPIO_IQ_LOG_STOP)) & 0x80000000 ) >> 31) #define GET_TB_ADR_SEL (((REG32(ADR_TB_ADR_SEL)) & 0x0000ffff ) >> 0) #define GET_TB_CS (((REG32(ADR_TB_ADR_SEL)) & 0x80000000 ) >> 31) #define GET_TB_RDATA (((REG32(ADR_TB_RDATA)) & 0xffffffff ) >> 0) #define GET_UART_W2B_EN (((REG32(ADR_UART_W2B)) & 0x00000001 ) >> 0) #define GET_SYSCTRL_CMD (((REG32(ADR_SYSCTRL_COMMAND)) & 0xffffffff ) >> 0) #define GET_CLK_FBUS_SEL (((REG32(ADR_FBUS_CLK_SEL)) & 0x0000000f ) >> 0) #define GET_SYS_XOSC_ON (((REG32(ADR_SYSCTRL_STATUS)) & 0x00000001 ) >> 0) #define GET_SYS_DPLL_ON (((REG32(ADR_SYSCTRL_STATUS)) & 0x00000002 ) >> 1) #define GET_FSM_SYSCTRL (((REG32(ADR_SYSCTRL_STATUS)) & 0x00001f00 ) >> 8) #define GET_I2SMAS_CLK_DIV (((REG32(ADR_I2SMAS_CFG)) & 0x00003fff ) >> 0) #define GET_I2S_MCLK_DIV (((REG32(ADR_I2SMAS_CFG)) & 0x00030000 ) >> 16) #define GET_I2S_MASTER (((REG32(ADR_I2SMAS_CFG)) & 0x80000000 ) >> 31) #define GET_HBUSREQ_LOCK (((REG32(ADR_HBUSREQ_LOCK)) & 0x00001fff ) >> 0) #define GET_HBURST_LOCK (((REG32(ADR_HBURST_LOCK)) & 0x00001fff ) >> 0) #define GET_FENCE_HIT_ADR (((REG32(ADR_FENCE_CTRL)) & 0x001fffff ) >> 0) #define GET_EDLM_SRAM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x08000000 ) >> 27) #define GET_EILM_ROM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x10000000 ) >> 28) #define GET_EILM_SRAM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x20000000 ) >> 29) #define GET_FBUS_SRAM_ERRCK_EN (((REG32(ADR_FENCE_CTRL)) & 0x40000000 ) >> 30) #define GET_FENCE_HIT_EN (((REG32(ADR_FENCE_CTRL)) & 0x80000000 ) >> 31) #define GET_EDLM_SRAM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000001 ) >> 0) #define GET_EILM_ROM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000002 ) >> 1) #define GET_EILM_SRAM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000004 ) >> 2) #define GET_FBUS_SRAM_ERR_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000008 ) >> 3) #define GET_FENCE_HIT_INT (((REG32(ADR_FENCE_STATUS)) & 0x00000010 ) >> 4) #define GET_TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0 (((REG32(ADR_POWER_SW_INFO)) & 0x00000001 ) >> 0) #define GET_TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0 (((REG32(ADR_POWER_SW_INFO)) & 0x00000002 ) >> 1) #define GET_TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0 (((REG32(ADR_POWER_SW_INFO)) & 0x00000004 ) >> 2) #define GET_VIAROM_EMA (((REG32(ADR_VIAROM_EMA)) & 0x00000007 ) >> 0) #define GET_TEST_MODE0 (((REG32(ADR_TEST_MODE)) & 0x00000001 ) >> 0) #define GET_TEST_MODE1 (((REG32(ADR_TEST_MODE)) & 0x00000002 ) >> 1) #define GET_TEST_MODE2 (((REG32(ADR_TEST_MODE)) & 0x00000004 ) >> 2) #define GET_TEST_MODE3 (((REG32(ADR_TEST_MODE)) & 0x00000008 ) >> 3) #define GET_TEST_MODE4 (((REG32(ADR_TEST_MODE)) & 0x00000010 ) >> 4) #define GET_TEST_MODE_ALL (((REG32(ADR_TEST_MODE)) & 0x00000020 ) >> 5) #define GET_CLK_EN_CPUN10 (((REG32(ADR_MANUAL_RESET_N)) & 0x00000002 ) >> 1) #define GET_N10_WARM_RESET_N (((REG32(ADR_MANUAL_RESET_N)) & 0x00000004 ) >> 2) #define GET_FW_EVENT (((REG32(ADR_DEBUG_FIRMWARE_EVENT_FLAG)) & 0xffffffff ) >> 0) #define GET_HOST_EVENT (((REG32(ADR_DEBUG_HOST_EVENT_FLAG)) & 0xffffffff ) >> 0) #define GET_CHIP_INFO_ID_31_0 (((REG32(ADR_CHIP_INFO_ID_0)) & 0xffffffff ) >> 0) #define GET_CHIP_INFO_ID_63_32 (((REG32(ADR_CHIP_INFO_ID_1)) & 0xffffffff ) >> 0) #define GET_CHIP_VER (((REG32(ADR_CHIP_TYPE_VER)) & 0x00ffffff ) >> 0) #define GET_CHIP_TYPE (((REG32(ADR_CHIP_TYPE_VER)) & 0xff000000 ) >> 24) #define GET_CHIP_DATE_YYYYMMDD (((REG32(ADR_CHIP_DATE_YYYYMMDD)) & 0xffffffff ) >> 0) #define GET_CHIP_DATE_00HHMMSS (((REG32(ADR_CHIP_DATE_00HHMMSS)) & 0x00ffffff ) >> 0) #define GET_CHIP_GITSHA_31_0 (((REG32(ADR_CHIP_GITSHA_0)) & 0xffffffff ) >> 0) #define GET_CHIP_GITSHA_63_32 (((REG32(ADR_CHIP_GITSHA_1)) & 0xffffffff ) >> 0) #define GET_CHIP_GITSHA_95_64 (((REG32(ADR_CHIP_GITSHA_2)) & 0xffffffff ) >> 0) #define GET_CHIP_GITSHA_127_96 (((REG32(ADR_CHIP_GITSHA_3)) & 0xffffffff ) >> 0) #define GET_CHIP_GITSHA_159_128 (((REG32(ADR_CHIP_GITSHA_4)) & 0xffffffff ) >> 0) #define GET_N10CFG_DEFAULT_IVB (((REG32(ADR_N10CFG_DEF_IVB)) & 0x0000ffff ) >> 0) #define GET_SYS_N10_IVB_VAL (((REG32(ADR_N10CFG_SETTING)) & 0xffff0000 ) >> 16) #define GET_USB20_HOST_SELRW (((REG32(ADR_USB20_HOST_SEL)) & 0x00000001 ) >> 0) #define GET_CHIP_INFO_FPGA_TAG (((REG32(ADR_CHIP_INFO_FPGATAG)) & 0xffffffff ) >> 0) #define GET_SYS_PMU_MODE_TRAN_INT (((REG32(ADR_PMU_MODE_TRAN_INT)) & 0x00000001 ) >> 0) #define GET_DBG_WRITE_TO_FINISH_SIM (((REG32(ADR_DEBUG_SIM_FINISH)) & 0x00000001 ) >> 0) #define GET_DATA_SPI_WAKEUP (((REG32(ADR_ALWAYS_ON_CFG00)) & 0x00000001 ) >> 0) #define GET_WAKE_SOON_WITH_SCK (((REG32(ADR_SDIO_RESET_WAKE_CFG)) & 0x00000001 ) >> 0) #define GET_ALLOW_SD_SPI_RESET (((REG32(ADR_SDIO_RESET_WAKE_CFG)) & 0x00000002 ) >> 1) #define GET_WDT_MCU_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000001 ) >> 0) #define GET_WDT_SYS_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000002 ) >> 1) #define GET_SDIO_CMD52_06H_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000004 ) >> 2) #define GET_DATA_SPI_RESET (((REG32(ADR_BOOT_INFO)) & 0x00000008 ) >> 3) #define GET_UART_NRTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000001 ) >> 0) #define GET_UART_NCTS (((REG32(ADR_SPARE_UART_INFO)) & 0x00000002 ) >> 1) #define GET_NORMAL_PWR_ON1 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000001 ) >> 0) #define GET_NORMAL_PWR_ON2 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000002 ) >> 1) #define GET_NORMAL_PWR_ON3 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000004 ) >> 2) #define GET_SUSPEND_PWR_ON1 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000010 ) >> 4) #define GET_SUSPEND_PWR_ON2 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000020 ) >> 5) #define GET_SUSPEND_PWR_ON3 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000040 ) >> 6) #define GET_NORMAL_ISO_ON1 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000100 ) >> 8) #define GET_NORMAL_ISO_ON2 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000200 ) >> 9) #define GET_NORMAL_ISO_ON3 (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00000400 ) >> 10) #define GET_TOP_ON1_RST_N (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00001000 ) >> 12) #define GET_TOP_ON2_RST_N (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00002000 ) >> 13) #define GET_TOP_ON3_RST_N (((REG32(ADR_POWER_ON_OFF_CTRL)) & 0x00004000 ) >> 14) #define GET_HOST_WAKE_WIFI (((REG32(ADR_HOST_WAKE_WIFI_CTRL)) & 0x007fffff ) >> 0) #define GET_HOST_WAKE_WIFI_POL (((REG32(ADR_HOST_WAKE_WIFI_CTRL)) & 0x80000000 ) >> 31) #define GET_PRESCALER_US (((REG32(ADR_PRESCALER_USTIMER)) & 0x000001ff ) >> 0) #define GET_RTC_TIMER_WAKE_PMU_EN (((REG32(ADR_WAKE_PMU_ENABLE)) & 0x00000001 ) >> 0) #define GET_USB_WAKE_PMU_EN (((REG32(ADR_WAKE_PMU_ENABLE)) & 0x00000002 ) >> 1) #define GET_ILM160KB_EN (((REG32(ADR_SRAMCFG_SETTING)) & 0x00000002 ) >> 1) #define GET_PATCH00_EN (((REG32(ADR_ROM_PATCH00_0)) & 0x00000001 ) >> 0) #define GET_PATCH00_ADDR (((REG32(ADR_ROM_PATCH00_0)) & 0x0001fffc ) >> 2) #define GET_PATCH00_DATA (((REG32(ADR_ROM_PATCH00_1)) & 0xffffffff ) >> 0) #define GET_PATCH01_EN (((REG32(ADR_ROM_PATCH01_0)) & 0x00000001 ) >> 0) #define GET_PATCH01_ADDR (((REG32(ADR_ROM_PATCH01_0)) & 0x0001fffc ) >> 2) #define GET_PATCH01_DATA (((REG32(ADR_ROM_PATCH01_1)) & 0xffffffff ) >> 0) #define GET_TU0_TM_INIT_VALUE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TU0_TM_MODE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TU0_TM_INT_STS_DONE (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TU0_TM_INT_MASK (((REG32(ADR_TU0_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TU0_TM_CUR_VALUE (((REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TU0_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TU1_TM_INIT_VALUE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TU1_TM_MODE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TU1_TM_INT_STS_DONE (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TU1_TM_INT_MASK (((REG32(ADR_TU1_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TU1_TM_CUR_VALUE (((REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TU1_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TU2_TM_INIT_VALUE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TU2_TM_MODE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TU2_TM_INT_STS_DONE (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TU2_TM_INT_MASK (((REG32(ADR_TU2_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TU2_TM_CUR_VALUE (((REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TU2_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TU3_TM_INIT_VALUE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TU3_TM_MODE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TU3_TM_INT_STS_DONE (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TU3_TM_INT_MASK (((REG32(ADR_TU3_MICROSECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TU3_TM_CUR_VALUE (((REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TU3_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TM0_TM_INIT_VALUE (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TM0_TM_MODE (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TM0_TM_INT_STS_DONE (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TM0_TM_INT_MASK (((REG32(ADR_TM0_MILLISECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TM0_TM_CUR_VALUE (((REG32(ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TM0_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM0_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TM1_TM_INIT_VALUE (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TM1_TM_MODE (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TM1_TM_INT_STS_DONE (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TM1_TM_INT_MASK (((REG32(ADR_TM1_MILLISECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TM1_TM_CUR_VALUE (((REG32(ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TM1_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM1_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TM2_TM_INIT_VALUE (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TM2_TM_MODE (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TM2_TM_INT_STS_DONE (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TM2_TM_INT_MASK (((REG32(ADR_TM2_MILLISECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TM2_TM_CUR_VALUE (((REG32(ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TM2_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM2_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0) #define GET_TM3_TM_INIT_VALUE (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x0000ffff ) >> 0) #define GET_TM3_TM_MODE (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x00010000 ) >> 16) #define GET_TM3_TM_INT_STS_DONE (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x00020000 ) >> 17) #define GET_TM3_TM_INT_MASK (((REG32(ADR_TM3_MILLISECOND_TIMER)) & 0x00040000 ) >> 18) #define GET_TM3_TM_CUR_VALUE (((REG32(ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE)) & 0x0000ffff ) >> 0) #define GET_TM3_PRESCALER_USTIMER_LOCAL (((REG32(ADR_TM3_MILLISECOND_TIMER_PRESCALE)) & 0x000001ff ) >> 0) #define GET_MCU_WDT_TIME_CNT (((REG32(ADR_MCU_WDOG_REG)) & 0x0000ffff ) >> 0) #define GET_MCU_WDT_INT_CNT_OFS (((REG32(ADR_MCU_WDOG_REG)) & 0x00ff0000 ) >> 16) #define GET_MCU_WDT_STATUS (((REG32(ADR_MCU_WDOG_REG)) & 0x40000000 ) >> 30) #define GET_MCU_WDOG_ENA (((REG32(ADR_MCU_WDOG_REG)) & 0x80000000 ) >> 31) #define GET_SYS_WDT_TIME_CNT (((REG32(ADR_SYS_WDOG_REG)) & 0x0000ffff ) >> 0) #define GET_SYS_WDT_INT_CNT_OFS (((REG32(ADR_SYS_WDOG_REG)) & 0x00ff0000 ) >> 16) #define GET_SYS_WDT_STATUS (((REG32(ADR_SYS_WDOG_REG)) & 0x40000000 ) >> 30) #define GET_SYS_WDOG_ENA (((REG32(ADR_SYS_WDOG_REG)) & 0x80000000 ) >> 31) #define GET_PWM_POST_SCALER_0 (((REG32(ADR_PWM_0_CTRL)) & 0x000000ff ) >> 0) #define GET_PWM_SETTING_UPDATE_0 (((REG32(ADR_PWM_0_CTRL)) & 0x10000000 ) >> 28) #define GET_PWM_ALWAYSON_0 (((REG32(ADR_PWM_0_CTRL)) & 0x20000000 ) >> 29) #define GET_PWM_INVERT_0 (((REG32(ADR_PWM_0_CTRL)) & 0x40000000 ) >> 30) #define GET_PWM_ENABLE_0 (((REG32(ADR_PWM_0_CTRL)) & 0x80000000 ) >> 31) #define GET_PWM_INI_VALUE_PERIOD_0 (((REG32(ADR_PWM_0_SET)) & 0x0000ffff ) >> 0) #define GET_PWM_INI_VALUE_P_0 (((REG32(ADR_PWM_0_SET)) & 0xffff0000 ) >> 16) #define GET_PWM_POST_SCALER_1 (((REG32(ADR_PWM_1_CTRL)) & 0x000000ff ) >> 0) #define GET_PWM_SETTING_UPDATE_1 (((REG32(ADR_PWM_1_CTRL)) & 0x10000000 ) >> 28) #define GET_PWM_ALWAYSON_1 (((REG32(ADR_PWM_1_CTRL)) & 0x20000000 ) >> 29) #define GET_PWM_INVERT_1 (((REG32(ADR_PWM_1_CTRL)) & 0x40000000 ) >> 30) #define GET_PWM_ENABLE_1 (((REG32(ADR_PWM_1_CTRL)) & 0x80000000 ) >> 31) #define GET_PWM_INI_VALUE_PERIOD_1 (((REG32(ADR_PWM_1_SET)) & 0x0000ffff ) >> 0) #define GET_PWM_INI_VALUE_P_1 (((REG32(ADR_PWM_1_SET)) & 0xffff0000 ) >> 16) #define GET_PWM_POST_SCALER_2 (((REG32(ADR_PWM_2_CTRL)) & 0x000000ff ) >> 0) #define GET_PWM_SETTING_UPDATE_2 (((REG32(ADR_PWM_2_CTRL)) & 0x10000000 ) >> 28) #define GET_PWM_ALWAYSON_2 (((REG32(ADR_PWM_2_CTRL)) & 0x20000000 ) >> 29) #define GET_PWM_INVERT_2 (((REG32(ADR_PWM_2_CTRL)) & 0x40000000 ) >> 30) #define GET_PWM_ENABLE_2 (((REG32(ADR_PWM_2_CTRL)) & 0x80000000 ) >> 31) #define GET_PWM_INI_VALUE_PERIOD_2 (((REG32(ADR_PWM_2_SET)) & 0x0000ffff ) >> 0) #define GET_PWM_INI_VALUE_P_2 (((REG32(ADR_PWM_2_SET)) & 0xffff0000 ) >> 16) #define GET_PWM_POST_SCALER_3 (((REG32(ADR_PWM_3_CTRL)) & 0x000000ff ) >> 0) #define GET_PWM_SETTING_UPDATE_3 (((REG32(ADR_PWM_3_CTRL)) & 0x10000000 ) >> 28) #define GET_PWM_ALWAYSON_3 (((REG32(ADR_PWM_3_CTRL)) & 0x20000000 ) >> 29) #define GET_PWM_INVERT_3 (((REG32(ADR_PWM_3_CTRL)) & 0x40000000 ) >> 30) #define GET_PWM_ENABLE_3 (((REG32(ADR_PWM_3_CTRL)) & 0x80000000 ) >> 31) #define GET_PWM_INI_VALUE_PERIOD_3 (((REG32(ADR_PWM_3_SET)) & 0x0000ffff ) >> 0) #define GET_PWM_INI_VALUE_P_3 (((REG32(ADR_PWM_3_SET)) & 0xffff0000 ) >> 16) #define GET_PWM_POST_SCALER_4 (((REG32(ADR_PWM_4_CTRL)) & 0x000000ff ) >> 0) #define GET_PWM_SETTING_UPDATE_4 (((REG32(ADR_PWM_4_CTRL)) & 0x10000000 ) >> 28) #define GET_PWM_ALWAYSON_4 (((REG32(ADR_PWM_4_CTRL)) & 0x20000000 ) >> 29) #define GET_PWM_INVERT_4 (((REG32(ADR_PWM_4_CTRL)) & 0x40000000 ) >> 30) #define GET_PWM_ENABLE_4 (((REG32(ADR_PWM_4_CTRL)) & 0x80000000 ) >> 31) #define GET_PWM_INI_VALUE_PERIOD_4 (((REG32(ADR_PWM_4_SET)) & 0x0000ffff ) >> 0) #define GET_PWM_INI_VALUE_P_4 (((REG32(ADR_PWM_4_SET)) & 0xffff0000 ) >> 16) #define GET_MANUAL_IO (((REG32(ADR_MANUAL_IO)) & 0x007fffff ) >> 0) #define GET_MANUAL_PU (((REG32(ADR_MANUAL_PU)) & 0x007fffff ) >> 0) #define GET_MANUAL_PD (((REG32(ADR_MANUAL_PD)) & 0x007fffff ) >> 0) #define GET_MANUAL_DS (((REG32(ADR_MANUAL_DS)) & 0x007fffff ) >> 0) #define GET_IO_PO (((REG32(ADR_IO_PO)) & 0x007fffff ) >> 0) #define GET_IO_PI (((REG32(ADR_IO_PI)) & 0x007fffff ) >> 0) #define GET_IO_PIE (((REG32(ADR_IO_PIE)) & 0x007fffff ) >> 0) #define GET_IO_POEN (((REG32(ADR_IO_POEN)) & 0x007fffff ) >> 0) #define GET_IO_PUE (((REG32(ADR_IO_PUE)) & 0x007fffff ) >> 0) #define GET_IO_PDE (((REG32(ADR_IO_PDE)) & 0x007fffff ) >> 0) #define GET_IO_DS (((REG32(ADR_IO_DS)) & 0x007fffff ) >> 0) #define GET_SEL_I2STRX_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00000001 ) >> 0) #define GET_SEL_I2STRX_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00000002 ) >> 1) #define GET_SEL_SPI_SLV (((REG32(ADR_IO_FUNC_SEL)) & 0x00000004 ) >> 2) #define GET_SEL_SPI_MST (((REG32(ADR_IO_FUNC_SEL)) & 0x00000008 ) >> 3) #define GET_SEL_I2C_SLV (((REG32(ADR_IO_FUNC_SEL)) & 0x00000010 ) >> 4) #define GET_SEL_I2C_MST_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00000020 ) >> 5) #define GET_SEL_I2C_MST_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00000040 ) >> 6) #define GET_SEL_UART0_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00000080 ) >> 7) #define GET_SEL_UART0_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00000100 ) >> 8) #define GET_SEL_BTCX (((REG32(ADR_IO_FUNC_SEL)) & 0x00000200 ) >> 9) #define GET_SEL_FLASH (((REG32(ADR_IO_FUNC_SEL)) & 0x00000400 ) >> 10) #define GET_SEL_RF (((REG32(ADR_IO_FUNC_SEL)) & 0x00000800 ) >> 11) #define GET_SEL_PWM (((REG32(ADR_IO_FUNC_SEL)) & 0x0001f000 ) >> 12) #define GET_SEL_DEBUG_I (((REG32(ADR_IO_FUNC_SEL)) & 0x00020000 ) >> 17) #define GET_SEL_DEBUG_II (((REG32(ADR_IO_FUNC_SEL)) & 0x00040000 ) >> 18) #define GET_SEL_MEM_BIST (((REG32(ADR_IO_FUNC_SEL)) & 0x00080000 ) >> 19) #define GET_SEL_USB_BIST (((REG32(ADR_IO_FUNC_SEL)) & 0x00100000 ) >> 20) #define GET_SEL_USB_TEST (((REG32(ADR_IO_FUNC_SEL)) & 0x00200000 ) >> 21) #define GET_SEL_USB_IDDQ (((REG32(ADR_IO_FUNC_SEL)) & 0x00400000 ) >> 22) #define GET_I2S_RAW_DATA (((REG32(ADR_IO_FUNC_SEL)) & 0x40000000 ) >> 30) #define GET_SPI_RAW_DATA (((REG32(ADR_IO_FUNC_SEL)) & 0x80000000 ) >> 31) #define GET_SEL_GPO_INT (((REG32(ADR_INT_THRU_GPIO)) & 0x007fffff ) >> 0) #define GET_ROM_START_INDEX (((REG32(ADR_BIST_CTRL)) & 0x0000000f ) >> 0) #define GET_ROM_END_INDEX (((REG32(ADR_BIST_CTRL)) & 0x000000f0 ) >> 4) #define GET_ROMCRC32_GOLDEN (((REG32(ADR_BIST_CTRL1)) & 0xffffffff ) >> 0) #define GET_ROMCRC32_RESULT (((REG32(ADR_BIST_CTRL2)) & 0xffffffff ) >> 0) #define GET_I2CS_ADDR_DC (((REG32(ADR_I2CS_ID_ADDR)) & 0x00000001 ) >> 0) #define GET_I2CS_ADDR (((REG32(ADR_I2CS_ID_ADDR)) & 0x000000fe ) >> 1) #define GET_I2CS_INT (((REG32(ADR_I2CS_STATUS)) & 0x0000001f ) >> 0) #define GET_I2CS_IDLE (((REG32(ADR_I2CS_STATUS)) & 0x00000400 ) >> 10) #define GET_I2CS_TIME_OUT_CNT (((REG32(ADR_I2CS_TIME_CNT)) & 0x0000ffff ) >> 0) #define GET_I2CS_STATE (((REG32(ADR_I2CS_STATE)) & 0x000000ff ) >> 0) #define GET_I2CS_DATA_CONFIG (((REG32(ADR_I2CS_CTRL)) & 0x00000001 ) >> 0) #define GET_I2CS_HOLD_BUS_EN (((REG32(ADR_I2CS_CTRL)) & 0x00000002 ) >> 1) #define GET_IO_PORT_REG (((REG32(ADR_IO_PORT_REG)) & 0x0001ffff ) >> 0) #define GET_MASK_RX_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000001 ) >> 0) #define GET_EDCA4_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000002 ) >> 1) #define GET_MASK_SOC_SYSTEM_INT (((REG32(ADR_INT_MASK_REG)) & 0x00000004 ) >> 2) #define GET_EDCA0_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000008 ) >> 3) #define GET_EDCA1_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000010 ) >> 4) #define GET_EDCA2_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000020 ) >> 5) #define GET_EDCA3_LOW_THR_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000040 ) >> 6) #define GET_TX_LIMIT_INT_MASK (((REG32(ADR_INT_MASK_REG)) & 0x00000080 ) >> 7) #define GET_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000001 ) >> 0) #define GET_EDCA4_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000002 ) >> 1) #define GET_SOC_SYSTEM_INT_STATUS (((REG32(ADR_INT_STATUS_REG)) & 0x00000004 ) >> 2) #define GET_EDCA0_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000008 ) >> 3) #define GET_EDCA1_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000010 ) >> 4) #define GET_EDCA2_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000020 ) >> 5) #define GET_EDCA3_LOW_THR_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000040 ) >> 6) #define GET_TX_LIMIT_INT_STS (((REG32(ADR_INT_STATUS_REG)) & 0x00000080 ) >> 7) #define GET_HOST_TRIGGERED_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000100 ) >> 8) #define GET_HOST_TRIGGERED_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000200 ) >> 9) #define GET_SOC_TRIGGER_RX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000400 ) >> 10) #define GET_SOC_TRIGGER_TX_INT (((REG32(ADR_INT_STATUS_REG)) & 0x00000800 ) >> 11) #define GET_RDY_FOR_TX_RX (((REG32(ADR_FN1_STATUS_REG)) & 0x00000001 ) >> 0) #define GET_RDY_FOR_FW_DOWNLOAD (((REG32(ADR_FN1_STATUS_REG)) & 0x00000002 ) >> 1) #define GET_ILLEGAL_CMD_RESP_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000004 ) >> 2) #define GET_SDIO_TRX_DATA_SEQUENCE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000008 ) >> 3) #define GET_GPIO_INT_TRIGGER_OPTION (((REG32(ADR_FN1_STATUS_REG)) & 0x00000010 ) >> 4) #define GET_TRIGGER_FUNCTION_SETTING (((REG32(ADR_FN1_STATUS_REG)) & 0x00000060 ) >> 5) #define GET_CMD52_ABORT_RESPONSE (((REG32(ADR_FN1_STATUS_REG)) & 0x00000080 ) >> 7) #define GET_CARD_RCA_REG (((REG32(ADR_CARD_RCA_REG)) & 0x0000ffff ) >> 0) #define GET_SDIO_BYTE_MODE_BATCH_SIZE_REG (((REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) & 0x000000ff ) >> 0) #define GET_SDIO_CARD_STATUS_REG (((REG32(ADR_SDIO_CARD_STATUS_REG)) & 0xffffffff ) >> 0) #define GET_R5_RESPONSE_FLAG (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x000000ff ) >> 0) #define GET_MCU_TO_SDIO_INFO_MASK (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00010000 ) >> 16) #define GET_INT_THROUGH_PIN (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00020000 ) >> 17) #define GET_DIRECT_INT_MUX_MODE (((REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) & 0x00040000 ) >> 18) #define GET_SD_CMD_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00000007 ) >> 0) #define GET_SD_CMD_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00000070 ) >> 4) #define GET_SD_DAT_3_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00000700 ) >> 8) #define GET_SD_DAT_3_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00007000 ) >> 12) #define GET_SD_DAT_2_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00070000 ) >> 16) #define GET_SD_DAT_2_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x00700000 ) >> 20) #define GET_SD_DAT_1_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x07000000 ) >> 24) #define GET_SD_DAT_1_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_0)) & 0x70000000 ) >> 28) #define GET_SD_DAT_0_IN_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_1)) & 0x00000007 ) >> 0) #define GET_SD_DAT_0_OUT_DLY_SEL (((REG32(ADR_SDIO_DELAY_CHAIN_1)) & 0x00000070 ) >> 4) #define GET_FN1_DMA_START_ADDR_REG (((REG32(ADR_FN1_DMA_START_ADDR_REG)) & 0xffffffff ) >> 0) #define GET_SDIO_TO_MCU_INFO (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x000000ff ) >> 0) #define GET_SDIO_PARTIAL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000100 ) >> 8) #define GET_SDIO_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000200 ) >> 9) #define GET_PERI_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000400 ) >> 10) #define GET_MAC_ALL_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00000800 ) >> 11) #define GET_AHB_BRIDGE_RESET (((REG32(ADR_FN1_INT_CTRL_RESET)) & 0x00001000 ) >> 12) #define GET_MCU_TO_SDIO_INFO (((REG32(ADR_MCU_NOTIFY_HOST_EVENT)) & 0x000000ff ) >> 0) #define GET_RAW_IDLE (((REG32(ADR_MCU_NOTIFY_HOST_EVENT)) & 0x00000100 ) >> 8) #define GET_PEDGE_MODE (((REG32(ADR_MCU_NOTIFY_HOST_EVENT)) & 0x00000200 ) >> 9) #define GET_RAW_CLEAR (((REG32(ADR_MCU_NOTIFY_HOST_EVENT)) & 0x00000400 ) >> 10) #define GET_RAW_STATE (((REG32(ADR_MCU_NOTIFY_HOST_EVENT)) & 0x00001800 ) >> 11) #define GET_FN1_DMA_RD_START_ADDR_REG (((REG32(ADR_FN1_DMA_RD_START_ADDR_REG)) & 0xffffffff ) >> 0) #define GET_CCCR_00H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x000000ff ) >> 0) #define GET_CCCR_02H_REG (((REG32(ADR_CCCR_00H_REG)) & 0x00ff0000 ) >> 16) #define GET_CCCR_03H_REG (((REG32(ADR_CCCR_00H_REG)) & 0xff000000 ) >> 24) #define GET_CCCR_04H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000000ff ) >> 0) #define GET_CCCR_05H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x0000ff00 ) >> 8) #define GET_CCCR_06H_REG (((REG32(ADR_CCCR_04H_REG)) & 0x000f0000 ) >> 16) #define GET_CCCR_07H_REG (((REG32(ADR_CCCR_04H_REG)) & 0xff000000 ) >> 24) #define GET_SUPPORT_DIRECT_COMMAND_SDIO (((REG32(ADR_CCCR_08H_REG)) & 0x00000001 ) >> 0) #define GET_SUPPORT_MULTIPLE_BLOCK_TRANSFER (((REG32(ADR_CCCR_08H_REG)) & 0x00000002 ) >> 1) #define GET_SUPPORT_READ_WAIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000004 ) >> 2) #define GET_SUPPORT_BUS_CONTROL (((REG32(ADR_CCCR_08H_REG)) & 0x00000008 ) >> 3) #define GET_SUPPORT_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000010 ) >> 4) #define GET_ENABLE_BLOCK_GAP_INTERRUPT (((REG32(ADR_CCCR_08H_REG)) & 0x00000020 ) >> 5) #define GET_LOW_SPEED_CARD (((REG32(ADR_CCCR_08H_REG)) & 0x00000040 ) >> 6) #define GET_LOW_SPEED_CARD_4BIT (((REG32(ADR_CCCR_08H_REG)) & 0x00000080 ) >> 7) #define GET_COMMON_CIS_PONTER (((REG32(ADR_CCCR_08H_REG)) & 0x01ffff00 ) >> 8) #define GET_SD_SSDR50 (((REG32(ADR_CCCR_14H_REG)) & 0x01000000 ) >> 24) #define GET_SD_SSDR104 (((REG32(ADR_CCCR_14H_REG)) & 0x02000000 ) >> 25) #define GET_SUPPORT_HIGH_SPEED (((REG32(ADR_CCCR_13H_REG)) & 0x01000000 ) >> 24) #define GET_BSS (((REG32(ADR_CCCR_13H_REG)) & 0x0e000000 ) >> 25) #define GET_FBR_100H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000000f ) >> 0) #define GET_CSASUPPORT (((REG32(ADR_FBR_100H_REG)) & 0x00000040 ) >> 6) #define GET_ENABLECSA (((REG32(ADR_FBR_100H_REG)) & 0x00000080 ) >> 7) #define GET_FBR_101H_REG (((REG32(ADR_FBR_100H_REG)) & 0x0000ff00 ) >> 8) #define GET_FBR_109H_REG (((REG32(ADR_FBR_109H_REG)) & 0x01ffff00 ) >> 8) #define GET_F0_CIS_CONTENT_REG_31_0 (((REG32(ADR_F0_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_63_32 (((REG32(ADR_F0_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_95_64 (((REG32(ADR_F0_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_127_96 (((REG32(ADR_F0_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_159_128 (((REG32(ADR_F0_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_191_160 (((REG32(ADR_F0_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_223_192 (((REG32(ADR_F0_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_255_224 (((REG32(ADR_F0_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_287_256 (((REG32(ADR_F0_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_319_288 (((REG32(ADR_F0_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_351_320 (((REG32(ADR_F0_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_383_352 (((REG32(ADR_F0_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_415_384 (((REG32(ADR_F0_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_447_416 (((REG32(ADR_F0_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_479_448 (((REG32(ADR_F0_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0) #define GET_F0_CIS_CONTENT_REG_511_480 (((REG32(ADR_F0_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_31_0 (((REG32(ADR_F1_CIS_CONTENT_REG_0)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_63_32 (((REG32(ADR_F1_CIS_CONTENT_REG_1)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_95_64 (((REG32(ADR_F1_CIS_CONTENT_REG_2)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_127_96 (((REG32(ADR_F1_CIS_CONTENT_REG_3)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_159_128 (((REG32(ADR_F1_CIS_CONTENT_REG_4)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_191_160 (((REG32(ADR_F1_CIS_CONTENT_REG_5)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_223_192 (((REG32(ADR_F1_CIS_CONTENT_REG_6)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_255_224 (((REG32(ADR_F1_CIS_CONTENT_REG_7)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_287_256 (((REG32(ADR_F1_CIS_CONTENT_REG_8)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_319_288 (((REG32(ADR_F1_CIS_CONTENT_REG_9)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_351_320 (((REG32(ADR_F1_CIS_CONTENT_REG_10)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_383_352 (((REG32(ADR_F1_CIS_CONTENT_REG_11)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_415_384 (((REG32(ADR_F1_CIS_CONTENT_REG_12)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_447_416 (((REG32(ADR_F1_CIS_CONTENT_REG_13)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_479_448 (((REG32(ADR_F1_CIS_CONTENT_REG_14)) & 0xffffffff ) >> 0) #define GET_F1_CIS_CONTENT_REG_511_480 (((REG32(ADR_F1_CIS_CONTENT_REG_15)) & 0xffffffff ) >> 0) #define GET_SPARE_MEM (((REG32(ADR_SPI_MODE)) & 0x000000ff ) >> 0) #define GET_TX_SEG (((REG32(ADR_TX_SEG)) & 0xffffffff ) >> 0) #define GET_CLK_WIDTH (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0x0000ffff ) >> 0) #define GET_CSN_INTER (((REG32(ADR_SPI_TO_PHY_PARAM1)) & 0xffff0000 ) >> 16) #define GET_BACK_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0x0000ffff ) >> 0) #define GET_FRONT_DLY (((REG32(ADR_SPI_TO_PHY_PARAM2)) & 0xffff0000 ) >> 16) #define GET_TWI_START_TRIG (((REG32(ADR_TWIM_EN)) & 0x00000001 ) >> 0) #define GET_TWI_STOP_TRIG (((REG32(ADR_TWIM_EN)) & 0x00000002 ) >> 1) #define GET_TWI_TRANS_CONTINUE (((REG32(ADR_TWIM_EN)) & 0x00000004 ) >> 2) #define GET_TWI_DEV_A_10B (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00000001 ) >> 0) #define GET_TWI_MODE (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00000002 ) >> 1) #define GET_SCL (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00010000 ) >> 16) #define GET_SDA (((REG32(ADR_TWIM_STATUS_SETTING)) & 0x00020000 ) >> 17) #define GET_TWI_INT_TXD_STALL_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000001 ) >> 0) #define GET_TWI_INT_RXD_STALL_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000002 ) >> 1) #define GET_TWI_INT_TRANS_FINISH_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000004 ) >> 2) #define GET_TWI_INT_MISMATCH_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000008 ) >> 3) #define GET_TWI_INT_TRANS_FAIL_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000010 ) >> 4) #define GET_TWI_INT_HOLD_BUS_EN (((REG32(ADR_TWIM_INTERRUPT_EN)) & 0x00000020 ) >> 5) #define GET_TWI_INT_TXD_STALL (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000001 ) >> 0) #define GET_TWI_INT_RXD_STALL (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000002 ) >> 1) #define GET_TWI_INT_TRANS_FINISH (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000004 ) >> 2) #define GET_TWI_INT_MISMATCH (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000008 ) >> 3) #define GET_TWI_INT_TRANS_FAIL (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000010 ) >> 4) #define GET_TWI_INT_HOLD_BUS (((REG32(ADR_TWIM_INTERRUPT)) & 0x00000020 ) >> 5) #define GET_TWI_INT_TXD_STALL_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000001 ) >> 0) #define GET_TWI_INT_RXD_STALL_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000002 ) >> 1) #define GET_TWI_INT_TRANS_FINISH_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000004 ) >> 2) #define GET_TWI_INT_MISMATCH_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000008 ) >> 3) #define GET_TWI_INT_TRANS_FAIL_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000010 ) >> 4) #define GET_TWI_INT_HOLD_BUS_ST (((REG32(ADR_TWIM_INTERRUPT_STATUS)) & 0x00000020 ) >> 5) #define GET_TWI_STATUS_RECORD_0 (((REG32(ADR_TWIM_STATUS_RECORD_0)) & 0xffffffff ) >> 0) #define GET_TWI_STATUS_RECORD_1 (((REG32(ADR_TWIM_STATUS_RECORD_1)) & 0xffffffff ) >> 0) #define GET_TWI_RX (((REG32(ADR_TWIM_DEV_A)) & 0x00000001 ) >> 0) #define GET_TWI_DEV_A10B (((REG32(ADR_TWIM_DEV_A)) & 0x000007fe ) >> 1) #define GET_TWI_TXD_DATA (((REG32(ADR_TWIM_TXD_DATA)) & 0x000000ff ) >> 0) #define GET_TWI_RXD_DATA (((REG32(ADR_TWIM_RXD_DATA)) & 0x000000ff ) >> 0) #define GET_TWI_PSCL (((REG32(ADR_TWIM_PSCL)) & 0x000003ff ) >> 0) #define GET_TWI_STA_STO_PSCL (((REG32(ADR_TWIM_PSCL)) & 0x03ff0000 ) >> 16) #define GET_TWI_TRANS_PSDA (((REG32(ADR_TWIM_TRANS_PSDA)) & 0x000003ff ) >> 0) #define GET_TWI_DELAY_ACK (((REG32(ADR_TWIM_DELAY_ACK)) & 0x000003ff ) >> 0) #define GET_I2CM_INT_WDONE (((REG32(ADR_I2CM_EN)) & 0x00000001 ) >> 0) #define GET_I2CM_INT_RDONE (((REG32(ADR_I2CM_EN)) & 0x00000002 ) >> 1) #define GET_I2CM_IDLE (((REG32(ADR_I2CM_EN)) & 0x00000004 ) >> 2) #define GET_I2CM_INT_MISMATCH (((REG32(ADR_I2CM_EN)) & 0x00000008 ) >> 3) #define GET_I2CM_PSCL (((REG32(ADR_I2CM_EN)) & 0x00003ff0 ) >> 4) #define GET_I2CM_MANUAL_MODE (((REG32(ADR_I2CM_EN)) & 0x00010000 ) >> 16) #define GET_I2CM_INT_WDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00020000 ) >> 17) #define GET_I2CM_INT_RDATA_NEED (((REG32(ADR_I2CM_EN)) & 0x00040000 ) >> 18) #define GET_I2CM_DEV_A (((REG32(ADR_I2CM_DEV_A)) & 0x000003ff ) >> 0) #define GET_I2CM_DEV_A10B (((REG32(ADR_I2CM_DEV_A)) & 0x00004000 ) >> 14) #define GET_I2CM_RX (((REG32(ADR_I2CM_DEV_A)) & 0x00008000 ) >> 15) #define GET_I2CM_LEN (((REG32(ADR_I2CM_LEN)) & 0x0000ffff ) >> 0) #define GET_I2CM_T_LEFT (((REG32(ADR_I2CM_LEN)) & 0x00070000 ) >> 16) #define GET_I2CM_R_GET (((REG32(ADR_I2CM_LEN)) & 0x07000000 ) >> 24) #define GET_I2CM_WDAT (((REG32(ADR_I2CM_WDAT)) & 0xffffffff ) >> 0) #define GET_I2CM_RDAT (((REG32(ADR_I2CM_RDAT)) & 0xffffffff ) >> 0) #define GET_I2CM_SR_LEN (((REG32(ADR_I2CM_EN_2)) & 0x0000ffff ) >> 0) #define GET_I2CM_SR_RX (((REG32(ADR_I2CM_EN_2)) & 0x00010000 ) >> 16) #define GET_I2CM_REPEAT_START (((REG32(ADR_I2CM_EN_2)) & 0x00020000 ) >> 17) #define GET_I2CM_STA_STO_PSCL (((REG32(ADR_I2CM_START_STOP_PERIOD)) & 0x000003ff ) >> 0) #define GET_UART_DATA (((REG32(ADR_UART_DATA)) & 0x000000ff ) >> 0) #define GET_DATA_RDY_IE (((REG32(ADR_UART_IER)) & 0x00000001 ) >> 0) #define GET_THR_EMPTY_IE (((REG32(ADR_UART_IER)) & 0x00000002 ) >> 1) #define GET_RX_LINESTS_IE (((REG32(ADR_UART_IER)) & 0x00000004 ) >> 2) #define GET_MDM_STS_IE (((REG32(ADR_UART_IER)) & 0x00000008 ) >> 3) #define GET_TX_THRH_IE (((REG32(ADR_UART_IER)) & 0x00000010 ) >> 4) #define GET_TX_THRL_IE (((REG32(ADR_UART_IER)) & 0x00000020 ) >> 5) #define GET_FIFO_EN (((REG32(ADR_UART_FCR)) & 0x00000001 ) >> 0) #define GET_RXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000002 ) >> 1) #define GET_TXFIFO_RST (((REG32(ADR_UART_FCR)) & 0x00000004 ) >> 2) #define GET_DMA_MODE (((REG32(ADR_UART_FCR)) & 0x00000008 ) >> 3) #define GET_EN_AUTO_RTS (((REG32(ADR_UART_FCR)) & 0x00000010 ) >> 4) #define GET_EN_AUTO_CTS (((REG32(ADR_UART_FCR)) & 0x00000020 ) >> 5) #define GET_RXFIFO_TRGLVL (((REG32(ADR_UART_FCR)) & 0x000000c0 ) >> 6) #define GET_WORD_LEN (((REG32(ADR_UART_LCR)) & 0x00000003 ) >> 0) #define GET_STOP_BIT (((REG32(ADR_UART_LCR)) & 0x00000004 ) >> 2) #define GET_PARITY_EN (((REG32(ADR_UART_LCR)) & 0x00000008 ) >> 3) #define GET_EVEN_PARITY (((REG32(ADR_UART_LCR)) & 0x00000010 ) >> 4) #define GET_FORCE_PARITY (((REG32(ADR_UART_LCR)) & 0x00000020 ) >> 5) #define GET_SET_BREAK (((REG32(ADR_UART_LCR)) & 0x00000040 ) >> 6) #define GET_DLAB (((REG32(ADR_UART_LCR)) & 0x00000080 ) >> 7) #define GET_DTR (((REG32(ADR_UART_MCR)) & 0x00000001 ) >> 0) #define GET_RTS (((REG32(ADR_UART_MCR)) & 0x00000002 ) >> 1) #define GET_OUT_1 (((REG32(ADR_UART_MCR)) & 0x00000004 ) >> 2) #define GET_OUT_2 (((REG32(ADR_UART_MCR)) & 0x00000008 ) >> 3) #define GET_LOOP_BACK (((REG32(ADR_UART_MCR)) & 0x00000010 ) >> 4) #define GET_DE_RTS (((REG32(ADR_UART_MCR)) & 0x00000020 ) >> 5) #define GET_DATA_RDY (((REG32(ADR_UART_LSR)) & 0x00000001 ) >> 0) #define GET_OVERRUN_ERR (((REG32(ADR_UART_LSR)) & 0x00000002 ) >> 1) #define GET_PARITY_ERR (((REG32(ADR_UART_LSR)) & 0x00000004 ) >> 2) #define GET_FRAMING_ERR (((REG32(ADR_UART_LSR)) & 0x00000008 ) >> 3) #define GET_BREAK_INT (((REG32(ADR_UART_LSR)) & 0x00000010 ) >> 4) #define GET_THR_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000020 ) >> 5) #define GET_TX_EMPTY (((REG32(ADR_UART_LSR)) & 0x00000040 ) >> 6) #define GET_FIFODATA_ERR (((REG32(ADR_UART_LSR)) & 0x00000080 ) >> 7) #define GET_DELTA_CTS (((REG32(ADR_UART_MSR)) & 0x00000001 ) >> 0) #define GET_DELTA_DSR (((REG32(ADR_UART_MSR)) & 0x00000002 ) >> 1) #define GET_TRAILEDGE_RI (((REG32(ADR_UART_MSR)) & 0x00000004 ) >> 2) #define GET_DELTA_CD (((REG32(ADR_UART_MSR)) & 0x00000008 ) >> 3) #define GET_CTS (((REG32(ADR_UART_MSR)) & 0x00000010 ) >> 4) #define GET_DSR (((REG32(ADR_UART_MSR)) & 0x00000020 ) >> 5) #define GET_RI (((REG32(ADR_UART_MSR)) & 0x00000040 ) >> 6) #define GET_CD (((REG32(ADR_UART_MSR)) & 0x00000080 ) >> 7) #define GET_BRDC_DIV (((REG32(ADR_UART_SPR)) & 0x0000ffff ) >> 0) #define GET_RTHR_L (((REG32(ADR_UART_RTHR)) & 0x0000000f ) >> 0) #define GET_RTHR_H (((REG32(ADR_UART_RTHR)) & 0x000000f0 ) >> 4) #define GET_INT_IDCODE (((REG32(ADR_UART_ISR)) & 0x0000000f ) >> 0) #define GET_RX_IDLE (((REG32(ADR_UART_ISR)) & 0x00000010 ) >> 4) #define GET_TX_IDLE (((REG32(ADR_UART_ISR)) & 0x00000020 ) >> 5) #define GET_FIFOS_ENABLED (((REG32(ADR_UART_ISR)) & 0x000000c0 ) >> 6) #define GET_TTHR_L (((REG32(ADR_UART_TTHR)) & 0x0000000f ) >> 0) #define GET_TTHR_H (((REG32(ADR_UART_TTHR)) & 0x000000f0 ) >> 4) #define GET_RX_RECIEVED (((REG32(ADR_UART_INT_MAP)) & 0x00000001 ) >> 0) #define GET_RX_FIFO_TO (((REG32(ADR_UART_INT_MAP)) & 0x00000002 ) >> 1) #define GET_TX_L (((REG32(ADR_UART_INT_MAP)) & 0x00000004 ) >> 2) #define GET_TX_H (((REG32(ADR_UART_INT_MAP)) & 0x00000008 ) >> 3) #define GET_TX_EMPTY2 (((REG32(ADR_UART_INT_MAP)) & 0x00000010 ) >> 4) #define GET_OVERRUN (((REG32(ADR_UART_INT_MAP)) & 0x00000020 ) >> 5) #define GET_FRAMING (((REG32(ADR_UART_INT_MAP)) & 0x00000040 ) >> 6) #define GET_BREAK (((REG32(ADR_UART_INT_MAP)) & 0x00000080 ) >> 7) #define GET_PARITY (((REG32(ADR_UART_INT_MAP)) & 0x00000100 ) >> 8) #define GET_MODEN_INT (((REG32(ADR_UART_INT_MAP)) & 0x00000200 ) >> 9) #define GET_ROP_A (((REG32(ADR_UART_POINTER)) & 0x0000000f ) >> 0) #define GET_RIP_A (((REG32(ADR_UART_POINTER)) & 0x000000f0 ) >> 4) #define GET_TOP_A (((REG32(ADR_UART_POINTER)) & 0x00000f00 ) >> 8) #define GET_TIP_A (((REG32(ADR_UART_POINTER)) & 0x0000f000 ) >> 12) #define GET_HSUART_RXD (((REG32(ADR_HSUART_TRX_CHAR)) & 0x000000ff ) >> 0) #define GET_HSUART_ENABRXBUFF (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000001 ) >> 0) #define GET_HSUART_ENABTXBUFF (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000002 ) >> 1) #define GET_HSUART_ENABLNSTAT (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000004 ) >> 2) #define GET_HSUART_ENABMDSTAT (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000008 ) >> 3) #define GET_HSUART_ENABCTXTHR (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000010 ) >> 4) #define GET_HSUART_ENABDMARXEND (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000040 ) >> 6) #define GET_HSUART_ENABDMATXEND (((REG32(ADR_HSUART_INTRRUPT_ENABLE)) & 0x00000080 ) >> 7) #define GET_HSUART_FIFOE (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000001 ) >> 0) #define GET_HSUART_RX_FIFO_RST (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000002 ) >> 1) #define GET_HSUART_TX_FIFO_RST (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000004 ) >> 2) #define GET_HSUART_DMA (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x00000008 ) >> 3) #define GET_HSUART_RX_TRIG_LV (((REG32(ADR_HSUART_FIFO_CTRL)) & 0x000000c0 ) >> 6) #define GET_HSUART_WLS (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000003 ) >> 0) #define GET_HSUART_STB (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000004 ) >> 2) #define GET_HSUART_PEN (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000008 ) >> 3) #define GET_HSUART_SP_EPS (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000030 ) >> 4) #define GET_HSUART_SB (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000040 ) >> 6) #define GET_HSUART_DLAB (((REG32(ADR_HSUART_LINE_CTRL)) & 0x00000080 ) >> 7) #define GET_HSUART_DTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000001 ) >> 0) #define GET_HSUART_RTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000002 ) >> 1) #define GET_HSUART_OUT1 (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000004 ) >> 2) #define GET_HSUART_OUT2 (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000008 ) >> 3) #define GET_HSUART_LOOP1 (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000010 ) >> 4) #define GET_HSUART_ARTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000040 ) >> 6) #define GET_HSUART_ACTS (((REG32(ADR_HSUART_MODEM_CTRL)) & 0x00000080 ) >> 7) #define GET_HSUART_DR (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000001 ) >> 0) #define GET_HSUART_OE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000002 ) >> 1) #define GET_HSUART_PE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000004 ) >> 2) #define GET_HSUART_FE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000008 ) >> 3) #define GET_HSUART_BI (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000010 ) >> 4) #define GET_HSUART_THRE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000020 ) >> 5) #define GET_HSUART_TSRE (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000040 ) >> 6) #define GET_HSUART_ERF (((REG32(ADR_HSUART_LINE_STATUS)) & 0x00000080 ) >> 7) #define GET_HSUART_DCTS (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000001 ) >> 0) #define GET_HSUART_DDSR (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000002 ) >> 1) #define GET_HSUART_TERI (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000004 ) >> 2) #define GET_HSUART_DDCD (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000008 ) >> 3) #define GET_HSUART_CTS (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000010 ) >> 4) #define GET_HSUART_DSR (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000020 ) >> 5) #define GET_HSUART_RI (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000040 ) >> 6) #define GET_HSUART_DCR (((REG32(ADR_HSUART_MODEM_STATUS)) & 0x00000080 ) >> 7) #define GET_HSUART_SCR (((REG32(ADR_HSUART_SCRATCH_BOARD)) & 0x000000ff ) >> 0) #define GET_HSUART_RTS_AUTO_TH_L (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x0000001f ) >> 0) #define GET_HSUART_RTS_AUTO_TH_H (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x00001f00 ) >> 8) #define GET_HSUART_TX_THR_L (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x001f0000 ) >> 16) #define GET_HSUART_TX_THR_H (((REG32(ADR_HSUART_FIFO_THRESHOLD)) & 0x1f000000 ) >> 24) #define GET_HSUART_IIR (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x0000000f ) >> 0) #define GET_HSUART_TXDMA_DONE (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x00000020 ) >> 5) #define GET_HSUART_IFOFOE0 (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x00000040 ) >> 6) #define GET_HSUART_IFIFOE1 (((REG32(ADR_HSUART_INTERRUPT_STATUS)) & 0x00000080 ) >> 7) #define GET_HSUART_DIV (((REG32(ADR_HSUART_DIV_FRAC)) & 0x0000ffff ) >> 0) #define GET_HSUART_FRAC (((REG32(ADR_HSUART_DIV_FRAC)) & 0x00ff0000 ) >> 16) #define GET_HSUART_INT (((REG32(ADR_HSUART_EXPANSION_INTERRUPT_STATUS)) & 0x0000ffff ) >> 0) #define GET_HSUART_DMA_RX_STR_ADDR (((REG32(ADR_HSUART_DMA_RX_STR_ADDR)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_RX_END_ADDR (((REG32(ADR_HSUART_DMA_RX_END_ADDR)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_RX_WPT (((REG32(ADR_HSUART_DMA_RX_WPT)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_RX_RPT (((REG32(ADR_HSUART_DMA_RX_RPT)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_TX_STR_ADDR (((REG32(ADR_HSUART_DMA_TX_STR_ADDR)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_TX_END_ADDR (((REG32(ADR_HSUART_DMA_TX_END_ADDR)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_TX_WPT (((REG32(ADR_HSUART_DMA_TX_WPT)) & 0xffffffff ) >> 0) #define GET_HSUART_DMA_TX_RPT (((REG32(ADR_HSUART_DMA_TX_RPT)) & 0xffffffff ) >> 0) #define GET_MANUAL_T_ADDR (((REG32(ADR_MANUAL_MODE_TX_ADDR)) & 0xffffffff ) >> 0) #define GET_MANUAL_R_ADDR (((REG32(ADR_MANUAL_MODE_RX_ADDR)) & 0xffffffff ) >> 0) #define GET_FLASH_FRONT_DLY (((REG32(ADR_SPI_PARAM)) & 0x0000000f ) >> 0) #define GET_FLASH_BACK_DLY (((REG32(ADR_SPI_PARAM)) & 0x000000f0 ) >> 4) #define GET_CSN_DLY (((REG32(ADR_SPI_PARAM)) & 0x00000f00 ) >> 8) #define GET_INDICATOR (((REG32(ADR_SPI_PARAM)) & 0x000ff000 ) >> 12) #define GET_DUMY_DLY (((REG32(ADR_SPI_PARAM)) & 0x00f00000 ) >> 20) #define GET_MEM_SEL (((REG32(ADR_SPI_PARAM)) & 0x01000000 ) >> 24) #define GET_SPI_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00000001 ) >> 0) #define GET_SPI_FLASH_MODE (((REG32(ADR_SPI_PARAM2)) & 0x00000006 ) >> 1) #define GET_MANUAL_MODE_BUSY (((REG32(ADR_SPI_PARAM2)) & 0x00000008 ) >> 3) #define GET_PREFETCH_EN (((REG32(ADR_SPI_PARAM2)) & 0x00000010 ) >> 4) #define GET_WRAP_EN (((REG32(ADR_SPI_PARAM2)) & 0x00000020 ) >> 5) #define GET_CONTINUE_R_EN (((REG32(ADR_SPI_PARAM2)) & 0x00000040 ) >> 6) #define GET_MANUAL_T_LEN (((REG32(ADR_SPI_TX_LEN)) & 0x0000ffff ) >> 0) #define GET_MANUAL_R_LEN (((REG32(ADR_SPI_RX_LEN)) & 0x0000ffff ) >> 0) #define GET_BIT1_WR_CMD (((REG32(ADR_CMD_SET)) & 0x000000ff ) >> 0) #define GET_BIT1_RD_CMD (((REG32(ADR_CMD_SET)) & 0x0000ff00 ) >> 8) #define GET_BIT2_RD_CMD (((REG32(ADR_CMD_SET)) & 0x00ff0000 ) >> 16) #define GET_BIT4_RD_CMD (((REG32(ADR_CMD_SET)) & 0xff000000 ) >> 24) #define GET_BIT4_WR_CMD (((REG32(ADR_CMD_SET_1)) & 0x000000ff ) >> 0) #define GET_FLS_CLK_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00000007 ) >> 0) #define GET_FLS_CLK_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00000070 ) >> 4) #define GET_FLS_MOSI_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00000700 ) >> 8) #define GET_FLS_MOSI_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00007000 ) >> 12) #define GET_FLS_MISO_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00070000 ) >> 16) #define GET_FLS_MISO_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x00700000 ) >> 20) #define GET_FLS_WP_IN_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x07000000 ) >> 24) #define GET_FLS_WP_OUT_DLY_SEL (((REG32(ADR_FLASH_IO0_DLY)) & 0x70000000 ) >> 28) #define GET_FLS_NC_IN_DLY_SEL (((REG32(ADR_FLASH_IO1_DLY)) & 0x00000007 ) >> 0) #define GET_FLS_NC_OUT_DLY_SEL (((REG32(ADR_FLASH_IO1_DLY)) & 0x00000070 ) >> 4) #define GET_SPI_F_MISO_CLK_SEL (((REG32(ADR_FLASH_IO1_DLY)) & 0x00000100 ) >> 8) #define GET_INS_START_ADDR (((REG32(ADR_INS_SPACE_START_ADDR)) & 0x00ffffff ) >> 0) #define GET_INS_END_ADDR (((REG32(ADR_INS_SPACE_END_ADDR)) & 0x00ffffff ) >> 0) #define GET_INS_BUF_CLR (((REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) & 0x00000001 ) >> 0) #define GET_RW_BUF_CLR (((REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) & 0x00000002 ) >> 1) #define GET_ERR_FLAG_CLR (((REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) & 0x00000004 ) >> 2) #define GET_DMA_ADR_SRC (((REG32(ADR_DMA_ADR_SRC)) & 0xffffffff ) >> 0) #define GET_DMA_ADR_DST (((REG32(ADR_DMA_ADR_DST)) & 0xffffffff ) >> 0) #define GET_DMA_SRC_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000007 ) >> 0) #define GET_DMA_SRC_INC (((REG32(ADR_DMA_CTRL)) & 0x00000008 ) >> 3) #define GET_DMA_DST_SIZE (((REG32(ADR_DMA_CTRL)) & 0x00000070 ) >> 4) #define GET_DMA_DST_INC (((REG32(ADR_DMA_CTRL)) & 0x00000080 ) >> 7) #define GET_DMA_FAST_FILL (((REG32(ADR_DMA_CTRL)) & 0x00000100 ) >> 8) #define GET_DMA_SDIO_KICK (((REG32(ADR_DMA_CTRL)) & 0x00001000 ) >> 12) #define GET_DMA_BADR_EN (((REG32(ADR_DMA_CTRL)) & 0x00002000 ) >> 13) #define GET_DMA_LEN (((REG32(ADR_DMA_CTRL)) & 0xffff0000 ) >> 16) #define GET_DMA_INT_MASK (((REG32(ADR_DMA_INT)) & 0x00000001 ) >> 0) #define GET_DMA_STS (((REG32(ADR_DMA_INT)) & 0x00000100 ) >> 8) #define GET_DMA_FINISH (((REG32(ADR_DMA_INT)) & 0x80000000 ) >> 31) #define GET_DMA_CONST (((REG32(ADR_DMA_FILL_CONST)) & 0xffffffff ) >> 0) #define GET_D2_DMA_ADR_SRC (((REG32(ADR_D2_DMA_ADR_SRC)) & 0xffffffff ) >> 0) #define GET_D2_DMA_ADR_DST (((REG32(ADR_D2_DMA_ADR_DST)) & 0xffffffff ) >> 0) #define GET_D2_DMA_SRC_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000007 ) >> 0) #define GET_D2_DMA_SRC_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000008 ) >> 3) #define GET_D2_DMA_DST_SIZE (((REG32(ADR_D2_DMA_CTRL)) & 0x00000070 ) >> 4) #define GET_D2_DMA_DST_INC (((REG32(ADR_D2_DMA_CTRL)) & 0x00000080 ) >> 7) #define GET_D2_DMA_FAST_FILL (((REG32(ADR_D2_DMA_CTRL)) & 0x00000100 ) >> 8) #define GET_D2_DMA_SDIO_KICK (((REG32(ADR_D2_DMA_CTRL)) & 0x00001000 ) >> 12) #define GET_D2_DMA_BADR_EN (((REG32(ADR_D2_DMA_CTRL)) & 0x00002000 ) >> 13) #define GET_D2_DMA_LEN (((REG32(ADR_D2_DMA_CTRL)) & 0xffff0000 ) >> 16) #define GET_D2_DMA_INT_MASK (((REG32(ADR_D2_DMA_INT)) & 0x00000001 ) >> 0) #define GET_D2_DMA_STS (((REG32(ADR_D2_DMA_INT)) & 0x00000100 ) >> 8) #define GET_D2_DMA_FINISH (((REG32(ADR_D2_DMA_INT)) & 0x80000000 ) >> 31) #define GET_D2_DMA_CONST (((REG32(ADR_D2_DMA_FILL_CONST)) & 0xffffffff ) >> 0) #define GET_MASK_TYPHOST_INT_MAP_02 (((REG32(ADR_MASK_TYPHOST_INT_MAP_02)) & 0xffffffff ) >> 0) #define GET_RAW_TYPHOST_INT_MAP_02 (((REG32(ADR_RAW_TYPHOST_INT_MAP_02)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPHOST_INT_MAP_02 (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP_02)) & 0xffffffff ) >> 0) #define GET_MASK_TYPHOST_INT_MAP_15 (((REG32(ADR_MASK_TYPHOST_INT_MAP_15)) & 0xffffffff ) >> 0) #define GET_RAW_TYPHOST_INT_MAP_15 (((REG32(ADR_RAW_TYPHOST_INT_MAP_15)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPHOST_INT_MAP_15 (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP_15)) & 0xffffffff ) >> 0) #define GET_MASK_TYPHOST_INT_MAP_31 (((REG32(ADR_MASK_TYPHOST_INT_MAP_31)) & 0xffffffff ) >> 0) #define GET_RAW_TYPHOST_INT_MAP_31 (((REG32(ADR_RAW_TYPHOST_INT_MAP_31)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPHOST_INT_MAP_31 (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP_31)) & 0xffffffff ) >> 0) #define GET_MASK_TYPHOST_INT_MAP (((REG32(ADR_MASK_TYPHOST_INT_MAP)) & 0xffffffff ) >> 0) #define GET_RAW_TYPHOST_INT_MAP (((REG32(ADR_RAW_TYPHOST_INT_MAP)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPHOST_INT_MAP (((REG32(ADR_POSTMASK_TYPHOST_INT_MAP)) & 0xffffffff ) >> 0) #define GET_SUMMARY_TYPHOST_INT_MAP (((REG32(ADR_SUMMARY_TYPHOST_INT_MAP)) & 0x00000001 ) >> 0) #define GET_MASK_TYPMCU_INT_MAP_02 (((REG32(ADR_MASK_TYPMCU_INT_MAP_02)) & 0xffffffff ) >> 0) #define GET_RAW_TYPMCU_INT_MAP_02 (((REG32(ADR_RAW_TYPMCU_INT_MAP_02)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPMCU_INT_MAP_02 (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP_02)) & 0xffffffff ) >> 0) #define GET_MASK_TYPMCU_INT_MAP_15 (((REG32(ADR_MASK_TYPMCU_INT_MAP_15)) & 0xffffffff ) >> 0) #define GET_RAW_TYPMCU_INT_MAP_15 (((REG32(ADR_RAW_TYPMCU_INT_MAP_15)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPMCU_INT_MAP_15 (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP_15)) & 0xffffffff ) >> 0) #define GET_MASK_TYPMCU_INT_MAP_31 (((REG32(ADR_MASK_TYPMCU_INT_MAP_31)) & 0xffffffff ) >> 0) #define GET_RAW_TYPMCU_INT_MAP_31 (((REG32(ADR_RAW_TYPMCU_INT_MAP_31)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPMCU_INT_MAP_31 (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP_31)) & 0xffffffff ) >> 0) #define GET_MASK_TYPMCU_INT_MAP (((REG32(ADR_MASK_TYPMCU_INT_MAP)) & 0xffffffff ) >> 0) #define GET_RAW_TYPMCU_INT_MAP (((REG32(ADR_RAW_TYPMCU_INT_MAP)) & 0xffffffff ) >> 0) #define GET_POSTMASK_TYPMCU_INT_MAP (((REG32(ADR_POSTMASK_TYPMCU_INT_MAP)) & 0xffffffff ) >> 0) #define GET_SUMMARY_TYPMCU_INT_MAP (((REG32(ADR_SUMMARY_TYPMCU_INT_MAP)) & 0x00000001 ) >> 0) #define GET_INT_GPI_SUB_00 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x0000000f ) >> 0) #define GET_INT_GPI_SUB_01 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x000000f0 ) >> 4) #define GET_INT_GPI_SUB_02 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x00000f00 ) >> 8) #define GET_INT_GPI_SUB_03 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x0000f000 ) >> 12) #define GET_INT_GPI_SUB_04 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x000f0000 ) >> 16) #define GET_INT_GPI_SUB_05 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x00f00000 ) >> 20) #define GET_INT_GPI_SUB_06 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0x0f000000 ) >> 24) #define GET_INT_GPI_SUB_07 (((REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) & 0xf0000000 ) >> 28) #define GET_INT_GPI_SUB_08 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x0000000f ) >> 0) #define GET_INT_GPI_SUB_09 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x000000f0 ) >> 4) #define GET_INT_GPI_SUB_10 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x00000f00 ) >> 8) #define GET_INT_GPI_SUB_11 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x0000f000 ) >> 12) #define GET_INT_GPI_SUB_12 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x000f0000 ) >> 16) #define GET_INT_GPI_SUB_13 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x00f00000 ) >> 20) #define GET_INT_GPI_SUB_14 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0x0f000000 ) >> 24) #define GET_INT_GPI_SUB_15 (((REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) & 0xf0000000 ) >> 28) #define GET_INT_GPI_SUB_16 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x0000000f ) >> 0) #define GET_INT_GPI_SUB_17 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x000000f0 ) >> 4) #define GET_INT_GPI_SUB_18 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x00000f00 ) >> 8) #define GET_INT_GPI_SUB_19 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x0000f000 ) >> 12) #define GET_INT_GPI_SUB_20 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x000f0000 ) >> 16) #define GET_INT_GPI_SUB_21 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x00f00000 ) >> 20) #define GET_INT_GPI_SUB_22 (((REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) & 0x0f000000 ) >> 24) #define GET_INT_GPI_MODE_00 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00000007 ) >> 0) #define GET_INT_GPI_MODE_01 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00000070 ) >> 4) #define GET_INT_GPI_MODE_02 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00000700 ) >> 8) #define GET_INT_GPI_MODE_03 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00007000 ) >> 12) #define GET_INT_GPI_MODE_04 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00070000 ) >> 16) #define GET_INT_GPI_MODE_05 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x00700000 ) >> 20) #define GET_INT_GPI_MODE_06 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x07000000 ) >> 24) #define GET_INT_GPI_MODE_07 (((REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) & 0x70000000 ) >> 28) #define GET_INT_GPI_MODE_08 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00000007 ) >> 0) #define GET_INT_GPI_MODE_09 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00000070 ) >> 4) #define GET_INT_GPI_MODE_10 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00000700 ) >> 8) #define GET_INT_GPI_MODE_11 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00007000 ) >> 12) #define GET_INT_GPI_MODE_12 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00070000 ) >> 16) #define GET_INT_GPI_MODE_13 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x00700000 ) >> 20) #define GET_INT_GPI_MODE_14 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x07000000 ) >> 24) #define GET_INT_GPI_MODE_15 (((REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) & 0x70000000 ) >> 28) #define GET_INT_GPI_MODE_16 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00000007 ) >> 0) #define GET_INT_GPI_MODE_17 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00000070 ) >> 4) #define GET_INT_GPI_MODE_18 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00000700 ) >> 8) #define GET_INT_GPI_MODE_19 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00007000 ) >> 12) #define GET_INT_GPI_MODE_20 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00070000 ) >> 16) #define GET_INT_GPI_MODE_21 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x00700000 ) >> 20) #define GET_INT_GPI_MODE_22 (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x07000000 ) >> 24) #define GET_GPO_INT_POL (((REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) & 0x80000000 ) >> 31) #define GET_INT_IPC_RAW (((REG32(ADR_IPC_INTERRUPT)) & 0xffffffff ) >> 0) #define GET_INT_WIFI_PHY (((REG32(ADR_CLR_INT_STS2)) & 0x00800000 ) >> 23) #define GET_INT_UART_DBG_RX_TOUT (((REG32(ADR_CLR_INT_STS2)) & 0x04000000 ) >> 26) #define GET_INT_UART_DATA_RX_TOUT (((REG32(ADR_CLR_INT_STS2)) & 0x40000000 ) >> 30) #define GET_INT_ALC_TIMEOUT (((REG32(ADR_CLR_INT_STS1)) & 0x00000100 ) >> 8) #define GET_INT_REQ_LOCK (((REG32(ADR_CLR_INT_STS1)) & 0x00000200 ) >> 9) #define GET_INT_TX_LIMIT (((REG32(ADR_CLR_INT_STS1)) & 0x00000400 ) >> 10) #define GET_INT_ID_THOLD_RX (((REG32(ADR_CLR_INT_STS1)) & 0x00000800 ) >> 11) #define GET_INT_ID_THOLD_TX (((REG32(ADR_CLR_INT_STS1)) & 0x00001000 ) >> 12) #define GET_INT_ID_DOUBLE_RLS (((REG32(ADR_CLR_INT_STS1)) & 0x00002000 ) >> 13) #define GET_INT_RX_ID_LEN_THOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00004000 ) >> 14) #define GET_INT_TX_ID_LEN_THOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00008000 ) >> 15) #define GET_INT_ALL_ID_LEN_THOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00010000 ) >> 16) #define GET_INT_TRASH_CAN (((REG32(ADR_CLR_INT_STS1)) & 0x00020000 ) >> 17) #define GET_INT_MB_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00040000 ) >> 18) #define GET_INT_EDCA0_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00100000 ) >> 20) #define GET_INT_EDCA1_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00200000 ) >> 21) #define GET_INT_EDCA2_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00400000 ) >> 22) #define GET_INT_EDCA3_LOWTHOLD (((REG32(ADR_CLR_INT_STS1)) & 0x00800000 ) >> 23) #define GET_INT_SDIO_WAKE (((REG32(ADR_CLR_INT_STS0)) & 0x00000004 ) >> 2) #define GET_INT_SPI_M_DONE (((REG32(ADR_CLR_INT_STS0)) & 0x00000008 ) >> 3) #define GET_INT_FLASH_DMA_DONE (((REG32(ADR_CLR_INT_STS0)) & 0x00000040 ) >> 6) #define GET_INT_FBUSDMAC_INT_COMBINED (((REG32(ADR_CLR_INT_STS0)) & 0x00000200 ) >> 9) #define GET_INT_DMAC_INT_COMBINED (((REG32(ADR_CLR_INT_STS0)) & 0x00000400 ) >> 10) #define GET_INT_I2S (((REG32(ADR_CLR_INT_STS0)) & 0x00010000 ) >> 16) #define GET_INT_CPU_ALT (((REG32(ADR_CLR_INT_STS0)) & 0x00040000 ) >> 18) #define GET_INT_CPU (((REG32(ADR_CLR_INT_STS0)) & 0x00080000 ) >> 19) #define GET_INT_US_TIMER_0 (((REG32(ADR_CLR_INT_STS0)) & 0x00100000 ) >> 20) #define GET_INT_US_TIMER_1 (((REG32(ADR_CLR_INT_STS0)) & 0x00200000 ) >> 21) #define GET_INT_US_TIMER_2 (((REG32(ADR_CLR_INT_STS0)) & 0x00400000 ) >> 22) #define GET_INT_US_TIMER_3 (((REG32(ADR_CLR_INT_STS0)) & 0x00800000 ) >> 23) #define GET_INT_MS_TIMER_0 (((REG32(ADR_CLR_INT_STS0)) & 0x01000000 ) >> 24) #define GET_INT_MS_TIMER_1 (((REG32(ADR_CLR_INT_STS0)) & 0x02000000 ) >> 25) #define GET_INT_MS_TIMER_2 (((REG32(ADR_CLR_INT_STS0)) & 0x04000000 ) >> 26) #define GET_INT_MS_TIMER_3 (((REG32(ADR_CLR_INT_STS0)) & 0x08000000 ) >> 27) #define GET_INT_I2CMST (((REG32(ADR_CLR_INT_STS0)) & 0x10000000 ) >> 28) #define GET_INT_HCI (((REG32(ADR_CLR_INT_STS0)) & 0x20000000 ) >> 29) #define GET_INT_CO_DMA (((REG32(ADR_CLR_INT_STS0)) & 0x40000000 ) >> 30) #define GET_PATCH02_EN (((REG32(ADR_ROM_PATCH02_0)) & 0x00000001 ) >> 0) #define GET_PATCH02_ADDR (((REG32(ADR_ROM_PATCH02_0)) & 0x0001fffc ) >> 2) #define GET_PATCH02_DATA (((REG32(ADR_ROM_PATCH02_1)) & 0xffffffff ) >> 0) #define GET_PATCH03_EN (((REG32(ADR_ROM_PATCH03_0)) & 0x00000001 ) >> 0) #define GET_PATCH03_ADDR (((REG32(ADR_ROM_PATCH03_0)) & 0x0001fffc ) >> 2) #define GET_PATCH03_DATA (((REG32(ADR_ROM_PATCH03_1)) & 0xffffffff ) >> 0) #define GET_PATCH04_EN (((REG32(ADR_ROM_PATCH04_0)) & 0x00000001 ) >> 0) #define GET_PATCH04_ADDR (((REG32(ADR_ROM_PATCH04_0)) & 0x0001fffc ) >> 2) #define GET_PATCH04_DATA (((REG32(ADR_ROM_PATCH04_1)) & 0xffffffff ) >> 0) #define GET_PATCH05_EN (((REG32(ADR_ROM_PATCH05_0)) & 0x00000001 ) >> 0) #define GET_PATCH05_ADDR (((REG32(ADR_ROM_PATCH05_0)) & 0x0001fffc ) >> 2) #define GET_PATCH05_DATA (((REG32(ADR_ROM_PATCH05_1)) & 0xffffffff ) >> 0) #define GET_PATCH06_EN (((REG32(ADR_ROM_PATCH06_0)) & 0x00000001 ) >> 0) #define GET_PATCH06_ADDR (((REG32(ADR_ROM_PATCH06_0)) & 0x0001fffc ) >> 2) #define GET_PATCH06_DATA (((REG32(ADR_ROM_PATCH06_1)) & 0xffffffff ) >> 0) #define GET_PATCH07_EN (((REG32(ADR_ROM_PATCH07_0)) & 0x00000001 ) >> 0) #define GET_PATCH07_ADDR (((REG32(ADR_ROM_PATCH07_0)) & 0x0001fffc ) >> 2) #define GET_PATCH07_DATA (((REG32(ADR_ROM_PATCH07_1)) & 0xffffffff ) >> 0) #define GET_PATCH08_EN (((REG32(ADR_ROM_PATCH08_0)) & 0x00000001 ) >> 0) #define GET_PATCH08_ADDR (((REG32(ADR_ROM_PATCH08_0)) & 0x0001fffc ) >> 2) #define GET_PATCH08_DATA (((REG32(ADR_ROM_PATCH08_1)) & 0xffffffff ) >> 0) #define GET_PATCH09_EN (((REG32(ADR_ROM_PATCH09_0)) & 0x00000001 ) >> 0) #define GET_PATCH09_ADDR (((REG32(ADR_ROM_PATCH09_0)) & 0x0001fffc ) >> 2) #define GET_PATCH09_DATA (((REG32(ADR_ROM_PATCH09_1)) & 0xffffffff ) >> 0) #define GET_PATCH10_EN (((REG32(ADR_ROM_PATCH10_0)) & 0x00000001 ) >> 0) #define GET_PATCH10_ADDR (((REG32(ADR_ROM_PATCH10_0)) & 0x0001fffc ) >> 2) #define GET_PATCH10_DATA (((REG32(ADR_ROM_PATCH10_1)) & 0xffffffff ) >> 0) #define GET_PATCH11_EN (((REG32(ADR_ROM_PATCH11_0)) & 0x00000001 ) >> 0) #define GET_PATCH11_ADDR (((REG32(ADR_ROM_PATCH11_0)) & 0x0001fffc ) >> 2) #define GET_PATCH11_DATA (((REG32(ADR_ROM_PATCH11_1)) & 0xffffffff ) >> 0) #define GET_PATCH12_EN (((REG32(ADR_ROM_PATCH12_0)) & 0x00000001 ) >> 0) #define GET_PATCH12_ADDR (((REG32(ADR_ROM_PATCH12_0)) & 0x0001fffc ) >> 2) #define GET_PATCH12_DATA (((REG32(ADR_ROM_PATCH12_1)) & 0xffffffff ) >> 0) #define GET_PATCH13_EN (((REG32(ADR_ROM_PATCH13_0)) & 0x00000001 ) >> 0) #define GET_PATCH13_ADDR (((REG32(ADR_ROM_PATCH13_0)) & 0x0001fffc ) >> 2) #define GET_PATCH13_DATA (((REG32(ADR_ROM_PATCH13_1)) & 0xffffffff ) >> 0) #define GET_PATCH14_EN (((REG32(ADR_ROM_PATCH14_0)) & 0x00000001 ) >> 0) #define GET_PATCH14_ADDR (((REG32(ADR_ROM_PATCH14_0)) & 0x0001fffc ) >> 2) #define GET_PATCH14_DATA (((REG32(ADR_ROM_PATCH14_1)) & 0xffffffff ) >> 0) #define GET_PATCH15_EN (((REG32(ADR_ROM_PATCH15_0)) & 0x00000001 ) >> 0) #define GET_PATCH15_ADDR (((REG32(ADR_ROM_PATCH15_0)) & 0x0001fffc ) >> 2) #define GET_PATCH15_DATA (((REG32(ADR_ROM_PATCH15_1)) & 0xffffffff ) >> 0) #define GET_INT_BROWNOUT_LOWBATTERY (((REG32(ADR_BROWNOUT_INT)) & 0x00000001 ) >> 0) #define GET_LOWBATTERY_SAMPLE_MIN_COUNT (((REG32(ADR_BROWNOUT_SETUP)) & 0x0000000f ) >> 0) #define GET_TX_ON_DEMAND_ENA (((REG32(ADR_CONTROL)) & 0x00000002 ) >> 1) #define GET_RX_2_HOST (((REG32(ADR_CONTROL)) & 0x00000004 ) >> 2) #define GET_AUTO_SEQNO (((REG32(ADR_CONTROL)) & 0x00000008 ) >> 3) #define GET_BYPASS_TX_PARSER_ENCAP (((REG32(ADR_CONTROL)) & 0x00000010 ) >> 4) #define GET_HDR_STRIP (((REG32(ADR_CONTROL)) & 0x00000020 ) >> 5) #define GET_ERP_PROTECT (((REG32(ADR_CONTROL)) & 0x000000c0 ) >> 6) #define GET_PRO_VER (((REG32(ADR_CONTROL)) & 0x00000300 ) >> 8) #define GET_TXQ_ID0 (((REG32(ADR_CONTROL)) & 0x00007000 ) >> 12) #define GET_TXQ_ID1 (((REG32(ADR_CONTROL)) & 0x00070000 ) >> 16) #define GET_TX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00100000 ) >> 20) #define GET_RX_ETHER_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00200000 ) >> 21) #define GET_RX_NULL_TRAP_EN (((REG32(ADR_CONTROL)) & 0x00400000 ) >> 22) #define GET_TRX_DEBUG_CNT_ENA (((REG32(ADR_CONTROL)) & 0x10000000 ) >> 28) #define GET_HCI_TX_AGG_EN (((REG32(ADR_HCI_TRX_MODE)) & 0x00000001 ) >> 0) #define GET_HCI_RX_EN (((REG32(ADR_HCI_TRX_MODE)) & 0x00000002 ) >> 1) #define GET_HCI_RX_FORM_1 (((REG32(ADR_HCI_TRX_MODE)) & 0x40000000 ) >> 30) #define GET_HCI_RX_FORM_0 (((REG32(ADR_HCI_TRX_MODE)) & 0x80000000 ) >> 31) #define GET_TX_FLOW_CTRL (((REG32(ADR_TX_FLOW_0)) & 0x0000ffff ) >> 0) #define GET_TX_FLOW_MGMT (((REG32(ADR_TX_FLOW_0)) & 0xffff0000 ) >> 16) #define GET_TX_FLOW_DATA (((REG32(ADR_TX_FLOW_1)) & 0xffffffff ) >> 0) #define GET_SD_RX_LEN (((REG32(ADR_REMAINING_RX_PACKET_LENGTH)) & 0x0000ffff ) >> 0) #define GET_RX_ACCU_LEN (((REG32(ADR_RX_PACKET_LENGTH_STATUS)) & 0x0000ffff ) >> 0) #define GET_HCI_RX_LEN (((REG32(ADR_RX_PACKET_LENGTH_STATUS)) & 0xffff0000 ) >> 16) #define GET_DOT11RTSTHRESHOLD (((REG32(ADR_THRESHOLD)) & 0xffff0000 ) >> 16) #define GET_TX_ERR_RECOVER (((REG32(ADR_TX_ERROR_RECEOVERY)) & 0x00000001 ) >> 0) #define GET_TX_ERR_FIRST_4B_EN (((REG32(ADR_TX_ERROR_RECEOVERY)) & 0x00000002 ) >> 1) #define GET_RX_INT_TIMEOUT (((REG32(ADR_TX_ERROR_RECEOVERY)) & 0xffff0000 ) >> 16) #define GET_TXF_ID (((REG32(ADR_TXFID_INCREASE)) & 0x0000003f ) >> 0) #define GET_SEQ_CTRL (((REG32(ADR_GLOBAL_SEQUENCE)) & 0x0000ffff ) >> 0) #define GET_DBG_ADDR_EN (((REG32(ADR_HCI_REG_0X2C)) & 0x00000001 ) >> 0) #define GET_DBG_ADDR_FENCE (((REG32(ADR_HCI_REG_0X2C)) & 0x0000ff00 ) >> 8) #define GET_TX_PBOFFSET (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x000000ff ) >> 0) #define GET_TX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x0000ff00 ) >> 8) #define GET_RX_INFO_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0x00ff0000 ) >> 16) #define GET_RX_LAST_PHY_SIZE (((REG32(ADR_HCI_TX_RX_INFO_SIZE)) & 0xff000000 ) >> 24) #define GET_TX_INFO_CLEAR_SIZE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x0000003f ) >> 0) #define GET_TX_INFO_CLEAR_ENABLE (((REG32(ADR_HCI_TX_INFO_CLEAR)) & 0x00000100 ) >> 8) #define GET_RX_PER_RD_LEN (((REG32(ADR_HCI_TO_PKTBUF_SETTING)) & 0x0000003f ) >> 0) #define GET_BACKUP_PG_CNT (((REG32(ADR_HCI_TO_PKTBUF_SETTING)) & 0x00000f00 ) >> 8) #define GET_MANUAL_HCI_ALLOC_EN (((REG32(ADR_HCI_MANUAL_ALLOC)) & 0x00000001 ) >> 0) #define GET_MANUAL_HCI_ALLOC_SIZE (((REG32(ADR_HCI_MANUAL_ALLOC_ACTION)) & 0x0000ffff ) >> 0) #define GET_MANUAL_ALLOC_ID (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x0000007f ) >> 0) #define GET_HAS_MANUAL_BUF (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x00000080 ) >> 7) #define GET_DOUBLE_ALLOC_ERR (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x00000100 ) >> 8) #define GET_NO_ALLOC_ERR (((REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) & 0x00000200 ) >> 9) #define GET_TXTRAP_ETHTYPE1 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0) #define GET_TXTRAP_ETHTYPE0 (((REG32(ADR_TX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16) #define GET_RXTRAP_ETHTYPE1 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0x0000ffff ) >> 0) #define GET_RXTRAP_ETHTYPE0 (((REG32(ADR_RX_ETHER_TYPE_1)) & 0xffff0000 ) >> 16) #define GET_TX_PKT_SEND_LEN (((REG32(ADR_TX_PACKET_LENGTH)) & 0x0000ffff ) >> 0) #define GET_TX_SDIO_PKT_LEN (((REG32(ADR_TX_PACKET_LENGTH)) & 0xffff0000 ) >> 16) #define GET_TX_PKT_SEND_ID (((REG32(ADR_TX_PACKET_ID)) & 0x0000007f ) >> 0) #define GET_HCI_PENDING_RX_MPDU_CNT (((REG32(ADR_RX_RESCUE_HELPER)) & 0x0000001f ) >> 0) #define GET_HCI_RX_HALT (((REG32(ADR_RX_RESCUE_HELPER)) & 0x00000100 ) >> 8) #define GET_HIF_LOOP_BACK (((REG32(ADR_RX_RESCUE_HELPER)) & 0x00000200 ) >> 9) #define GET_USB_BULK_IN_LEN_INIT (((REG32(ADR_RX_RESCUE_HELPER)) & 0x40000000 ) >> 30) #define GET_HCI_RX_MPDU_DEQUE (((REG32(ADR_RX_RESCUE_HELPER)) & 0x80000000 ) >> 31) #define GET_HCI_BULK_IN_HOST_SIZE (((REG32(ADR_HCI_FORCE_PRE_BULK_IN)) & 0x0001ffff ) >> 0) #define GET_HCI_BULK_IN_TIME_OUT (((REG32(ADR_HCI_BULK_IN_TIME_OUT_VALUE)) & 0xffffffff ) >> 0) #define GET_HCI_MONITOR_REG0 (((REG32(ADR_HCI_STATE_DEBUG_MODE_0)) & 0xffffffff ) >> 0) #define GET_HCI_MONITOR_REG2 (((REG32(ADR_HCI_STATE_DEBUG_MODE_2)) & 0xffffffff ) >> 0) #define GET_HCI_MONITOR_REG3 (((REG32(ADR_HCI_STATE_DEBUG_MODE_3)) & 0xffffffff ) >> 0) #define GET_HCI_MONITOR_REG4 (((REG32(ADR_HCI_STATE_DEBUG_MODE_4)) & 0xffffffff ) >> 0) #define GET_HCI_MONITOR_REG5 (((REG32(ADR_HCI_STATE_DEBUG_MODE_5)) & 0xffffffff ) >> 0) #define GET_SDIO_TX_INVALID_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_6)) & 0xffffffff ) >> 0) #define GET_HCI_MB_MAX_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x000000ff ) >> 0) #define GET_HCI_PROC_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x0000ff00 ) >> 8) #define GET_SDIO_TRANS_CNT (((REG32(ADR_HCI_STATE_DEBUG_MODE_7)) & 0x00ff0000 ) >> 16) #define GET_TX_ON_DEMAND_LENGTH (((REG32(ADR_HCI_TX_ON_DEMAND_LENGTH)) & 0xffffffff ) >> 0) #define GET_HCI_TX_ALLOC_CNT (((REG32(ADR_HCI_TX_ALLOC_SUCCESS_COUNT)) & 0xffffffff ) >> 0) #define GET_HCI_TX_ALLOC_TIME (((REG32(ADR_HCI_TX_ALLOC_SPENDING_TIME)) & 0xffffffff ) >> 0) #define GET_RX_PKT_TRAP_COUNTER (((REG32(ADR_RX_TRAP_COUNT)) & 0xffffffff ) >> 0) #define GET_TX_PKT_TRAP_COUNTER (((REG32(ADR_TX_TRAP_COUNT)) & 0xffffffff ) >> 0) #define GET_RX_PKT_DROP_COUNTER (((REG32(ADR_RX_DROP_COUNT)) & 0xffffffff ) >> 0) #define GET_TX_PKT_DROP_COUNTER (((REG32(ADR_TX_DROP_COUNT)) & 0xffffffff ) >> 0) #define GET_HOST_EVENT_COUNTER (((REG32(ADR_RX_HOST_EVENT_COUNT)) & 0xffffffff ) >> 0) #define GET_HOST_CMD_COUNTER (((REG32(ADR_TX_HOST_COMMAND_COUNT)) & 0xffffffff ) >> 0) #define GET_RX_PKT_COUNTER (((REG32(ADR_RX_PACKET_COUNTER)) & 0xffffffff ) >> 0) #define GET_TX_PKT_COUNTER (((REG32(ADR_TX_PACKET_COUNTER)) & 0xffffffff ) >> 0) #define GET_HOST_RX_FAIL_COUNTER (((REG32(ADR_SDIO_RX_FAIL_COUNT)) & 0xffffffff ) >> 0) #define GET_HOST_TX_FAIL_COUNTER (((REG32(ADR_SDIO_TX_FAIL_COUNT)) & 0xffffffff ) >> 0) #define GET_CORRECT_RATE_REP_LEN (((REG32(ADR_CORRECT_RATE_REPORT_LENGTH)) & 0x00000001 ) >> 0) #define GET_TX_PKT_SEND_TO_RX (((REG32(ADR_TX_PACKET_SEND_TO_RX_DIRECTLY)) & 0x00000001 ) >> 0) #define GET_PEERPS_REJECT_ENABLE (((REG32(ADR_POWER_SAVING_PEER_REJECT_FUNCTION)) & 0x00000001 ) >> 0) #define GET_TRANS_FULL_PKT_AMPDU1P2 (((REG32(ADR_POWER_SAVING_PEER_REJECT_FUNCTION)) & 0x00000010 ) >> 4) #define GET_TX_RX_TRAP_HW_ID_SELECT_ENABLE (((REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) & 0x00000001 ) >> 0) #define GET_TX_TRAP_HW_ID (((REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) & 0x000000f0 ) >> 4) #define GET_RX_TRAP_HW_ID (((REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) & 0x00000f00 ) >> 8) #define GET_RX_DEBUG_HCI_EXP_0 (((REG32(ADR_RX_HCI_EXP_0_CTRL)) & 0x00000001 ) >> 0) #define GET_RX_DEBUG_HCI_EXP_0_RND_MODE (((REG32(ADR_RX_HCI_EXP_0_CTRL)) & 0x00000030 ) >> 4) #define GET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN (((REG32(ADR_RX_HCI_EXP_0_LEN)) & 0x0000ffff ) >> 0) #define GET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX (((REG32(ADR_RX_HCI_EXP_0_LEN)) & 0xffff0000 ) >> 16) #define GET_RX_AGG_CNT (((REG32(ADR_FORCE_RX_AGGREGATION_MODE)) & 0x0000000f ) >> 0) #define GET_RX_AGG_METHOD_3 (((REG32(ADR_FORCE_RX_AGGREGATION_MODE)) & 0x00000080 ) >> 7) #define GET_RX_AGG_TIMER_RELOAD_VALUE (((REG32(ADR_FORCE_RX_AGGREGATION_MODE)) & 0xffff0000 ) >> 16) #define GET_CS_START_ADDR (((REG32(ADR_CS_START_ADDR)) & 0x0000ffff ) >> 0) #define GET_CS_PKT_ID (((REG32(ADR_CS_START_ADDR)) & 0x007f0000 ) >> 16) #define GET_ADD_LEN (((REG32(ADR_CS_ADD_LEN)) & 0x0000ffff ) >> 0) #define GET_CS_ADDER_EN (((REG32(ADR_CS_CMD)) & 0x00000001 ) >> 0) #define GET_PSEUDO (((REG32(ADR_CS_CMD)) & 0x00000002 ) >> 1) #define GET_CALCULATE (((REG32(ADR_CS_INI_BUF)) & 0xffffffff ) >> 0) #define GET_L4_LEN (((REG32(ADR_CS_PSEUDO_BUF)) & 0x0000ffff ) >> 0) #define GET_L4_PROTOL (((REG32(ADR_CS_PSEUDO_BUF)) & 0x00ff0000 ) >> 16) #define GET_CHECK_SUM (((REG32(ADR_CS_CHECK_SUM)) & 0x0000ffff ) >> 0) #define GET_RAND_EN (((REG32(ADR_RAND_EN)) & 0x00000001 ) >> 0) #define GET_RAND_NUM (((REG32(ADR_RAND_NUM)) & 0xffffffff ) >> 0) #define GET_MUL_OP1 (((REG32(ADR_MUL_OP1)) & 0xffffffff ) >> 0) #define GET_MUL_OP2 (((REG32(ADR_MUL_OP2)) & 0xffffffff ) >> 0) #define GET_MUL_ANS0 (((REG32(ADR_MUL_ANS0)) & 0xffffffff ) >> 0) #define GET_MUL_ANS1 (((REG32(ADR_MUL_ANS1)) & 0xffffffff ) >> 0) #define GET_RD_ADDR (((REG32(ADR_DMA_RDATA)) & 0x0000ffff ) >> 0) #define GET_RD_ID (((REG32(ADR_DMA_RDATA)) & 0x007f0000 ) >> 16) #define GET_WR_ADDR (((REG32(ADR_DMA_WDATA)) & 0x0000ffff ) >> 0) #define GET_WR_ID (((REG32(ADR_DMA_WDATA)) & 0x007f0000 ) >> 16) #define GET_LEN (((REG32(ADR_DMA_LEN)) & 0x0000ffff ) >> 0) #define GET_CLR (((REG32(ADR_DMA_CLR)) & 0x00000001 ) >> 0) #define GET_PHY_MODE (((REG32(ADR_NAV_DATA)) & 0x00000003 ) >> 0) #define GET_SHRT_PREAM (((REG32(ADR_NAV_DATA)) & 0x00000004 ) >> 2) #define GET_SHRT_GI (((REG32(ADR_NAV_DATA)) & 0x00000008 ) >> 3) #define GET_DATA_RATE (((REG32(ADR_NAV_DATA)) & 0x000007f0 ) >> 4) #define GET_MCS (((REG32(ADR_NAV_DATA)) & 0x00007000 ) >> 12) #define GET_FRAME_LEN (((REG32(ADR_NAV_DATA)) & 0xffff0000 ) >> 16) #define GET_DURATION (((REG32(ADR_CO_NAV)) & 0x0000ffff ) >> 0) #define GET_SHA_DST_ADDR (((REG32(ADR_SHA_DST_ADDR)) & 0xffffffff ) >> 0) #define GET_SHA_SRC_ADDR (((REG32(ADR_SHA_SRC_ADDR)) & 0xffffffff ) >> 0) #define GET_SHA_BUSY (((REG32(ADR_SHA_SETTING)) & 0x00000001 ) >> 0) #define GET_SHA_ENDIAN (((REG32(ADR_SHA_SETTING)) & 0x00000002 ) >> 1) #define GET_EFS_CLKFREQ (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00000fff ) >> 0) #define GET_EFS_VDDQ_EN_LOW_ACTIVE (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x00010000 ) >> 16) #define GET_EFS_CLKFREQ_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0x0ff00000 ) >> 20) #define GET_EFS_PRE_RD (((REG32(ADR_EFUSE_CLK_FREQ)) & 0xf0000000 ) >> 28) #define GET_EFS_LDO_ON (((REG32(ADR_EFUSE_LDO_TIME)) & 0x0000ffff ) >> 0) #define GET_EFS_LDO_OFF (((REG32(ADR_EFUSE_LDO_TIME)) & 0xffff0000 ) >> 16) #define GET_EFS_RD_FLAG (((REG32(ADR_EFUSE_STATUS)) & 0x00000001 ) >> 0) #define GET_EFS_PROGRESS_DONE (((REG32(ADR_EFUSE_STATUS2)) & 0x00000001 ) >> 0) #define GET_EFS_WR_KICK (((REG32(ADR_EFUSE_WR_KICK)) & 0x00000001 ) >> 0) #define GET_EFS_RD_KICK (((REG32(ADR_EFUSE_RD_KICK)) & 0x00000001 ) >> 0) #define GET_EFS_VDDQ_EN (((REG32(ADR_EFUSE_VDDQ_EN)) & 0x00000001 ) >> 0) #define GET_EFS_BYTE_0 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_1 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_2 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_3 (((REG32(ADR_EFUSE_WDATA_0_0)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_4 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_5 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_6 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_7 (((REG32(ADR_EFUSE_WDATA_0_1)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_8 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_9 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_10 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_11 (((REG32(ADR_EFUSE_WDATA_0_2)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_12 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_13 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_14 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_15 (((REG32(ADR_EFUSE_WDATA_0_3)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_16 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_17 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_18 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_19 (((REG32(ADR_EFUSE_WDATA_0_4)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_20 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_21 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_22 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_23 (((REG32(ADR_EFUSE_WDATA_0_5)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_24 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_25 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_26 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_27 (((REG32(ADR_EFUSE_WDATA_0_6)) & 0xff000000 ) >> 24) #define GET_EFS_BYTE_28 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0x000000ff ) >> 0) #define GET_EFS_BYTE_29 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0x0000ff00 ) >> 8) #define GET_EFS_BYTE_30 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0x00ff0000 ) >> 16) #define GET_EFS_BYTE_31 (((REG32(ADR_EFUSE_WDATA_0_7)) & 0xff000000 ) >> 24) #define GET_SPI_M_FRONT_DLY (((REG32(ADR_SPI_DELAY)) & 0x0000ffff ) >> 0) #define GET_SPI_M_BACK_DLY (((REG32(ADR_SPI_DELAY)) & 0xffff0000 ) >> 16) #define GET_SPI_CLK_DIV (((REG32(ADR_SPI_CLK_DIV)) & 0x0000ffff ) >> 0) #define GET_SPI_MASTER_BUSY (((REG32(ADR_SPI_BUSY)) & 0x00000001 ) >> 0) #define GET_SPI_CLR (((REG32(ADR_SPI_CLR)) & 0x00000001 ) >> 0) #define GET_CPOL (((REG32(ADR_SPI_MAS_MODE)) & 0x00000001 ) >> 0) #define GET_CPHA (((REG32(ADR_SPI_MAS_MODE)) & 0x00000002 ) >> 1) #define GET_CSPOL (((REG32(ADR_SPI_M_CFG)) & 0x00000001 ) >> 0) #define GET_INV_DATA (((REG32(ADR_SPI_M_CFG)) & 0x00000002 ) >> 1) #define GET_FAST_CLK (((REG32(ADR_SPI_M_CFG)) & 0x00000004 ) >> 2) #define GET_AUTO_CSN (((REG32(ADR_SPI_M_CFG)) & 0x00000008 ) >> 3) #define GET_THREE_WIRE (((REG32(ADR_SPI_M_CFG)) & 0x000003f0 ) >> 4) #define GET_ENDIAN (((REG32(ADR_SPI_M_CFG)) & 0x00000400 ) >> 10) #define GET_EARLY_SAMPLE (((REG32(ADR_SPI_M_CFG)) & 0x00000800 ) >> 11) #define GET_SPI_CSN (((REG32(ADR_SPI_CFG)) & 0x00000001 ) >> 0) #define GET_CMD_LEN_SPIMAS (((REG32(ADR_SPI_MAS_COMMAND_LEN)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_TB0_31_0 (((REG32(ADR_MRX_MCAST_TB0_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_TB0_47_32 (((REG32(ADR_MRX_MCAST_TB0_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_MASK0_31_0 (((REG32(ADR_MRX_MCAST_MK0_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_MASK0_47_32 (((REG32(ADR_MRX_MCAST_MK0_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_CTRL_0 (((REG32(ADR_MRX_MCAST_CTRL0)) & 0x00000003 ) >> 0) #define GET_MRX_MCAST_TB1_31_0 (((REG32(ADR_MRX_MCAST_TB1_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_TB1_47_32 (((REG32(ADR_MRX_MCAST_TB1_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_MASK1_31_0 (((REG32(ADR_MRX_MCAST_MK1_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_MASK1_47_32 (((REG32(ADR_MRX_MCAST_MK1_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_CTRL_1 (((REG32(ADR_MRX_MCAST_CTRL1)) & 0x00000003 ) >> 0) #define GET_MRX_MCAST_TB2_31_0 (((REG32(ADR_MRX_MCAST_TB2_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_TB2_47_32 (((REG32(ADR_MRX_MCAST_TB2_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_MASK2_31_0 (((REG32(ADR_MRX_MCAST_MK2_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_MASK2_47_32 (((REG32(ADR_MRX_MCAST_MK2_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_CTRL_2 (((REG32(ADR_MRX_MCAST_CTRL2)) & 0x00000003 ) >> 0) #define GET_MRX_MCAST_TB3_31_0 (((REG32(ADR_MRX_MCAST_TB3_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_TB3_47_32 (((REG32(ADR_MRX_MCAST_TB3_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_MASK3_31_0 (((REG32(ADR_MRX_MCAST_MK3_0)) & 0xffffffff ) >> 0) #define GET_MRX_MCAST_MASK3_47_32 (((REG32(ADR_MRX_MCAST_MK3_1)) & 0x0000ffff ) >> 0) #define GET_MRX_MCAST_CTRL_3 (((REG32(ADR_MRX_MCAST_CTRL3)) & 0x00000003 ) >> 0) #define GET_MRX_PHY_INFO (((REG32(ADR_MRX_PHY_INFO)) & 0xffffffff ) >> 0) #define GET_DBG_BA_TYPE (((REG32(ADR_MRX_BA_DBG)) & 0x0000003f ) >> 0) #define GET_DBG_BA_SEQ (((REG32(ADR_MRX_BA_DBG)) & 0x000fff00 ) >> 8) #define GET_MRX_FLT_TB0 (((REG32(ADR_MRX_FLT_TB0)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB1 (((REG32(ADR_MRX_FLT_TB1)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB2 (((REG32(ADR_MRX_FLT_TB2)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB3 (((REG32(ADR_MRX_FLT_TB3)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB4 (((REG32(ADR_MRX_FLT_TB4)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB5 (((REG32(ADR_MRX_FLT_TB5)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB6 (((REG32(ADR_MRX_FLT_TB6)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB7 (((REG32(ADR_MRX_FLT_TB7)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB8 (((REG32(ADR_MRX_FLT_TB8)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB9 (((REG32(ADR_MRX_FLT_TB9)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB10 (((REG32(ADR_MRX_FLT_TB10)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB11 (((REG32(ADR_MRX_FLT_TB11)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB12 (((REG32(ADR_MRX_FLT_TB12)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB13 (((REG32(ADR_MRX_FLT_TB13)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB14 (((REG32(ADR_MRX_FLT_TB14)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_TB15 (((REG32(ADR_MRX_FLT_TB15)) & 0x00007fff ) >> 0) #define GET_MRX_FLT_EN0 (((REG32(ADR_MRX_FLT_EN0)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN1 (((REG32(ADR_MRX_FLT_EN1)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN2 (((REG32(ADR_MRX_FLT_EN2)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN3 (((REG32(ADR_MRX_FLT_EN3)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN4 (((REG32(ADR_MRX_FLT_EN4)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN5 (((REG32(ADR_MRX_FLT_EN5)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN6 (((REG32(ADR_MRX_FLT_EN6)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN7 (((REG32(ADR_MRX_FLT_EN7)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN8 (((REG32(ADR_MRX_FLT_EN8)) & 0x0000ffff ) >> 0) #define GET_MRX_LEN_FLT (((REG32(ADR_MRX_LEN_FLT)) & 0x0000ffff ) >> 0) #define GET_RX_FLOW_DATA (((REG32(ADR_RX_FLOW_DATA)) & 0xffffffff ) >> 0) #define GET_RX_FLOW_MNG (((REG32(ADR_RX_FLOW_MNG)) & 0x0000ffff ) >> 0) #define GET_RX_FLOW_CTRL (((REG32(ADR_RX_FLOW_CTRL)) & 0x0000ffff ) >> 0) #define GET_MRX_STP_EN (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x00000001 ) >> 0) #define GET_MRX_STP_OFST (((REG32(ADR_RX_TIME_STAMP_CFG)) & 0x0000ff00 ) >> 8) #define GET_DBG_FF_FULL (((REG32(ADR_DBG_FF_FULL)) & 0x0000ffff ) >> 0) #define GET_DBG_FF_FULL_CLR (((REG32(ADR_DBG_FF_FULL)) & 0x80000000 ) >> 31) #define GET_DBG_WFF_FULL (((REG32(ADR_DBG_WFF_FULL)) & 0x0000ffff ) >> 0) #define GET_DBG_WFF_FULL_CLR (((REG32(ADR_DBG_WFF_FULL)) & 0x80000000 ) >> 31) #define GET_DBG_MB_FULL (((REG32(ADR_DBG_MB_FULL)) & 0x0000ffff ) >> 0) #define GET_DBG_MB_FULL_CLR (((REG32(ADR_DBG_MB_FULL)) & 0x80000000 ) >> 31) #define GET_BA_CTRL (((REG32(ADR_BA_CTRL)) & 0x00000003 ) >> 0) #define GET_BA_DBG_EN (((REG32(ADR_BA_CTRL)) & 0x00000004 ) >> 2) #define GET_BA_AGRE_EN (((REG32(ADR_BA_CTRL)) & 0x00000008 ) >> 3) #define GET_BA_TA_31_0 (((REG32(ADR_BA_TA_0)) & 0xffffffff ) >> 0) #define GET_BA_TA_47_32 (((REG32(ADR_BA_TA_1)) & 0x0000ffff ) >> 0) #define GET_BA_TID (((REG32(ADR_BA_TID)) & 0x0000000f ) >> 0) #define GET_BA_ST_SEQ (((REG32(ADR_BA_ST_SEQ)) & 0x00000fff ) >> 0) #define GET_BA_SB0 (((REG32(ADR_BA_SB0)) & 0xffffffff ) >> 0) #define GET_BA_SB1 (((REG32(ADR_BA_SB1)) & 0xffffffff ) >> 0) #define GET_MRX_WD (((REG32(ADR_MRX_WATCH_DOG)) & 0x0001ffff ) >> 0) #define GET_ACK_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000001 ) >> 0) #define GET_BA_GEN_EN (((REG32(ADR_ACK_GEN_EN)) & 0x00000002 ) >> 1) #define GET_ACK_GEN_DUR (((REG32(ADR_ACK_GEN_PARA)) & 0x0000ffff ) >> 0) #define GET_ACK_GEN_INFO (((REG32(ADR_ACK_GEN_PARA)) & 0x00ff0000 ) >> 16) #define GET_ACK_GEN_RA_31_0 (((REG32(ADR_ACK_GEN_RA_0)) & 0xffffffff ) >> 0) #define GET_ACK_GEN_RA_47_32 (((REG32(ADR_ACK_GEN_RA_1)) & 0x0000ffff ) >> 0) #define GET_MIB_LEN_FAIL (((REG32(ADR_MIB_LEN_FAIL)) & 0x0000ffff ) >> 0) #define GET_TRAP_HW_ID (((REG32(ADR_TRAP_HW_ID)) & 0x0000000f ) >> 0) #define GET_ID_IN_USE (((REG32(ADR_ID_IN_USE)) & 0x000000ff ) >> 0) #define GET_MRX_ERR (((REG32(ADR_MRX_ERR)) & 0xffffffff ) >> 0) #define GET_GRP_WSID (((REG32(ADR_GROUP_WSID)) & 0x0000000f ) >> 0) #define GET_ADDR1A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000003 ) >> 0) #define GET_ADDR2A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x0000000c ) >> 2) #define GET_ADDR3A_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000030 ) >> 4) #define GET_ADDR1B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x000000c0 ) >> 6) #define GET_ADDR2B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000300 ) >> 8) #define GET_ADDR3B_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00000c00 ) >> 10) #define GET_ADDR3C_SEL (((REG32(ADR_HDR_ADDR_SEL)) & 0x00003000 ) >> 12) #define GET_FRM_CTRL (((REG32(ADR_FRAME_TYPE_CNTR_SET)) & 0x0000003f ) >> 0) #define GET_SCOREBOAD_SIZE (((REG32(ADR_AMPDU_SCOREBOAD_SIZE)) & 0x0000007f ) >> 0) #define GET_MASK_ABNORMAL_CRC (((REG32(ADR_CHANNEL)) & 0x00000001 ) >> 0) #define GET_PS_EN (((REG32(ADR_CHANNEL)) & 0x00000002 ) >> 1) #define GET_MULTI_AMPDU_W_EN (((REG32(ADR_CHANNEL)) & 0x00000004 ) >> 2) #define GET_BA_H_QUEUE_EN (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x00000001 ) >> 0) #define GET_EOSP_H_QUEUE_EN (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x00000002 ) >> 1) #define GET_EOSP_HW_ID (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x0000003c ) >> 2) #define GET_BA_HW_ID (((REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) & 0x000003c0 ) >> 6) #define GET_IDX_EXTEND (((REG32(ADR_DUAL_IDX_EXTEND)) & 0x00000001 ) >> 0) #define GET_MRX_FLT_EN9 (((REG32(ADR_MRX_FLT_EN9)) & 0x0000ffff ) >> 0) #define GET_MRX_FLT_EN10 (((REG32(ADR_MRX_FLT_EN10)) & 0x0000ffff ) >> 0) #define GET_CSR_PHY_INFO (((REG32(ADR_PHY_INFO)) & 0x00007fff ) >> 0) #define GET_AMPDU_SIG (((REG32(ADR_AMPDU_SIG)) & 0x000000ff ) >> 0) #define GET_MIB_AMPDU (((REG32(ADR_MIB_AMPDU)) & 0xffffffff ) >> 0) #define GET_LEN_FLT (((REG32(ADR_LEN_FLT)) & 0x0000ffff ) >> 0) #define GET_MIB_DELIMITER (((REG32(ADR_MIB_DELIMITER)) & 0x0000ffff ) >> 0) #define GET_MTX_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00010000 ) >> 16) #define GET_MTX_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00020000 ) >> 17) #define GET_MTX_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00040000 ) >> 18) #define GET_MTX_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00080000 ) >> 19) #define GET_MTX_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00100000 ) >> 20) #define GET_MTX_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00200000 ) >> 21) #define GET_MTX_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x00400000 ) >> 22) #define GET_MTX_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x00800000 ) >> 23) #define GET_MTX_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x01000000 ) >> 24) #define GET_MTX_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x02000000 ) >> 25) #define GET_MTX_INT_Q5_Q_EMPTY (((REG32(ADR_MTX_INT_STS)) & 0x04000000 ) >> 26) #define GET_MTX_INT_Q5_TXOP_RUNOUT (((REG32(ADR_MTX_INT_STS)) & 0x08000000 ) >> 27) #define GET_MTX_EN_INT_Q0_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00010000 ) >> 16) #define GET_MTX_EN_INT_Q0_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00020000 ) >> 17) #define GET_MTX_EN_INT_Q1_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00040000 ) >> 18) #define GET_MTX_EN_INT_Q1_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00080000 ) >> 19) #define GET_MTX_EN_INT_Q2_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00100000 ) >> 20) #define GET_MTX_EN_INT_Q2_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00200000 ) >> 21) #define GET_MTX_EN_INT_Q3_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x00400000 ) >> 22) #define GET_MTX_EN_INT_Q3_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x00800000 ) >> 23) #define GET_MTX_EN_INT_Q4_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x01000000 ) >> 24) #define GET_MTX_EN_INT_Q4_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x02000000 ) >> 25) #define GET_MTX_EN_INT_Q5_Q_EMPTY (((REG32(ADR_MTX_INT_EN)) & 0x04000000 ) >> 26) #define GET_MTX_EN_INT_Q5_TXOP_RUNOUT (((REG32(ADR_MTX_INT_EN)) & 0x08000000 ) >> 27) #define GET_MTX_MTX2PHY_SLOW (((REG32(ADR_MTX_MISC_EN)) & 0x00000001 ) >> 0) #define GET_MTX_M2M_SLOW_PRD (((REG32(ADR_MTX_MISC_EN)) & 0x0000000e ) >> 1) #define GET_MTX_AMPDU_CRC8_AUTO (((REG32(ADR_MTX_MISC_EN)) & 0x00000020 ) >> 5) #define GET_MTX_BLOCKTX_IGNORE_BT_BUSY (((REG32(ADR_MTX_MISC_EN)) & 0x00000040 ) >> 6) #define GET_MTX_RAW_DATA_MODE (((REG32(ADR_MTX_MISC_EN)) & 0x00000080 ) >> 7) #define GET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP (((REG32(ADR_MTX_MISC_EN)) & 0x00000800 ) >> 11) #define GET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN (((REG32(ADR_MTX_MISC_EN)) & 0x00001000 ) >> 12) #define GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS (((REG32(ADR_MTX_MISC_EN)) & 0x00002000 ) >> 13) #define GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY (((REG32(ADR_MTX_MISC_EN)) & 0x00004000 ) >> 14) #define GET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY (((REG32(ADR_MTX_MISC_EN)) & 0x00008000 ) >> 15) #define GET_MTX_HALT_Q_MB (((REG32(ADR_MTX_MISC_EN)) & 0x007f0000 ) >> 16) #define GET_MTX_IGNORE_PHYRX_IFS_DELTATIME (((REG32(ADR_MTX_MISC_EN)) & 0x01000000 ) >> 24) #define GET_MTX_SELFSTA_PS (((REG32(ADR_MTX_MISC_EN)) & 0x02000000 ) >> 25) #define GET_NO_PKT_BUF_REDUCTION (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000001 ) >> 0) #define GET_NO_REDUCE_TXALLFAIL_PKT (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000004 ) >> 2) #define GET_NO_REDUCE_PKT_PEERPS_MPDU (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000010 ) >> 4) #define GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2 (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000040 ) >> 6) #define GET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3 (((REG32(ADR_MTX_TX_REPORT_OPTION)) & 0x00000080 ) >> 7) #define GET_RO_PTC_SCHEDULE (((REG32(ADR_MTX_STATUS0)) & 0x0000000f ) >> 0) #define GET_RO_FSM_MTXPTC (((REG32(ADR_MTX_STATUS0)) & 0x00000070 ) >> 4) #define GET_RO_ACT_MASK (((REG32(ADR_MTX_STATUS0)) & 0x00007f00 ) >> 8) #define GET_RO_CAND_MASK (((REG32(ADR_MTX_STATUS0)) & 0x007f0000 ) >> 16) #define GET_RO_WAIT_RESPONSE_PHASE (((REG32(ADR_MTX_STATUS0)) & 0x03000000 ) >> 24) #define GET_RO_FSM_MTXHALT (((REG32(ADR_MTX_STATUS0)) & 0x30000000 ) >> 28) #define GET_RO_FSM_MTXDMA (((REG32(ADR_MTX_STATUS4)) & 0x00000007 ) >> 0) #define GET_RO_FSM_MTXPHYTX (((REG32(ADR_MTX_STATUS4)) & 0x00000070 ) >> 4) #define GET_RO_MTXDMA_CMD (((REG32(ADR_MTX_STATUS4)) & 0x00003f00 ) >> 8) #define GET_RO_TXOP_INTERVAL (((REG32(ADR_MTX_STATUS4)) & 0xffff0000 ) >> 16) #define GET_MTX_HALT_MODE0 (((REG32(ADR_MTX_HALT_OPTION)) & 0x00000001 ) >> 0) #define GET_BLOCK_TXQ (((REG32(ADR_MTX_HALT_OPTION)) & 0x007f0000 ) >> 16) #define GET_MTX_HALT_IGNORE_TXREQ_EN (((REG32(ADR_MTX_HALT_OPTION)) & 0x01000000 ) >> 24) #define GET_MTX_HALT_IGNORE_RXREQ_EN (((REG32(ADR_MTX_HALT_OPTION)) & 0x02000000 ) >> 25) #define GET_DBG_PHYTX_PROCEED (((REG32(ADR_MTX_PHYTX_DBG1)) & 0x00000001 ) >> 0) #define GET_MTX_MIB_CNT0_FRAME (((REG32(ADR_MTX_MIB_WSID0)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT0_ATTEMPT (((REG32(ADR_MTX_MIB_WSID0)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT0_SUCC (((REG32(ADR_MTX_MIB_WSID0)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN0 (((REG32(ADR_MTX_MIB_WSID0)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT1_FRAME (((REG32(ADR_MTX_MIB_WSID1)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT1_ATTEMPT (((REG32(ADR_MTX_MIB_WSID1)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT1_SUCC (((REG32(ADR_MTX_MIB_WSID1)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN1 (((REG32(ADR_MTX_MIB_WSID1)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT2_FRAME (((REG32(ADR_MTX_MIB_WSID2)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT2_ATTEMPT (((REG32(ADR_MTX_MIB_WSID2)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT2_SUCC (((REG32(ADR_MTX_MIB_WSID2)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN2 (((REG32(ADR_MTX_MIB_WSID2)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT3_FRAME (((REG32(ADR_MTX_MIB_WSID3)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT3_ATTEMPT (((REG32(ADR_MTX_MIB_WSID3)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT3_SUCC (((REG32(ADR_MTX_MIB_WSID3)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN3 (((REG32(ADR_MTX_MIB_WSID3)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT4_FRAME (((REG32(ADR_MTX_MIB_WSID4)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT4_ATTEMPT (((REG32(ADR_MTX_MIB_WSID4)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT4_SUCC (((REG32(ADR_MTX_MIB_WSID4)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN4 (((REG32(ADR_MTX_MIB_WSID4)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT5_FRAME (((REG32(ADR_MTX_MIB_WSID5)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT5_ATTEMPT (((REG32(ADR_MTX_MIB_WSID5)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT5_SUCC (((REG32(ADR_MTX_MIB_WSID5)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN5 (((REG32(ADR_MTX_MIB_WSID5)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT6_FRAME (((REG32(ADR_MTX_MIB_WSID6)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT6_ATTEMPT (((REG32(ADR_MTX_MIB_WSID6)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT6_SUCC (((REG32(ADR_MTX_MIB_WSID6)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN6 (((REG32(ADR_MTX_MIB_WSID6)) & 0x40000000 ) >> 30) #define GET_MTX_MIB_CNT7_FRAME (((REG32(ADR_MTX_MIB_WSID7)) & 0x000003ff ) >> 0) #define GET_MTX_MIB_CNT7_ATTEMPT (((REG32(ADR_MTX_MIB_WSID7)) & 0x000ffc00 ) >> 10) #define GET_MTX_MIB_CNT7_SUCC (((REG32(ADR_MTX_MIB_WSID7)) & 0x3ff00000 ) >> 20) #define GET_MTX_MIB_EN7 (((REG32(ADR_MTX_MIB_WSID7)) & 0x40000000 ) >> 30) #define GET_EN_UNEXPECT_WSID (((REG32(ADR_STAT_CONF0)) & 0x00000001 ) >> 0) #define GET_EN_STAT_FINISH_INT (((REG32(ADR_STAT_CONF0)) & 0x00000002 ) >> 1) #define GET_STAT_EN_MB (((REG32(ADR_STAT_CONF0)) & 0x00000040 ) >> 6) #define GET_STAT_MB_TARGET (((REG32(ADR_STAT_CONF0)) & 0x00000080 ) >> 7) #define GET_STAT_UNEXPECT_WSID (((REG32(ADR_STAT_CONF0)) & 0x00000100 ) >> 8) #define GET_STAT_FINISH (((REG32(ADR_STAT_CONF0)) & 0x00000200 ) >> 9) #define GET_STAT_PKT_ID (((REG32(ADR_STAT_CONF0)) & 0x007f0000 ) >> 16) #define GET_STAT_FSM (((REG32(ADR_STAT_CONF0)) & 0x1f000000 ) >> 24) #define GET_STAT_ENABLE (((REG32(ADR_STAT_CONF0)) & 0x20000000 ) >> 29) #define GET_STAT_WSID (((REG32(ADR_STAT_CONF1)) & 0x00000007 ) >> 0) #define GET_STAT_FREEZE (((REG32(ADR_STAT_CONF1)) & 0x00000100 ) >> 8) #define GET_STAT_CLR (((REG32(ADR_STAT_CONF1)) & 0x00000200 ) >> 9) #define GET_STAT_CLR_DONE (((REG32(ADR_STAT_CONF1)) & 0x00000400 ) >> 10) #define GET_MAC_TX_PS_UNLOCK (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0x000000ff ) >> 0) #define GET_MAC_TX_PEER_PS_LOCK_EN (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0x00000100 ) >> 8) #define GET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0x00000200 ) >> 9) #define GET_MAC_TX_PS_LOCK (((REG32(ADR_MTX_PEER_PS_LOCK)) & 0xff000000 ) >> 24) #define GET_MAC_TX_PS_LOCK_STATUS (((REG32(ADR_MTX_PEER_LOCK_STATUS)) & 0x000000ff ) >> 0) #define GET_MTX_RATERPT_HWID (((REG32(ADR_MTX_RATERPT)) & 0x0000000f ) >> 0) #define GET_CTYPE_RATE_RPT (((REG32(ADR_MTX_RATERPT)) & 0x00000070 ) >> 4) #define GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE (((REG32(ADR_MTX_DBGOPT_FORCE_RATE)) & 0x000000ff ) >> 0) #define GET_MTX_DBGOPT_FORCE_TXCTRL_RATE (((REG32(ADR_MTX_DBGOPT_FORCE_RATE)) & 0x0000ff00 ) >> 8) #define GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE (((REG32(ADR_MTX_DBGOPT_FORCE_RATE)) & 0x00030000 ) >> 16) #define GET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN (((REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) & 0x00000001 ) >> 0) #define GET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN (((REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) & 0x00000004 ) >> 2) #define GET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN (((REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) & 0x00000010 ) >> 4) #define GET_RO_PHYTXIP_TIMEOUT_CNT (((REG32(ADR_MTX_DBG_PHYTXIPTIMEOUT)) & 0x0000000f ) >> 0) #define GET_DBG_PHYTXIP_TIMEOUT_RECOVERY (((REG32(ADR_MTX_DBG_PHYTXIPTIMEOUT)) & 0x00000100 ) >> 8) #define GET_DBG_MTX_IGNORE_NAV (((REG32(ADR_MTX_DBG_MORE)) & 0x00000001 ) >> 0) #define GET_RO_IFSAIR1 (((REG32(ADR_MTX_DBG_ROIFSAIR1)) & 0xffffffff ) >> 0) #define GET_RO_IFSAIR2 (((REG32(ADR_MTX_DBG_ROIFSAIR2)) & 0xffffffff ) >> 0) #define GET_MTX_BCN_PKT_ID0 (((REG32(ADR_MTX_BCN_PKT_SET0)) & 0x0000007f ) >> 0) #define GET_MTX_BCN_PKT_ID1 (((REG32(ADR_MTX_BCN_PKT_SET1)) & 0x0000007f ) >> 0) #define GET_MTX_DTIM_OFST0 (((REG32(ADR_MTX_BCN_DTIM_SET0)) & 0x000003ff ) >> 0) #define GET_MTX_DTIM_OFST1 (((REG32(ADR_MTX_BCN_DTIM_SET1)) & 0x000003ff ) >> 0) #define GET_MTX_DTIM_NUM (((REG32(ADR_MTX_BCN_DTIM_CONFG)) & 0x000000ff ) >> 0) #define GET_MTX_INT_DTIM_NUM (((REG32(ADR_MTX_BCN_DTIM_CONFG)) & 0x0000ff00 ) >> 8) #define GET_MTX_INT_DTIM (((REG32(ADR_MTX_BCN_DTIM_INT_W1CLR)) & 0x00000001 ) >> 0) #define GET_MTX_INT_BCN (((REG32(ADR_MTX_BCN_INT_STS)) & 0x00000001 ) >> 0) #define GET_MTX_EN_INT_BCN (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000002 ) >> 1) #define GET_MTX_EN_INT_DTIM (((REG32(ADR_MTX_BCN_EN_INT)) & 0x00000008 ) >> 3) #define GET_MTX_BCN_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000001 ) >> 0) #define GET_MTX_TIME_STAMP_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000002 ) >> 1) #define GET_MTX_DTIM_CNT_AUTO_FILL (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000008 ) >> 3) #define GET_MTX_TSF_TIMER_EN (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00000020 ) >> 5) #define GET_TXQ5_DTIM_BEACON_BURST_MNG (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00010000 ) >> 16) #define GET_MTX_BCN_AUTO_SEQ_NO (((REG32(ADR_MTX_BCN_EN_MISC)) & 0x00020000 ) >> 17) #define GET_MTX_BCN_PKTID_CH_LOCK (((REG32(ADR_MTX_BCN_MISC)) & 0x00000001 ) >> 0) #define GET_MTX_BCN_CFG_VLD (((REG32(ADR_MTX_BCN_MISC)) & 0x00000006 ) >> 1) #define GET_MTX_AUTO_BCN_ONGOING (((REG32(ADR_MTX_BCN_MISC)) & 0x00000008 ) >> 3) #define GET_MTX_BCN_TIMER (((REG32(ADR_MTX_BCN_MISC)) & 0xffff0000 ) >> 16) #define GET_MTX_BCN_PERIOD (((REG32(ADR_MTX_BCN_PRD)) & 0x0000ffff ) >> 0) #define GET_MTX_BCN_TSF_L (((REG32(ADR_MTX_BCN_TSF_L)) & 0xffffffff ) >> 0) #define GET_MTX_BCN_TSF_U (((REG32(ADR_MTX_BCN_TSF_U)) & 0xffffffff ) >> 0) #define GET_TOUT_B (((REG32(ADR_MTX_TIME_TOUT)) & 0x000000ff ) >> 0) #define GET_TOUT_AGN (((REG32(ADR_MTX_TIME_TOUT)) & 0x0000ff00 ) >> 8) #define GET_EIFS_IN_SLOT (((REG32(ADR_MTX_TIME_TOUT)) & 0x003f0000 ) >> 16) #define GET_TXSIFS_SUB_MIN (((REG32(ADR_MTX_TIME_IFS)) & 0x0000000f ) >> 0) #define GET_TXSIFS_SUB_MAX (((REG32(ADR_MTX_TIME_IFS)) & 0x000000f0 ) >> 4) #define GET_SLOTTIME (((REG32(ADR_MTX_TIME_IFS)) & 0x00001f00 ) >> 8) #define GET_SIFS (((REG32(ADR_MTX_TIME_IFS)) & 0x001f0000 ) >> 16) #define GET_NAVCS_PHYCS_FALL_OFFSET_STEP (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x0000007f ) >> 0) #define GET_TX_IP_FALL_OFFSET_STEP (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x00007f00 ) >> 8) #define GET_PHYTXSTART_NCYCLE (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x007f0000 ) >> 16) #define GET_SIGEXT (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x0f000000 ) >> 24) #define GET_MAC_CLK_80M (((REG32(ADR_MTX_TIME_FINETUNE)) & 0x10000000 ) >> 28) #define GET_RO_MTX_TX_EN (((REG32(ADR_MTX_STATUS)) & 0x00100000 ) >> 20) #define GET_RO_MAC_TX_FIFO_WINC (((REG32(ADR_MTX_STATUS)) & 0x00200000 ) >> 21) #define GET_RO_MAC_TX_FIFO_WFULL_MX (((REG32(ADR_MTX_STATUS)) & 0x00400000 ) >> 22) #define GET_RO_MAC_TX_FIFO_WEMPTY (((REG32(ADR_MTX_STATUS)) & 0x00800000 ) >> 23) #define GET_TOMAC_TX_IP (((REG32(ADR_MTX_STATUS)) & 0x01000000 ) >> 24) #define GET_TOMAC_ED_CCA_PRIMARY_MX (((REG32(ADR_MTX_STATUS)) & 0x10000000 ) >> 28) #define GET_TOMAC_ED_CCA_SECONDARY_MX (((REG32(ADR_MTX_STATUS)) & 0x20000000 ) >> 29) #define GET_TOMAC_CS_CCA_MX (((REG32(ADR_MTX_STATUS)) & 0x40000000 ) >> 30) #define GET_BT_BUSY (((REG32(ADR_MTX_STATUS)) & 0x80000000 ) >> 31) #define GET_MTX_DBG_PHYRX_IFS_DELTATIME (((REG32(ADR_MTX_PHYRXIFS_DBG)) & 0x000007ff ) >> 0) #define GET_RO_IFSST0 (((REG32(ADR_MTX_DBG_IFSAIRRO0)) & 0xffffffff ) >> 0) #define GET_RO_IFSST1 (((REG32(ADR_MTX_DBG_IFSAIRRO1)) & 0xffffffff ) >> 0) #define GET_RO_IFSST2 (((REG32(ADR_MTX_DBG_IFSAIRRO2)) & 0xffffffff ) >> 0) #define GET_RO_IFSST3 (((REG32(ADR_MTX_DBG_IFSAIRRO3)) & 0xffffffff ) >> 0) #define GET_MTX_NAV (((REG32(ADR_MTX_NAV)) & 0x0000ffff ) >> 0) #define GET_RO_MTX_BASE1 (((REG32(ADR_MTX_DBG_RO_BASE1)) & 0xffffffff ) >> 0) #define GET_RO_MTX_BASE2 (((REG32(ADR_MTX_DBG_RO_BASE2)) & 0xffffffff ) >> 0) #define GET_RO_MTX_BASE3 (((REG32(ADR_MTX_DBG_RO_BASE3)) & 0xffffffff ) >> 0) #define GET_TXQ0_MTX_Q_RND_MODE (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0) #define GET_TXQ0_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) #define GET_TXQ0_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ0_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31) #define GET_TXQ0_MTX_Q_AIFSN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) #define GET_TXQ0_MTX_Q_ECWMIN (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) #define GET_TXQ0_MTX_Q_ECWMAX (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) #define GET_TXQ0_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ0_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) #define GET_TXQ0_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ0_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0) #define GET_TXQ0_RO_FSM_TXQ (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x00000003 ) >> 0) #define GET_TXQ0_RO_TRY_CNT (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4) #define GET_TXQ0_RO_RATESET_IDX (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x00000300 ) >> 8) #define GET_TXQ0_RO_AIFS_CNT (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12) #define GET_TXQ0_RO_BKF_CNT (((REG32(ADR_TXQ0_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16) #define GET_TXQ0_RO_PKTID (((REG32(ADR_TXQ0_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0) #define GET_TXQ1_MTX_Q_RND_MODE (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0) #define GET_TXQ1_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) #define GET_TXQ1_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ1_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31) #define GET_TXQ1_MTX_Q_AIFSN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) #define GET_TXQ1_MTX_Q_ECWMIN (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) #define GET_TXQ1_MTX_Q_ECWMAX (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) #define GET_TXQ1_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ1_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) #define GET_TXQ1_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ1_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0) #define GET_TXQ1_RO_FSM_TXQ (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x00000003 ) >> 0) #define GET_TXQ1_RO_TRY_CNT (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4) #define GET_TXQ1_RO_RATESET_IDX (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x00000300 ) >> 8) #define GET_TXQ1_RO_AIFS_CNT (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12) #define GET_TXQ1_RO_BKF_CNT (((REG32(ADR_TXQ1_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16) #define GET_TXQ1_RO_PKTID (((REG32(ADR_TXQ1_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0) #define GET_TXQ2_MTX_Q_RND_MODE (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0) #define GET_TXQ2_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) #define GET_TXQ2_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ2_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31) #define GET_TXQ2_MTX_Q_AIFSN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) #define GET_TXQ2_MTX_Q_ECWMIN (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) #define GET_TXQ2_MTX_Q_ECWMAX (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) #define GET_TXQ2_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ2_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) #define GET_TXQ2_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ2_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0) #define GET_TXQ2_RO_FSM_TXQ (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x00000003 ) >> 0) #define GET_TXQ2_RO_TRY_CNT (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4) #define GET_TXQ2_RO_RATESET_IDX (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x00000300 ) >> 8) #define GET_TXQ2_RO_AIFS_CNT (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12) #define GET_TXQ2_RO_BKF_CNT (((REG32(ADR_TXQ2_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16) #define GET_TXQ2_RO_PKTID (((REG32(ADR_TXQ2_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0) #define GET_TXQ3_MTX_Q_RND_MODE (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0) #define GET_TXQ3_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) #define GET_TXQ3_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ3_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31) #define GET_TXQ3_MTX_Q_AIFSN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) #define GET_TXQ3_MTX_Q_ECWMIN (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) #define GET_TXQ3_MTX_Q_ECWMAX (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) #define GET_TXQ3_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ3_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) #define GET_TXQ3_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ3_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0) #define GET_TXQ3_RO_FSM_TXQ (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x00000003 ) >> 0) #define GET_TXQ3_RO_TRY_CNT (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4) #define GET_TXQ3_RO_RATESET_IDX (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x00000300 ) >> 8) #define GET_TXQ3_RO_AIFS_CNT (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12) #define GET_TXQ3_RO_BKF_CNT (((REG32(ADR_TXQ3_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16) #define GET_TXQ3_RO_PKTID (((REG32(ADR_TXQ3_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0) #define GET_TXQ4_MTX_Q_RND_MODE (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0) #define GET_TXQ4_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) #define GET_TXQ4_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ4_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31) #define GET_TXQ4_MTX_Q_AIFSN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) #define GET_TXQ4_MTX_Q_ECWMIN (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) #define GET_TXQ4_MTX_Q_ECWMAX (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) #define GET_TXQ4_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ4_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) #define GET_TXQ4_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ4_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0) #define GET_TXQ4_RO_FSM_TXQ (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x00000003 ) >> 0) #define GET_TXQ4_RO_TRY_CNT (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4) #define GET_TXQ4_RO_RATESET_IDX (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x00000300 ) >> 8) #define GET_TXQ4_RO_AIFS_CNT (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12) #define GET_TXQ4_RO_BKF_CNT (((REG32(ADR_TXQ4_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16) #define GET_TXQ4_RO_PKTID (((REG32(ADR_TXQ4_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0) #define GET_TXQ5_MTX_Q_RND_MODE (((REG32(ADR_TXQ5_MTX_Q_MISC_EN)) & 0x00000007 ) >> 0) #define GET_TXQ5_MTX_Q_MB_NO_RLS (((REG32(ADR_TXQ5_MTX_Q_MISC_EN)) & 0x00000010 ) >> 4) #define GET_TXQ5_Q_NULLDATAFRAME_GEN_EN (((REG32(ADR_TXQ5_MTX_Q_MISC_EN)) & 0x80000000 ) >> 31) #define GET_TXQ5_MTX_Q_AIFSN (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0x0000000f ) >> 0) #define GET_TXQ5_MTX_Q_ECWMIN (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0x00000f00 ) >> 8) #define GET_TXQ5_MTX_Q_ECWMAX (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0x0000f000 ) >> 12) #define GET_TXQ5_MTX_Q_TXOP_LIMIT (((REG32(ADR_TXQ5_MTX_Q_AIFSN)) & 0xffff0000 ) >> 16) #define GET_TXQ5_MTX_Q_BKF_CNT_FIX (((REG32(ADR_TXQ5_MTX_Q_BKF_CNT_DBG)) & 0x0000ffff ) >> 0) #define GET_TXQ5_RO_FSM_TXQ (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x00000003 ) >> 0) #define GET_TXQ5_RO_TRY_CNT (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x000000f0 ) >> 4) #define GET_TXQ5_RO_RATESET_IDX (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x00000300 ) >> 8) #define GET_TXQ5_RO_AIFS_CNT (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0x0000f000 ) >> 12) #define GET_TXQ5_RO_BKF_CNT (((REG32(ADR_TXQ5_MTX_Q_HWDBG)) & 0xffff0000 ) >> 16) #define GET_TXQ5_RO_PKTID (((REG32(ADR_TXQ5_MTX_Q_HWDBG2)) & 0x0000007f ) >> 0) #define GET_MTX_RESPFRM_RATE_EXCEPTION (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_00 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_00)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_01 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_01)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_02 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_02)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_03 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_03)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_11 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_11)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_12 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_12)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_13 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_13)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_90_B0 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_90_B0)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_91_B1 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_91_B1)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_92_B2 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_92_B2)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_93_B3 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_93_B3)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_94_B4 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_94_B4)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_95_B5 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_95_B5)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_96_B6 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_96_B6)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_97_B7 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_97_B7)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C0_E0 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C0_E0)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C1_E1 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C1_E1)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C2_E2 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C2_E2)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C3_E3 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C3_E3)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C4_E4 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C4_E4)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C5_E5 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C5_E5)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C6_E6 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C6_E6)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_C7_E7 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_C7_E7)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D0_F0 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D0_F0)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D1_F1 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D1_F1)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D2_F2 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D2_F2)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D3_F3 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D3_F3)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D4_F4 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D4_F4)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D5_F5 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D5_F5)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D6_F6 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D6_F6)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D7_F7 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D7_F7)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D8_F8 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D8_F8)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_D9_F9 (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_D9_F9)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_DA_FA (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DA_FA)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_DB_FB (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DB_FB)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_DC_FC (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DC_FC)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_DD_FD (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DD_FD)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_DE_FE (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DE_FE)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_RATE_DF_FF (((REG32(ADR_MTX_RESPFRM_RATE_TABLE_DF_FF)) & 0x0000ffff ) >> 0) #define GET_MTX_RESPFRM_INFO_EXCEPTION (((REG32(ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_00 (((REG32(ADR_MTX_RESPFRM_INFO_00)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_01 (((REG32(ADR_MTX_RESPFRM_INFO_01)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_02 (((REG32(ADR_MTX_RESPFRM_INFO_02)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_03 (((REG32(ADR_MTX_RESPFRM_INFO_03)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_11 (((REG32(ADR_MTX_RESPFRM_INFO_11)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_12 (((REG32(ADR_MTX_RESPFRM_INFO_12)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_13 (((REG32(ADR_MTX_RESPFRM_INFO_13)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_90_B0 (((REG32(ADR_MTX_RESPFRM_INFO_90_B0)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_91_B1 (((REG32(ADR_MTX_RESPFRM_INFO_91_B1)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_92_B2 (((REG32(ADR_MTX_RESPFRM_INFO_92_B2)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_93_B3 (((REG32(ADR_MTX_RESPFRM_INFO_93_B3)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_94_B4 (((REG32(ADR_MTX_RESPFRM_INFO_94_B4)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_95_B5 (((REG32(ADR_MTX_RESPFRM_INFO_95_B5)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_96_B6 (((REG32(ADR_MTX_RESPFRM_INFO_96_B6)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_97_B7 (((REG32(ADR_MTX_RESPFRM_INFO_97_B7)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C0 (((REG32(ADR_MTX_RESPFRM_INFO_C0)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C1 (((REG32(ADR_MTX_RESPFRM_INFO_C1)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C2 (((REG32(ADR_MTX_RESPFRM_INFO_C2)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C3 (((REG32(ADR_MTX_RESPFRM_INFO_C3)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C4 (((REG32(ADR_MTX_RESPFRM_INFO_C4)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C5 (((REG32(ADR_MTX_RESPFRM_INFO_C5)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C6 (((REG32(ADR_MTX_RESPFRM_INFO_C6)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_C7 (((REG32(ADR_MTX_RESPFRM_INFO_C7)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D0 (((REG32(ADR_MTX_RESPFRM_INFO_D0)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D1 (((REG32(ADR_MTX_RESPFRM_INFO_D1)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D2 (((REG32(ADR_MTX_RESPFRM_INFO_D2)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D3 (((REG32(ADR_MTX_RESPFRM_INFO_D3)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D4 (((REG32(ADR_MTX_RESPFRM_INFO_D4)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D5 (((REG32(ADR_MTX_RESPFRM_INFO_D5)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D6 (((REG32(ADR_MTX_RESPFRM_INFO_D6)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D7 (((REG32(ADR_MTX_RESPFRM_INFO_D7)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D8 (((REG32(ADR_MTX_RESPFRM_INFO_D8)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_D9 (((REG32(ADR_MTX_RESPFRM_INFO_D9)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_DA (((REG32(ADR_MTX_RESPFRM_INFO_DA)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_DB (((REG32(ADR_MTX_RESPFRM_INFO_DB)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_DC (((REG32(ADR_MTX_RESPFRM_INFO_DC)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_DD (((REG32(ADR_MTX_RESPFRM_INFO_DD)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_DE (((REG32(ADR_MTX_RESPFRM_INFO_DE)) & 0x001fffff ) >> 0) #define GET_MTX_RESPFRM_INFO_DF (((REG32(ADR_MTX_RESPFRM_INFO_DF)) & 0x001fffff ) >> 0) #define GET_VALID0 (((REG32(ADR_WSID0)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN0 (((REG32(ADR_WSID0)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE0 (((REG32(ADR_WSID0)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE0 (((REG32(ADR_WSID0)) & 0x00000030 ) >> 4) #define GET_PEER_MAC0_31_0 (((REG32(ADR_PEER_MAC0_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC0_47_32 (((REG32(ADR_PEER_MAC0_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_0_0 (((REG32(ADR_TX_ACK_POLICY_0_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_0 (((REG32(ADR_TX_SEQ_CTRL_0_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_1 (((REG32(ADR_TX_ACK_POLICY_0_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_1 (((REG32(ADR_TX_SEQ_CTRL_0_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_2 (((REG32(ADR_TX_ACK_POLICY_0_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_2 (((REG32(ADR_TX_SEQ_CTRL_0_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_3 (((REG32(ADR_TX_ACK_POLICY_0_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_3 (((REG32(ADR_TX_SEQ_CTRL_0_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_4 (((REG32(ADR_TX_ACK_POLICY_0_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_4 (((REG32(ADR_TX_SEQ_CTRL_0_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_5 (((REG32(ADR_TX_ACK_POLICY_0_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_5 (((REG32(ADR_TX_SEQ_CTRL_0_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_6 (((REG32(ADR_TX_ACK_POLICY_0_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_6 (((REG32(ADR_TX_SEQ_CTRL_0_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_0_7 (((REG32(ADR_TX_ACK_POLICY_0_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_0_7 (((REG32(ADR_TX_SEQ_CTRL_0_7)) & 0x00000fff ) >> 0) #define GET_VALID1 (((REG32(ADR_WSID1)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN1 (((REG32(ADR_WSID1)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE1 (((REG32(ADR_WSID1)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE1 (((REG32(ADR_WSID1)) & 0x00000030 ) >> 4) #define GET_PEER_MAC1_31_0 (((REG32(ADR_PEER_MAC1_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC1_47_32 (((REG32(ADR_PEER_MAC1_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_1_0 (((REG32(ADR_TX_ACK_POLICY_1_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_0 (((REG32(ADR_TX_SEQ_CTRL_1_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_1 (((REG32(ADR_TX_ACK_POLICY_1_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_1 (((REG32(ADR_TX_SEQ_CTRL_1_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_2 (((REG32(ADR_TX_ACK_POLICY_1_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_2 (((REG32(ADR_TX_SEQ_CTRL_1_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_3 (((REG32(ADR_TX_ACK_POLICY_1_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_3 (((REG32(ADR_TX_SEQ_CTRL_1_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_4 (((REG32(ADR_TX_ACK_POLICY_1_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_4 (((REG32(ADR_TX_SEQ_CTRL_1_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_5 (((REG32(ADR_TX_ACK_POLICY_1_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_5 (((REG32(ADR_TX_SEQ_CTRL_1_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_6 (((REG32(ADR_TX_ACK_POLICY_1_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_6 (((REG32(ADR_TX_SEQ_CTRL_1_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_1_7 (((REG32(ADR_TX_ACK_POLICY_1_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_1_7 (((REG32(ADR_TX_SEQ_CTRL_1_7)) & 0x00000fff ) >> 0) #define GET_CH1_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000003 ) >> 0) #define GET_CH2_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00000300 ) >> 8) #define GET_CH3_PRI (((REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) & 0x00030000 ) >> 16) #define GET_RG_MAC_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000001 ) >> 0) #define GET_RG_MAC_M2M (((REG32(ADR_MAC_MODE)) & 0x00000002 ) >> 1) #define GET_RG_PHY_LPBK (((REG32(ADR_MAC_MODE)) & 0x00000004 ) >> 2) #define GET_RG_LPBK_RX_EN (((REG32(ADR_MAC_MODE)) & 0x00000008 ) >> 3) #define GET_EXT_MAC_MODE (((REG32(ADR_MAC_MODE)) & 0x00000010 ) >> 4) #define GET_EXT_PHY_MODE (((REG32(ADR_MAC_MODE)) & 0x00000020 ) >> 5) #define GET_HCI_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000001 ) >> 0) #define GET_CO_PROC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000002 ) >> 1) #define GET_MTX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000004 ) >> 2) #define GET_MTX_MISC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000008 ) >> 3) #define GET_MTX_QUE_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000010 ) >> 4) #define GET_MTX_CHST_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000020 ) >> 5) #define GET_MTX_BCN_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000040 ) >> 6) #define GET_MRX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000080 ) >> 7) #define GET_AMPDU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000100 ) >> 8) #define GET_MMU_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000200 ) >> 9) #define GET_ID_MNG_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00000800 ) >> 11) #define GET_MBOX_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00001000 ) >> 12) #define GET_SCRT_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00002000 ) >> 13) #define GET_MIC_SW_RST (((REG32(ADR_ALL_SOFTWARE_RESET)) & 0x00004000 ) >> 14) #define GET_CO_PROC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000002 ) >> 1) #define GET_MTX_MISC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000008 ) >> 3) #define GET_MTX_QUE_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000010 ) >> 4) #define GET_MTX_CHST_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000020 ) >> 5) #define GET_MTX_BCN_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000040 ) >> 6) #define GET_MRX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000080 ) >> 7) #define GET_AMPDU_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00000100 ) >> 8) #define GET_ID_MNG_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00004000 ) >> 14) #define GET_MBOX_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00008000 ) >> 15) #define GET_SCRT_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00010000 ) >> 16) #define GET_MIC_ENG_RST (((REG32(ADR_ENG_SOFTWARE_RESET)) & 0x00020000 ) >> 17) #define GET_CO_PROC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000002 ) >> 1) #define GET_MTX_MISC_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000008 ) >> 3) #define GET_MTX_QUE0_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000010 ) >> 4) #define GET_MTX_QUE1_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000020 ) >> 5) #define GET_MTX_QUE2_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000040 ) >> 6) #define GET_MTX_QUE3_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000080 ) >> 7) #define GET_MTX_QUE4_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000100 ) >> 8) #define GET_MTX_QUE5_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000200 ) >> 9) #define GET_MRX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000400 ) >> 10) #define GET_AMPDU_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00000800 ) >> 11) #define GET_SCRT_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00002000 ) >> 13) #define GET_ID_MNG_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00004000 ) >> 14) #define GET_MBOX_CSR_RST (((REG32(ADR_CSR_SOFTWARE_RESET)) & 0x00008000 ) >> 15) #define GET_HCI_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000001 ) >> 0) #define GET_CO_PROC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000002 ) >> 1) #define GET_MTX_MISC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000008 ) >> 3) #define GET_MTX_QUE_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000010 ) >> 4) #define GET_MRX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000020 ) >> 5) #define GET_AMPDU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000040 ) >> 6) #define GET_MMU_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000080 ) >> 7) #define GET_ID_MNG_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000200 ) >> 9) #define GET_MBOX_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000400 ) >> 10) #define GET_SCRT_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00000800 ) >> 11) #define GET_MIC_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00001000 ) >> 12) #define GET_MIB_CLK_EN (((REG32(ADR_MAC_CLOCK_ENABLE)) & 0x00002000 ) >> 13) #define GET_HCI_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000001 ) >> 0) #define GET_CO_PROC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000002 ) >> 1) #define GET_MTX_MISC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000008 ) >> 3) #define GET_MTX_QUE_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000010 ) >> 4) #define GET_MRX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000020 ) >> 5) #define GET_AMPDU_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00000040 ) >> 6) #define GET_ID_MNG_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00001000 ) >> 12) #define GET_MBOX_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00002000 ) >> 13) #define GET_SCRT_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00004000 ) >> 14) #define GET_MIC_ENG_CLK_EN (((REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) & 0x00008000 ) >> 15) #define GET_CO_PROC_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000002 ) >> 1) #define GET_MRX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000400 ) >> 10) #define GET_AMPDU_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00000800 ) >> 11) #define GET_SCRT_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00002000 ) >> 13) #define GET_ID_MNG_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00004000 ) >> 14) #define GET_MBOX_CSR_CLK_EN (((REG32(ADR_MAC_CSR_CLOCK_ENABLE)) & 0x00008000 ) >> 15) #define GET_OP_MODE (((REG32(ADR_GLBLE_SET)) & 0x00000003 ) >> 0) #define GET_HT_MODE (((REG32(ADR_GLBLE_SET)) & 0x0000000c ) >> 2) #define GET_QOS_EN (((REG32(ADR_GLBLE_SET)) & 0x00000010 ) >> 4) #define GET_PB_OFFSET (((REG32(ADR_GLBLE_SET)) & 0x0000ff00 ) >> 8) #define GET_SNIFFER_MODE (((REG32(ADR_GLBLE_SET)) & 0x00010000 ) >> 16) #define GET_DUP_FLT (((REG32(ADR_GLBLE_SET)) & 0x00020000 ) >> 17) #define GET_TX_PKT_RSVD (((REG32(ADR_GLBLE_SET)) & 0x001c0000 ) >> 18) #define GET_AMPDU_SNIFFER (((REG32(ADR_GLBLE_SET)) & 0x00200000 ) >> 21) #define GET_CCMP_H_SEL (((REG32(ADR_GLBLE_SET)) & 0x00400000 ) >> 22) #define GET_LUT_SEL_V2 (((REG32(ADR_GLBLE_SET)) & 0x00800000 ) >> 23) #define GET_REASON_TRAP0 (((REG32(ADR_REASON_TRAP0)) & 0xffffffff ) >> 0) #define GET_REASON_TRAP1 (((REG32(ADR_REASON_TRAP1)) & 0xffffffff ) >> 0) #define GET_BSSID_31_0 (((REG32(ADR_BSSID_0)) & 0xffffffff ) >> 0) #define GET_BSSID_47_32 (((REG32(ADR_BSSID_1)) & 0x0000ffff ) >> 0) #define GET_STA_MAC_31_0 (((REG32(ADR_STA_MAC_0)) & 0xffffffff ) >> 0) #define GET_STA_MAC_47_32 (((REG32(ADR_STA_MAC_1)) & 0x0000ffff ) >> 0) #define GET_PAIR_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000007 ) >> 0) #define GET_GRP_SCRT (((REG32(ADR_SCRT_SET)) & 0x00000038 ) >> 3) #define GET_SCRT_PKT_ID (((REG32(ADR_SCRT_SET)) & 0x00001fc0 ) >> 6) #define GET_SCRT_RPLY_IGNORE (((REG32(ADR_SCRT_SET)) & 0x00010000 ) >> 16) #define GET_SCRT_STATE (((REG32(ADR_SCRT_STATE)) & 0x0000000f ) >> 0) #define GET_BSSID1_31_0 (((REG32(ADR_BSSID1_0)) & 0xffffffff ) >> 0) #define GET_BSSID1_47_32 (((REG32(ADR_BSSID1_1)) & 0x0000ffff ) >> 0) #define GET_STA_MAC1_31_0 (((REG32(ADR_STA_MAC1_0)) & 0xffffffff ) >> 0) #define GET_STA_MAC1_47_32 (((REG32(ADR_STA_MAC1_1)) & 0x0000ffff ) >> 0) #define GET_OP_MODE1 (((REG32(ADR_OP_MODE1)) & 0x00000003 ) >> 0) #define GET_COEXIST_EN (((REG32(ADR_BTCX0)) & 0x00000001 ) >> 0) #define GET_WIRE_MODE (((REG32(ADR_BTCX0)) & 0x0000000e ) >> 1) #define GET_WL_RX_PRI (((REG32(ADR_BTCX0)) & 0x00000010 ) >> 4) #define GET_WL_TX_PRI (((REG32(ADR_BTCX0)) & 0x00000020 ) >> 5) #define GET_GURAN_USE_EN (((REG32(ADR_BTCX0)) & 0x00000100 ) >> 8) #define GET_GURAN_USE_CTRL (((REG32(ADR_BTCX0)) & 0x00000200 ) >> 9) #define GET_BEACON_TIMEOUT_EN (((REG32(ADR_BTCX0)) & 0x00000400 ) >> 10) #define GET_WLAN_ACT_POL (((REG32(ADR_BTCX0)) & 0x00000800 ) >> 11) #define GET_DUAL_ANT_EN (((REG32(ADR_BTCX0)) & 0x00001000 ) >> 12) #define GET_TRSW_PHY_POL (((REG32(ADR_BTCX0)) & 0x00010000 ) >> 16) #define GET_WIFI_TX_SW_POL (((REG32(ADR_BTCX0)) & 0x00020000 ) >> 17) #define GET_WIFI_RX_SW_POL (((REG32(ADR_BTCX0)) & 0x00040000 ) >> 18) #define GET_BT_SW_POL (((REG32(ADR_BTCX0)) & 0x00080000 ) >> 19) #define GET_BT_PRI_SMP_TIME (((REG32(ADR_BTCX1)) & 0x000000ff ) >> 0) #define GET_BT_STA_SMP_TIME (((REG32(ADR_BTCX1)) & 0x0000ff00 ) >> 8) #define GET_BEACON_TIMEOUT (((REG32(ADR_BTCX1)) & 0x00ff0000 ) >> 16) #define GET_WLAN_REMAIN_TIME (((REG32(ADR_BTCX1)) & 0xff000000 ) >> 24) #define GET_SW_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000001 ) >> 0) #define GET_SW_WL_TX (((REG32(ADR_SWITCH_CTL)) & 0x00000002 ) >> 1) #define GET_SW_WL_RX (((REG32(ADR_SWITCH_CTL)) & 0x00000004 ) >> 2) #define GET_SW_BT_TRX (((REG32(ADR_SWITCH_CTL)) & 0x00000008 ) >> 3) #define GET_BT_TXBAR_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000010 ) >> 4) #define GET_BT_TXBAR_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000020 ) >> 5) #define GET_BT_BUSY_MANUAL_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000100 ) >> 8) #define GET_BT_BUSY_SET (((REG32(ADR_SWITCH_CTL)) & 0x00000200 ) >> 9) #define GET_SWITCH_2WIRE_EN (((REG32(ADR_SWITCH_CTL)) & 0x00000400 ) >> 10) #define GET_RANDOM_SEED3 (((REG32(ADR_RANDOM_CTL)) & 0x000000ff ) >> 0) #define GET_RANDOM_SEED2 (((REG32(ADR_RANDOM_CTL)) & 0x0000ff00 ) >> 8) #define GET_RANDOM_SEED1 (((REG32(ADR_RANDOM_CTL)) & 0x00ff0000 ) >> 16) #define GET_BT_TRX_SMP_TIME (((REG32(ADR_RANDOM_CTL)) & 0xff000000 ) >> 24) #define GET_BTCX_INT_MASK (((REG32(ADR_BTCX_MISC_CTL)) & 0x0000001f ) >> 0) #define GET_BTCX_INTR (((REG32(ADR_BTCX_MISC_CTL)) & 0x00000020 ) >> 5) #define GET_AUTO_REMAIN (((REG32(ADR_BTCX_MISC_CTL)) & 0x00000040 ) >> 6) #define GET_PREDE_BT_TX (((REG32(ADR_BTCX_MISC_CTL)) & 0x00000080 ) >> 7) #define GET_G0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000004 ) >> 2) #define GET_G0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000008 ) >> 3) #define GET_G1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000010 ) >> 4) #define GET_G1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000020 ) >> 5) #define GET_Q0_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000040 ) >> 6) #define GET_Q0_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000080 ) >> 7) #define GET_Q1_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000100 ) >> 8) #define GET_Q1_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000200 ) >> 9) #define GET_Q2_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00000400 ) >> 10) #define GET_Q2_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00000800 ) >> 11) #define GET_Q3_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00001000 ) >> 12) #define GET_Q3_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00002000 ) >> 13) #define GET_SCRT_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00004000 ) >> 14) #define GET_SCRT_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00008000 ) >> 15) #define GET_MISC_PKT_CLS_MIB_EN (((REG32(ADR_MIB_EN)) & 0x00010000 ) >> 16) #define GET_MISC_PKT_CLS_ONGOING (((REG32(ADR_MIB_EN)) & 0x00020000 ) >> 17) #define GET_MTX_WSID0_SUCC (((REG32(ADR_MTX_WSID0_SUCC)) & 0x0000ffff ) >> 0) #define GET_MTX_WSID0_FRM (((REG32(ADR_MTX_WSID0_FRM)) & 0x0000ffff ) >> 0) #define GET_MTX_WSID0_RETRY (((REG32(ADR_MTX_WSID0_RETRY)) & 0x0000ffff ) >> 0) #define GET_MTX_WSID0_TOTAL (((REG32(ADR_MTX_WSID0_TOTAL)) & 0x0000ffff ) >> 0) #define GET_MTX_GRP (((REG32(ADR_MTX_GROUP)) & 0x000fffff ) >> 0) #define GET_MTX_FAIL (((REG32(ADR_MTX_FAIL)) & 0x0000ffff ) >> 0) #define GET_MTX_RETRY (((REG32(ADR_MTX_RETRY)) & 0x000fffff ) >> 0) #define GET_MTX_MULTI_RETRY (((REG32(ADR_MTX_MULTI_RETRY)) & 0x000fffff ) >> 0) #define GET_MTX_RTS_SUCC (((REG32(ADR_MTX_RTS_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_MTX_RTS_FAIL (((REG32(ADR_MTX_RTS_FAIL)) & 0x0000ffff ) >> 0) #define GET_MTX_ACK_FAIL (((REG32(ADR_MTX_ACK_FAIL)) & 0x0000ffff ) >> 0) #define GET_MTX_FRM (((REG32(ADR_MTX_FRM)) & 0x000fffff ) >> 0) #define GET_MTX_ACK_TX (((REG32(ADR_MTX_ACK_TX)) & 0x0000ffff ) >> 0) #define GET_MTX_CTS_TX (((REG32(ADR_MTX_CTS_TX)) & 0x0000ffff ) >> 0) #define GET_MRX_DUP (((REG32(ADR_MRX_DUP_FRM)) & 0x0000ffff ) >> 0) #define GET_MRX_FRG (((REG32(ADR_MRX_FRG_FRM)) & 0x000fffff ) >> 0) #define GET_MRX_GRP (((REG32(ADR_MRX_GROUP_FRM)) & 0x000fffff ) >> 0) #define GET_MRX_FCS_ERR (((REG32(ADR_MRX_FCS_ERR)) & 0x0000ffff ) >> 0) #define GET_MRX_FCS_SUC (((REG32(ADR_MRX_FCS_SUCC)) & 0x0000ffff ) >> 0) #define GET_MRX_MISS (((REG32(ADR_MRX_MISS)) & 0x0000ffff ) >> 0) #define GET_MRX_ALC_FAIL (((REG32(ADR_MRX_ALC_FAIL)) & 0x0000ffff ) >> 0) #define GET_MRX_DAT_NTF (((REG32(ADR_MRX_DAT_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_RTS_NTF (((REG32(ADR_MRX_RTS_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_CTS_NTF (((REG32(ADR_MRX_CTS_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_ACK_NTF (((REG32(ADR_MRX_ACK_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_BA_NTF (((REG32(ADR_MRX_BA_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_DATA_NTF (((REG32(ADR_MRX_DATA_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_MNG_NTF (((REG32(ADR_MRX_MNG_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_DAT_CRC_NTF (((REG32(ADR_MRX_DAT_CRC_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_BAR_NTF (((REG32(ADR_MRX_BAR_NTF)) & 0x0000ffff ) >> 0) #define GET_MRX_MB_MISS (((REG32(ADR_MRX_MB_MISS)) & 0x0000ffff ) >> 0) #define GET_MRX_NIDLE_MISS (((REG32(ADR_MRX_NIDLE_MISS)) & 0x0000ffff ) >> 0) #define GET_MRX_CSR_NTF (((REG32(ADR_MRX_CSR_NTF)) & 0x0000ffff ) >> 0) #define GET_DBG_Q0_SUCC (((REG32(ADR_DBG_Q0_FRM_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q0_FAIL (((REG32(ADR_DBG_Q0_FRM_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q0_ACK_SUCC (((REG32(ADR_DBG_Q0_ACK_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q0_ACK_FAIL (((REG32(ADR_DBG_Q0_ACK_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q1_SUCC (((REG32(ADR_DBG_Q1_FRM_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q1_FAIL (((REG32(ADR_DBG_Q1_FRM_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q1_ACK_SUCC (((REG32(ADR_DBG_Q1_ACK_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q1_ACK_FAIL (((REG32(ADR_DBG_Q1_ACK_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q2_SUCC (((REG32(ADR_DBG_Q2_FRM_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q2_FAIL (((REG32(ADR_DBG_Q2_FRM_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q2_ACK_SUCC (((REG32(ADR_DBG_Q2_ACK_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q2_ACK_FAIL (((REG32(ADR_DBG_Q2_ACK_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q3_SUCC (((REG32(ADR_DBG_Q3_FRM_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q3_FAIL (((REG32(ADR_DBG_Q3_FRM_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_Q3_ACK_SUCC (((REG32(ADR_DBG_Q3_ACK_SUCCESS)) & 0x0000ffff ) >> 0) #define GET_DBG_Q3_ACK_FAIL (((REG32(ADR_DBG_Q3_ACK_FAIL)) & 0x0000ffff ) >> 0) #define GET_SCRT_TKIP_CERR (((REG32(ADR_MIB_SCRT_TKIP0)) & 0x000fffff ) >> 0) #define GET_SCRT_TKIP_MIC_ERR (((REG32(ADR_MIB_SCRT_TKIP1)) & 0x000fffff ) >> 0) #define GET_SCRT_TKIP_RPLY (((REG32(ADR_MIB_SCRT_TKIP2)) & 0x000fffff ) >> 0) #define GET_SCRT_CCMP_RPLY (((REG32(ADR_MIB_SCRT_CCMP0)) & 0x000fffff ) >> 0) #define GET_SCRT_CCMP_CERR (((REG32(ADR_MIB_SCRT_CCMP1)) & 0x000fffff ) >> 0) #define GET_DBG_LEN_CRC_FAIL (((REG32(ADR_DBG_LEN_CRC_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_LEN_ALC_FAIL (((REG32(ADR_DBG_LEN_ALC_FAIL)) & 0x0000ffff ) >> 0) #define GET_DBG_AMPDU_PASS (((REG32(ADR_DBG_AMPDU_PASS)) & 0x0000ffff ) >> 0) #define GET_DBG_AMPDU_FAIL (((REG32(ADR_DBG_AMPDU_FAIL)) & 0x0000ffff ) >> 0) #define GET_RXID_ALC_CNT_FAIL (((REG32(ADR_ID_ALC_FAIL1)) & 0x0000ffff ) >> 0) #define GET_RXID_ALC_LEN_FAIL (((REG32(ADR_ID_ALC_FAIL2)) & 0x0000ffff ) >> 0) #define GET_VALID2 (((REG32(ADR_WSID2)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN2 (((REG32(ADR_WSID2)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE2 (((REG32(ADR_WSID2)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE2 (((REG32(ADR_WSID2)) & 0x00000030 ) >> 4) #define GET_PEER_MAC2_31_0 (((REG32(ADR_PEER_MAC2_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC2_47_32 (((REG32(ADR_PEER_MAC2_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_2_0 (((REG32(ADR_TX_ACK_POLICY_2_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_0 (((REG32(ADR_TX_SEQ_CTRL_2_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_1 (((REG32(ADR_TX_ACK_POLICY_2_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_1 (((REG32(ADR_TX_SEQ_CTRL_2_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_2 (((REG32(ADR_TX_ACK_POLICY_2_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_2 (((REG32(ADR_TX_SEQ_CTRL_2_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_3 (((REG32(ADR_TX_ACK_POLICY_2_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_3 (((REG32(ADR_TX_SEQ_CTRL_2_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_4 (((REG32(ADR_TX_ACK_POLICY_2_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_4 (((REG32(ADR_TX_SEQ_CTRL_2_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_5 (((REG32(ADR_TX_ACK_POLICY_2_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_5 (((REG32(ADR_TX_SEQ_CTRL_2_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_6 (((REG32(ADR_TX_ACK_POLICY_2_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_6 (((REG32(ADR_TX_SEQ_CTRL_2_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_2_7 (((REG32(ADR_TX_ACK_POLICY_2_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_2_7 (((REG32(ADR_TX_SEQ_CTRL_2_7)) & 0x00000fff ) >> 0) #define GET_VALID3 (((REG32(ADR_WSID3)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN3 (((REG32(ADR_WSID3)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE3 (((REG32(ADR_WSID3)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE3 (((REG32(ADR_WSID3)) & 0x00000030 ) >> 4) #define GET_PEER_MAC3_31_0 (((REG32(ADR_PEER_MAC3_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC3_47_32 (((REG32(ADR_PEER_MAC3_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_3_0 (((REG32(ADR_TX_ACK_POLICY_3_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_0 (((REG32(ADR_TX_SEQ_CTRL_3_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_1 (((REG32(ADR_TX_ACK_POLICY_3_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_1 (((REG32(ADR_TX_SEQ_CTRL_3_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_2 (((REG32(ADR_TX_ACK_POLICY_3_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_2 (((REG32(ADR_TX_SEQ_CTRL_3_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_3 (((REG32(ADR_TX_ACK_POLICY_3_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_3 (((REG32(ADR_TX_SEQ_CTRL_3_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_4 (((REG32(ADR_TX_ACK_POLICY_3_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_4 (((REG32(ADR_TX_SEQ_CTRL_3_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_5 (((REG32(ADR_TX_ACK_POLICY_3_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_5 (((REG32(ADR_TX_SEQ_CTRL_3_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_6 (((REG32(ADR_TX_ACK_POLICY_3_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_6 (((REG32(ADR_TX_SEQ_CTRL_3_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_3_7 (((REG32(ADR_TX_ACK_POLICY_3_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_3_7 (((REG32(ADR_TX_SEQ_CTRL_3_7)) & 0x00000fff ) >> 0) #define GET_VALID4 (((REG32(ADR_WSID4)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN4 (((REG32(ADR_WSID4)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE4 (((REG32(ADR_WSID4)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE4 (((REG32(ADR_WSID4)) & 0x00000030 ) >> 4) #define GET_PEER_MAC4_31_0 (((REG32(ADR_PEER_MAC4_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC4_47_32 (((REG32(ADR_PEER_MAC4_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_4_0 (((REG32(ADR_TX_ACK_POLICY_4_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_0 (((REG32(ADR_TX_SEQ_CTRL_4_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_1 (((REG32(ADR_TX_ACK_POLICY_4_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_1 (((REG32(ADR_TX_SEQ_CTRL_4_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_2 (((REG32(ADR_TX_ACK_POLICY_4_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_2 (((REG32(ADR_TX_SEQ_CTRL_4_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_3 (((REG32(ADR_TX_ACK_POLICY_4_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_3 (((REG32(ADR_TX_SEQ_CTRL_4_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_4 (((REG32(ADR_TX_ACK_POLICY_4_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_4 (((REG32(ADR_TX_SEQ_CTRL_4_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_5 (((REG32(ADR_TX_ACK_POLICY_4_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_5 (((REG32(ADR_TX_SEQ_CTRL_4_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_6 (((REG32(ADR_TX_ACK_POLICY_4_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_6 (((REG32(ADR_TX_SEQ_CTRL_4_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_4_7 (((REG32(ADR_TX_ACK_POLICY_4_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_4_7 (((REG32(ADR_TX_SEQ_CTRL_4_7)) & 0x00000fff ) >> 0) #define GET_VALID5 (((REG32(ADR_WSID5)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN5 (((REG32(ADR_WSID5)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE5 (((REG32(ADR_WSID5)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE5 (((REG32(ADR_WSID5)) & 0x00000030 ) >> 4) #define GET_PEER_MAC5_31_0 (((REG32(ADR_PEER_MAC5_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC5_47_32 (((REG32(ADR_PEER_MAC5_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_5_0 (((REG32(ADR_TX_ACK_POLICY_5_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_0 (((REG32(ADR_TX_SEQ_CTRL_5_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_1 (((REG32(ADR_TX_ACK_POLICY_5_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_1 (((REG32(ADR_TX_SEQ_CTRL_5_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_2 (((REG32(ADR_TX_ACK_POLICY_5_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_2 (((REG32(ADR_TX_SEQ_CTRL_5_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_3 (((REG32(ADR_TX_ACK_POLICY_5_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_3 (((REG32(ADR_TX_SEQ_CTRL_5_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_4 (((REG32(ADR_TX_ACK_POLICY_5_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_4 (((REG32(ADR_TX_SEQ_CTRL_5_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_5 (((REG32(ADR_TX_ACK_POLICY_5_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_5 (((REG32(ADR_TX_SEQ_CTRL_5_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_6 (((REG32(ADR_TX_ACK_POLICY_5_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_6 (((REG32(ADR_TX_SEQ_CTRL_5_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_5_7 (((REG32(ADR_TX_ACK_POLICY_5_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_5_7 (((REG32(ADR_TX_SEQ_CTRL_5_7)) & 0x00000fff ) >> 0) #define GET_VALID6 (((REG32(ADR_WSID6)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN6 (((REG32(ADR_WSID6)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE6 (((REG32(ADR_WSID6)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE6 (((REG32(ADR_WSID6)) & 0x00000030 ) >> 4) #define GET_PEER_MAC6_31_0 (((REG32(ADR_PEER_MAC6_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC6_47_32 (((REG32(ADR_PEER_MAC6_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_6_0 (((REG32(ADR_TX_ACK_POLICY_6_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_0 (((REG32(ADR_TX_SEQ_CTRL_6_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_1 (((REG32(ADR_TX_ACK_POLICY_6_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_1 (((REG32(ADR_TX_SEQ_CTRL_6_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_2 (((REG32(ADR_TX_ACK_POLICY_6_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_2 (((REG32(ADR_TX_SEQ_CTRL_6_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_3 (((REG32(ADR_TX_ACK_POLICY_6_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_3 (((REG32(ADR_TX_SEQ_CTRL_6_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_4 (((REG32(ADR_TX_ACK_POLICY_6_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_4 (((REG32(ADR_TX_SEQ_CTRL_6_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_5 (((REG32(ADR_TX_ACK_POLICY_6_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_5 (((REG32(ADR_TX_SEQ_CTRL_6_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_6 (((REG32(ADR_TX_ACK_POLICY_6_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_6 (((REG32(ADR_TX_SEQ_CTRL_6_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_6_7 (((REG32(ADR_TX_ACK_POLICY_6_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_6_7 (((REG32(ADR_TX_SEQ_CTRL_6_7)) & 0x00000fff ) >> 0) #define GET_VALID7 (((REG32(ADR_WSID7)) & 0x00000001 ) >> 0) #define GET_PEER_QOS_EN7 (((REG32(ADR_WSID7)) & 0x00000002 ) >> 1) #define GET_PEER_OP_MODE7 (((REG32(ADR_WSID7)) & 0x0000000c ) >> 2) #define GET_PEER_HT_MODE7 (((REG32(ADR_WSID7)) & 0x00000030 ) >> 4) #define GET_PEER_MAC7_31_0 (((REG32(ADR_PEER_MAC7_0)) & 0xffffffff ) >> 0) #define GET_PEER_MAC7_47_32 (((REG32(ADR_PEER_MAC7_1)) & 0x0000ffff ) >> 0) #define GET_TX_ACK_POLICY_7_0 (((REG32(ADR_TX_ACK_POLICY_7_0)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_0 (((REG32(ADR_TX_SEQ_CTRL_7_0)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_1 (((REG32(ADR_TX_ACK_POLICY_7_1)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_1 (((REG32(ADR_TX_SEQ_CTRL_7_1)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_2 (((REG32(ADR_TX_ACK_POLICY_7_2)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_2 (((REG32(ADR_TX_SEQ_CTRL_7_2)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_3 (((REG32(ADR_TX_ACK_POLICY_7_3)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_3 (((REG32(ADR_TX_SEQ_CTRL_7_3)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_4 (((REG32(ADR_TX_ACK_POLICY_7_4)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_4 (((REG32(ADR_TX_SEQ_CTRL_7_4)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_5 (((REG32(ADR_TX_ACK_POLICY_7_5)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_5 (((REG32(ADR_TX_SEQ_CTRL_7_5)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_6 (((REG32(ADR_TX_ACK_POLICY_7_6)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_6 (((REG32(ADR_TX_SEQ_CTRL_7_6)) & 0x00000fff ) >> 0) #define GET_TX_ACK_POLICY_7_7 (((REG32(ADR_TX_ACK_POLICY_7_7)) & 0x00000003 ) >> 0) #define GET_TX_SEQ_CTRL_7_7 (((REG32(ADR_TX_SEQ_CTRL_7_7)) & 0x00000fff ) >> 0) #define GET_RG_GEMINIA_HW_PINSEL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_HS_3WIRE_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_MODE_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_RX_GAIN_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_TX_GAIN_MANUAL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_TXGAIN_PHYCTRL (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_RX_AGC (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_MODE (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_GEMINIA_CAL_INDEX (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_GEMINIA_RFG (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_PGAG (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x003c0000 ) >> 18) #define GET_RG_GEMINIA_TX_GAIN (((REG32(ADR_GEMINIA_3_WIRE_REGISTER)) & 0x7f000000 ) >> 24) #define GET_RG_GEMINIA_TX_TRSW_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_EN_TX_TRSW (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_RX_LNA_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_EN_RX_LNA (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_RX_MIXER_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_EN_RX_MIXER (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_RX_DIV2_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_EN_RX_DIV2 (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_GEMINIA_RX_LOBUF_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_EN_RX_LOBUF (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_RX_TZ_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_EN_RX_TZ (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_RX_FILTER_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_EN_RX_FILTER (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_RX_ADC_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_EN_RX_ADC (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_GEMINIA_RX_RSSI_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_EN_RX_RSSI (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_TX_PA_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_EN_TX_PA (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_GEMINIA_TX_MOD_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_EN_TX_MOD (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_TX_DAC_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_EN_TX_DAC (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_TX_DIV2_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_EN_TX_DIV2 (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_TX_DIV2_BUF_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_EN_TX_DIV2_BUF (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_TX_BT_PA_MANUAL (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_EN_TX_BT_PA (((REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_EN_LDO_RX_FE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_EN_LDO_ABB (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_EN_LDO_ADC (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_EN_LDO_DAC (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_EN_IREF_RX (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_TX_DAC_CAL_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_EN_TX_DAC_CAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_RX_TZ_OUT_TRISTATE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_TX_SELF_MIXER_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_EN_TX_SELF_MIXER (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_RX_IQCAL_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_EN_RX_IQCAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_TX_DPD_MANUAL (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_EN_TX_DPD (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_GEMINIA_RXRCCALQ_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_EN_TX_TSSI (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_EN_SARADC (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_EN_TX_VTOI_2ND (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_GEMINIA_TXLPF_BYPASS (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_TX_EN_VOLTAGE_IN (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_EN_TX_DAC_OUT (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_EN_TX_DAC_VOUT (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_RX_ABBOUT_TRI_STATE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_EN_RX_TESTNODE (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_EN_RX_PADSW (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_LDO_RX_FE_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_LDO_RX_ABB_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_LDO_RX_ADC_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_LDO_TX_DAC_EN_BYP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_EN_LDO_RX_ADC_IQUP (((REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_LDO_LEVEL_RX_FE (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_GEMINIA_LDO_LEVEL_ABB (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00000038 ) >> 3) #define GET_RG_GEMINIA_LDO_LEVEL_ADC (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x000001c0 ) >> 6) #define GET_RG_GEMINIA_LDO_LEVEL_DAC (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00000e00 ) >> 9) #define GET_RG_GEMINIA_SX_LDO_CP_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_GEMINIA_SX_LDO_LO_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00038000 ) >> 15) #define GET_RG_GEMINIA_DP_LDO_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x00e00000 ) >> 21) #define GET_RG_GEMINIA_SX_LDO_VCO_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_GEMINIA_SX_LDO_DIV_LEVEL (((REG32(ADR_GEMINIA_LDO_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_WF_RX_ABBCTUNEI (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_RX_ABBCTUNEQ (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_GEMINIA_WF_RX_FILTERI_COARSE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_WF_RX_FILTERI1ST (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_GEMINIA_WF_RX_FILTERI2ND (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_WF_RX_FILTERI3RD (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_GEMINIA_WF_RX_ABBCFIX (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_WF_RX_ABB_N_MODE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_WF_RX_ABB_BT_MODE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_WF_RX_ABB_IDIV3 (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_WF_RX_EN_IDACA_COARSE (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_WF_RX_EN_LOOPA (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_WF_RX_FILTERVCM (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_GEMINIA_WF_RX_OUTVCM (((REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_GEMINIA_BT_RX_ABBCTUNEI (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_RX_ABBCTUNEQ (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_GEMINIA_BT_RX_FILTERI_COARSE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_BT_RX_FILTERI1ST (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_GEMINIA_BT_RX_FILTERI2ND (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_BT_RX_FILTERI3RD (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_GEMINIA_BT_RX_ABBCFIX (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_BT_RX_ABB_N_MODE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_BT_RX_ABB_BT_MODE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_BT_RX_ABB_IDIV3 (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_BT_RX_EN_IDACA_COARSE (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_BT_RX_EN_LOOPA (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_BT_RX_FILTERVCM (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_GEMINIA_BT_RX_OUTVCM (((REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_GEMINIA_RX_ADCRSSI_VCM (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_RX_REC_LPFCORNER (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_RX_ADCRSSI_CLKSEL (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_RSSI_CLOCK_GATING (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_TX_DPDGM_BIAS (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_TX_DPD_DIV (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_TX_TSSI_BIAS (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_TX_TSSI_DIV (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_GEMINIA_TX_TSSI_TEST (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_GEMINIA_TX_TSSI_TESTMODE (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_EN_RX_RSSI_TESTNODE (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x0e000000 ) >> 25) #define GET_RG_GEMINIA_RX_LNA_TRI_SEL (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_GEMINIA_RX_LNA_SETTLE (((REG32(ADR_GEMINIA_RX_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_WF_TXPGA_CAPSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_WF_TX_DIV_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_WF_TX_LOBUF_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_GEMINIA_WF_TX_VDDSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_BT_TXPGA_CAPSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_GEMINIA_BT_TX_DIV_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_GEMINIA_BT_TX_LOBUF_VSET (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_BT_TX_VDDSW (((REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_WF_PACELL_EN (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_GEMINIA_WF_PABIAS_CTRL (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_WF_TX_PA1_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_GEMINIA_WF_TX_PA2_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_GEMINIA_WF_TX_PA3_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_BT_PA_CAPSEL (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_BT_PABIAS_2X (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_BT_PABIAS_CTRL (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_GEMINIA_BT_TX_PA_VCAS (((REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_GEMINIA_TXPGA_MAIN (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_TXPGA_STEER (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_GEMINIA_TXMOD_GMCELL (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_TXLPF_GMCELL (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_GEMINIA_WF_TX_GAIN_OFFSET (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x000f0000 ) >> 16) #define GET_RG_GEMINIA_BT_TX_GAIN_OFFSET (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_GEMINIA_TX_VTOI_CURRENT (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_GEMINIA_TX_VTOI_GM (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_GEMINIA_TX_VTOI_OPTION (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_GEMINIA_TX_VTOI_FS (((REG32(ADR_GEMINIA_TX_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_WF_RX_HG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_WF_RX_HG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_WF_RX_HG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_WF_RX_HG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_WF_RX_HG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_WF_RX_HG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_WF_RX_HG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_WF_RX_HG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_WF_RX_HG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_WF_RX_MG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_WF_RX_MG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_WF_RX_MG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_WF_RX_MG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_WF_RX_MG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_WF_RX_MG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_WF_RX_MG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_WF_RX_MG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_WF_RX_MG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_WF_RX_LG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_WF_RX_LG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_WF_RX_LG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_WF_RX_LG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_WF_RX_LG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_WF_RX_LG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_WF_RX_LG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_WF_RX_LG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_WF_RX_LG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_WF_RX_ULG_LNA_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_WF_RX_ULG_TZ_GC (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_WF_RX_ULG_LNALG_BIAS (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_WF_RX_ULG_TZ_CAP (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_WF_RX_ULG_SQDC (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_WF_RX_ULG_DIV2_CORE (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_WF_RX_ULG_LOBUF (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_WF_RX_ULG_TZI (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_WF_RX_ULG_TZ_VCM (((REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_BT_RX_HG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_BT_RX_HG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_BT_RX_HG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_BT_RX_HG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_BT_RX_HG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_BT_RX_HG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_BT_RX_HG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_BT_RX_HG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_BT_RX_HG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_BT_RX_MG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_BT_RX_MG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_BT_RX_MG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_BT_RX_MG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_BT_RX_MG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_BT_RX_MG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_BT_RX_MG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_BT_RX_MG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_BT_RX_MG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_BT_RX_LG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_BT_RX_LG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_BT_RX_LG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_BT_RX_LG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_BT_RX_LG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_BT_RX_LG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_BT_RX_LG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_BT_RX_LG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_BT_RX_LG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_BT_RX_ULG_LNA_GC (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_BT_RX_ULG_TZ_GC (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_BT_RX_ULG_LNALG_BIAS (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_BT_RX_ULG_TZ_CAP (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_BT_RX_ULG_SQDC (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_BT_RX_ULG_DIV2_CORE (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_BT_RX_ULG_LOBUF (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x06000000 ) >> 25) #define GET_RG_GEMINIA_BT_RX_ULG_TZI (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_BT_RX_ULG_TZ_VCM (((REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_RX_ADC_CLKSEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_RX_ADC_DNLEN (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_RX_ADC_METAEN (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_RX_ADC_TFLAG (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_RX_ADC_TSEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_WF_RX_ADC_ICMP (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_GEMINIA_WF_RX_ADC_VCMI (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_GEMINIA_WF_RX_ADC_CLOAD (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_BT_RX_ADC_ICMP (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_BT_RX_ADC_VCMI (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_GEMINIA_BT_RX_ADC_CLOAD (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_GEMINIA_SARADC_VRSEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_GEMINIA_EN_SAR_TEST (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_GEMINIA_SARADC_THERMAL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_SARADC_TSSI (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_CLK_SAR_SEL (((REG32(ADR_GEMINIA_RX_ADC_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_WF_TX_DACI1ST (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_WF_TX_DACLPF_ICOARSE (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_WF_TX_DACLPF_IFINE (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_GEMINIA_WF_TX_DACLPF_VCM (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_GEMINIA_WF_TX_DAC_IBIAS (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_GEMINIA_WF_TX_DAC_IATTN (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_WF_TXLPF_BOOSTI (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_WF_TX_DAC_RCAL (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_WF_TX_DAC_OS (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_WF_TX_DAC_IOFFSET (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_GEMINIA_WF_TX_DAC_QOFFSET (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_GEMINIA_TX_DAC_TSEL (((REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) & 0xf0000000 ) >> 28) #define GET_RG_GEMINIA_BT_TX_DACI1ST (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_BT_TX_DACLPF_ICOARSE (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_BT_TX_DACLPF_IFINE (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_GEMINIA_BT_TX_DACLPF_VCM (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_GEMINIA_BT_TX_DAC_IBIAS (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_GEMINIA_BT_TX_DAC_IATTN (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_BT_TXLPF_BOOSTI (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_BT_TX_DAC_RCAL (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_BT_TX_DAC_OS (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_BT_TX_DAC_IOFFSET (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_GEMINIA_BT_TX_DAC_QOFFSET (((REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_GEMINIA_SX_EN_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_SX_EN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_EN_SX_CP_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_EN_SX_CP (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_EN_SX_DIV_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_EN_SX_DIV (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_EN_SX_VCO_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_EN_SX_VCO (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000080 ) >> 7) #define GET_RG_GEMINIA_SX_PFD_RST_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_SX_PFD_RST (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_SX_UOP_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_SX_UOP_EN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_EN_VCOBF_TXMB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_EN_VCOBF_TXMB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_EN_VCOBF_TXOB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_EN_VCOBF_TXOB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00008000 ) >> 15) #define GET_RG_GEMINIA_EN_VCOBF_RXMB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_EN_VCOBF_RXMB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_EN_VCOBF_RXOB_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_EN_VCOBF_RXOB (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00080000 ) >> 19) #define GET_RG_GEMINIA_EN_VCOBF_DIVCK_MAN (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_EN_VCOBF_DIVCK (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_SX_SBCAL_DIS (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_SX_SBCAL_AW (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_SX_AAC_DIS (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_SX_TTL_DIS (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_SX_CAL_INIT (((REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0xe0000000 ) >> 29) #define GET_RG_GEMINIA_EN_SX_LDO_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_EN_LDO_CP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_EN_LDO_DIV (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_EN_LDO_LO (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_EN_LDO_VCO (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_EN_LDO_CP_BYP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_EN_LDO_DIV_BYP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_GEMINIA_EN_LDO_LO_BYP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_EN_LDO_VCO_PSW (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_EN_LDO_VCO_VDD33 (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_EN_LDO_CP_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_EN_LDO_DIV_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_EN_LDO_LO_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_EN_LDO_VCO_IQUP (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_SX_LDO_FCOFFT (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_GEMINIA_LDO_CP_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_LDO_CP_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_LDO_DIV_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_LDO_DIV_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_LDO_LO_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_LDO_LO_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_LDO_VCO_FC_MAN (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_LDO_VCO_FC (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_LDO_VCO_RCF (((REG32(ADR_GEMINIA_SX_LDO_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_GEMINIA_SX_RFCTRL_F (((REG32(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0) #define GET_RG_GEMINIA_SX_RFCTRL_CH_7_0 (((REG32(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24) #define GET_RG_GEMINIA_SX_RFCTRL_CH_10_8 (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000007 ) >> 0) #define GET_RG_GEMINIA_SX_RFCH_MAP_EN (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_SX_XTAL_FREQ (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000060 ) >> 5) #define GET_RG_GEMINIA_SX_FREF_DOUB (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000080 ) >> 7) #define GET_RG_GEMINIA_SX_BTRX_SIDE (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_SX_LO_TIMES (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_SX_CHANNEL (((REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) & 0x0007f800 ) >> 11) #define GET_RG_GEMINIA_SX_CP_ISEL_BT (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x0000000f ) >> 0) #define GET_RG_GEMINIA_SX_CP_ISEL50U_BT (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_SX_CP_KP_DOUB_BT (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_SX_CP_ISEL_WF (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000780 ) >> 7) #define GET_RG_GEMINIA_SX_CP_ISEL50U_WF (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_SX_CP_KP_DOUB_WF (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_SX_CP_IOST_POL (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00008000 ) >> 15) #define GET_RG_GEMINIA_SX_CP_IOST (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_SX_PFD_SEL (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_SX_PFD_SET (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_SX_PFD_SET1 (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_SX_PFD_SET2 (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_SX_PFD_TRUP (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_SX_PFD_TRDN (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_SX_PFD_TLSEL (((REG32(ADR_GEMINIA_SYN_PFD_CHP_)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_SX_LPF_C1_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x0000000f ) >> 0) #define GET_RG_GEMINIA_SX_LPF_C2_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_SX_LPF_C3_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_SX_LPF_R2_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x00001e00 ) >> 9) #define GET_RG_GEMINIA_SX_LPF_R3_BT (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x0000e000 ) >> 13) #define GET_RG_GEMINIA_SX_LPF_C1_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x000f0000 ) >> 16) #define GET_RG_GEMINIA_SX_LPF_C2_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x00f00000 ) >> 20) #define GET_RG_GEMINIA_SX_LPF_C3_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_SX_LPF_R2_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0x1e000000 ) >> 25) #define GET_RG_GEMINIA_SX_LPF_R3_WF (((REG32(ADR_GEMINIA_SYN_LPF)) & 0xe0000000 ) >> 29) #define GET_RG_GEMINIA_SX_VCO_ISEL_MAN (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_SX_VCO_ISEL_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x0000001e ) >> 1) #define GET_RG_GEMINIA_SX_VCO_LPM_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_SX_VCO_VCCBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x000001c0 ) >> 6) #define GET_RG_GEMINIA_SX_VCO_KVDOUB_BT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_SX_VCO_ISEL_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00003c00 ) >> 10) #define GET_RG_GEMINIA_SX_VCO_LPM_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_SX_VCO_VCCBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00038000 ) >> 15) #define GET_RG_GEMINIA_SX_VCO_KVDOUB_WF (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_SX_VCO_VARBSEL (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00600000 ) >> 21) #define GET_RG_GEMINIA_SX_VCO_RTAIL_SHIFT (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_SX_VCO_CS_AWH (((REG32(ADR_GEMINIA_SYN_VCO)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_VOBF_TXMBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_VOBF_TXOBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_VOBF_RXMBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00000030 ) >> 4) #define GET_RG_GEMINIA_VOBF_RXOBSEL_BT (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x000000c0 ) >> 6) #define GET_RG_GEMINIA_VOBF_TXMBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00000c00 ) >> 10) #define GET_RG_GEMINIA_VOBF_TXOBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00003000 ) >> 12) #define GET_RG_GEMINIA_VOBF_RXMBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x0000c000 ) >> 14) #define GET_RG_GEMINIA_VOBF_RXOBSEL_WF (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_VOBF_DIVBFSEL (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00080000 ) >> 19) #define GET_RG_GEMINIA_SX_VCO_TXOB_AW (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_SX_VCO_RXOB_AW (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_VOBF_CAPIMB_POL (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_VOBF_CAPIMB (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x38000000 ) >> 27) #define GET_RG_GEMINIA_EN_SX_VCOMON (((REG32(ADR_GEMINIA_SYN_VCOBF)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_SX_DIV_PREVDD (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x0000000f ) >> 0) #define GET_RG_GEMINIA_SX_DIV_PSCVDD (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_SX_DIV_RST_H (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_SX_DIV_SDM_EDGE (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_SX_DIV_DMYBUF_EN (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_EN_SX_MOD (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_EN_SX_DITHER (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_SX_MOD_ORDER (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00180000 ) >> 19) #define GET_RG_GEMINIA_SX_DITHER_WEIGHT (((REG32(ADR_GEMINIA_SYN_DIV_SDM)) & 0x00600000 ) >> 21) #define GET_RG_GEMINIA_SX_SUB_SEL_MAN (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_SX_SUB_SEL (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x000001fe ) >> 1) #define GET_RG_GEMINIA_SX_SUB_C0P5_DIS (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_SX_SBCAL_CT (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00000c00 ) >> 10) #define GET_RG_GEMINIA_SX_SBCAL_WT (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_SX_SBCAL_DIFFMIN (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_SX_SBCAL_NTARG_MAN (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0x00008000 ) >> 15) #define GET_RG_GEMINIA_SX_SBCAL_NTARG (((REG32(ADR_GEMINIA_SYN_SBCAL)) & 0xffff0000 ) >> 16) #define GET_RG_GEMINIA_VO_AAC_TAR_BT (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x0000000f ) >> 0) #define GET_RG_GEMINIA_VO_AAC_IOST_BT (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00000030 ) >> 4) #define GET_RG_GEMINIA_VO_AAC_TAR_WF (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00000780 ) >> 7) #define GET_RG_GEMINIA_VO_AAC_IOST_WF (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00001800 ) >> 11) #define GET_RG_GEMINIA_VO_AAC_IMAX (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x0003c000 ) >> 14) #define GET_RG_GEMINIA_VO_AAC_INIT (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x000c0000 ) >> 18) #define GET_RG_GEMINIA_VO_AAC_EVA_TS (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00300000 ) >> 20) #define GET_RG_GEMINIA_VO_AAC_EN_MAN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x00800000 ) >> 23) #define GET_RG_GEMINIA_VO_AAC_EN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_VO_AAC_EVA_MAN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_VO_AAC_EVA (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_VO_AAC_TEST_EN (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_VO_AAC_TEST_SEL (((REG32(ADR_GEMINIA_SYN_AAC)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_SX_TTL_INIT (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_SX_TTL_FPT (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_SX_TTL_CPT (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000030 ) >> 4) #define GET_RG_GEMINIA_SX_TTL_ACCUM (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000180 ) >> 7) #define GET_RG_GEMINIA_SX_TTL_SUB (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00000c00 ) >> 10) #define GET_RG_GEMINIA_SX_TTL_SUB_INV (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_SX_TTL_VH (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x0000c000 ) >> 14) #define GET_RG_GEMINIA_SX_TTL_VL (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_SX_LPF_VTUNE_TEST (((REG32(ADR_GEMINIA_SYN_TTL)) & 0x00080000 ) >> 19) #define GET_RG_GEMINIA_DP_BBPLL_PD (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_DP_BBPLL_BP (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_EN_DP_MANUAL (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_DP_FREF_DOUB (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_DP_DAC320_DIVBY2 (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_DP_ADC320_DIVBY2_BT (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_DP_ADC320_DIVBY2_WF (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_EN_DPL_MOD (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_DPL_MOD_ORDER (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x00000600 ) >> 9) #define GET_RG_GEMINIA_DP_REFDIV (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x0003f800 ) >> 11) #define GET_RG_GEMINIA_DP_FODIV (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x01fc0000 ) >> 18) #define GET_RG_GEMINIA_EN_LDO_DP_BYP (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_EN_LDO_DP_IQUP (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_DP_OD_TEST (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_DP_BBPLL_TESTSEL (((REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_GEMINIA_DP_BBPLL_ICP (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_DP_BBPLL_IDUAL (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_GEMINIA_DP_CP_IOSTPOL (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_DP_CP_IOST (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000060 ) >> 5) #define GET_RG_GEMINIA_DP_PFD_PFDSEL (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_GEMINIA_DP_BBPLL_PFD_DLY (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_GEMINIA_DP_RP (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00003800 ) >> 11) #define GET_RG_GEMINIA_DP_RHP (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_GEMINIA_EN_DP_VT_MON (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_DP_VT_TH_HI (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_GEMINIA_DP_VT_TH_LO (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_GEMINIA_DP_BBPLL_BS (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x1f800000 ) >> 23) #define GET_RG_GEMINIA_DP_BBPLL_SDM_EDGE (((REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_DPL_RFCTRL_F (((REG32(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS)) & 0x00ffffff ) >> 0) #define GET_RG_GEMINIA_DPL_RFCTRL_CH (((REG32(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS)) & 0xff000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_IDACAI_TZ0_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_IDACAI_TZ0_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_IDACAI_TZ0_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_IDACAI_TZ0_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_IDACAI_TZ0_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_IDACAQ_TZ0_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_IDACAI_TZ1_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE4 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_IDACAI_TZ1_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE3 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_IDACAI_TZ1_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE2 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_IDACAI_TZ1_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE1 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_IDACAI_TZ1_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_IDACAQ_TZ1_COARSE0 (((REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0 (((REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_GEMINIA_SX_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_GEMINIA_TXDAC_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_TXRF_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_TXPA_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_RXRF_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16) #define GET_RG_GEMINIA_TXBTPA_DELAY (((REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) & 0x00f00000 ) >> 20) #define GET_RG_GEMINIA_TXDAC_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_GEMINIA_TXRF_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_GEMINIA_TXPA_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_GEMINIA_RXRF_T2R_DELAY (((REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_GEMINIA_TXDAC_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_GEMINIA_TXRF_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_GEMINIA_TXPA_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_GEMINIA_RXRF_R2T_DELAY (((REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_GEMINIA_WF_RX_DCCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_GEMINIA_BT_RX_DCCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_GEMINIA_RX_RCCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_GEMINIA_TX_LOCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_GEMINIA_TX_IQCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_GEMINIA_RX_IQCAL_DELAY (((REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_GEMINIA_PGAG_RCCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x0000000f ) >> 0) #define GET_RG_GEMINIA_PGAG_TXCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x000000f0 ) >> 4) #define GET_RG_GEMINIA_TX_GAIN_TXCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x00007f00 ) >> 8) #define GET_RG_GEMINIA_RFG_RXIQCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x00030000 ) >> 16) #define GET_RG_GEMINIA_PGAG_RXIQCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x003c0000 ) >> 18) #define GET_RG_GEMINIA_TX_GAIN_RXIQCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) & 0x1fc00000 ) >> 22) #define GET_RG_GEMINIA_RFG_DPDCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_PGAG_DPDCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) & 0x0000003c ) >> 2) #define GET_RG_GEMINIA_TX_GAIN_DPDCAL (((REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) & 0x00001fc0 ) >> 6) #define GET_DB_GEMINIA_AD_ADC_I_OUT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x000003ff ) >> 0) #define GET_DB_GEMINIA_AD_ADC_Q_OUT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x000ffc00 ) >> 10) #define GET_DB_GEMINIA_AD_RX_RSSIADC (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x00f00000 ) >> 20) #define GET_DB_GEMINIA_DA_SARADC_BIT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x3f000000 ) >> 24) #define GET_GEMINIA_SAR_ADC_FSM_RDY (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) & 0x40000000 ) >> 30) #define GET_DB_GEMINIA_DA_SX_SUB_SEL (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x000000ff ) >> 0) #define GET_DB_GEMINIA_DA_SX_VCO_ISEL (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x00001e00 ) >> 9) #define GET_DB_GEMINIA_VO_AAC_COMPOUT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x00002000 ) >> 13) #define GET_DB_GEMINIA_SX_TTL_VT_DET (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x00018000 ) >> 15) #define GET_DB_GEMINIA_AD_DP_VT_MON_Q (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) & 0x60000000 ) >> 29) #define GET_DB_GEMINIA_SX_SBCAL_NCOUNT (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX2)) & 0x0000ffff ) >> 0) #define GET_DB_GEMINIA_SX_SBCAL_NTARGET (((REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX2)) & 0xffff0000 ) >> 16) #define GET_RG_GEMINIA_NFRAC_DELTA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) & 0x00ffffff ) >> 0) #define GET_RG_GEMINIA_40M_MODE (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_LO_UP_CH (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_RX_IQ_ALPHA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x0000001f ) >> 0) #define GET_RG_GEMINIA_RX_IQ_THETA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00001f00 ) >> 8) #define GET_RG_GEMINIA_RX_IQ_MANUAL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_RXIQ_NOSHRK (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_RX_RSSIADC_TH (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x00f00000 ) >> 20) #define GET_RG_GEMINIA_RSSI_EDGE_SEL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_ADC_EDGE_SEL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_Q_INV (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_I_INV (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_IQ_SWAP (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_SIGN_SWAP (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_TX_IQ_ALPHA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x0000001f ) >> 0) #define GET_RG_GEMINIA_TX_IQ_THETA (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x00001f00 ) >> 8) #define GET_RG_GEMINIA_TX_IQ_MANUAL (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_TXIQ_NOSHRK (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_TX_FREQ_OFFSET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x0000ffff ) >> 0) #define GET_RG_GEMINIA_TONE_SCALE (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x01ff0000 ) >> 16) #define GET_RG_GEMINIA_TX_UP8X_MAN_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x08000000 ) >> 27) #define GET_RG_GEMINIA_DIS_DAC_OFFSET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_EXT_DAC_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_DPLL_CLK320BY2 (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_CBW_20_40 (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_DAC_DC_Q (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R5)) & 0x000003ff ) >> 0) #define GET_RG_GEMINIA_DAC_DC_I (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R5)) & 0x03ff0000 ) >> 16) #define GET_RG_GEMINIA_DAC_Q_SET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x000003ff ) >> 0) #define GET_RG_GEMINIA_DAC_MAN_Q_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_DAC_I_SET (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x03ff0000 ) >> 16) #define GET_RG_GEMINIA_DAC_MAN_I_EN (((REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_BW20_HB_COEF_01 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R0)) & 0x00001fff ) >> 0) #define GET_RG_GEMINIA_BW20_HB_COEF_00 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R0)) & 0x1fff0000 ) >> 16) #define GET_RG_GEMINIA_BW20_HB_COEF_03 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R1)) & 0x00001fff ) >> 0) #define GET_RG_GEMINIA_BW20_HB_COEF_02 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R1)) & 0x1fff0000 ) >> 16) #define GET_RG_GEMINIA_BW20_HB_COEF_05 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R2)) & 0x00001fff ) >> 0) #define GET_RG_GEMINIA_BW20_HB_COEF_04 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R2)) & 0x1fff0000 ) >> 16) #define GET_RG_GEMINIA_BW20_HB_COEF_07 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R3)) & 0x00001fff ) >> 0) #define GET_RG_GEMINIA_BW20_HB_COEF_06 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R3)) & 0x1fff0000 ) >> 16) #define GET_RG_GEMINIA_BW20_HB_COEF_09 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R4)) & 0x00001fff ) >> 0) #define GET_RG_GEMINIA_BW20_HB_COEF_08 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R4)) & 0x1fff0000 ) >> 16) #define GET_RG_GEMINIA_BW20_HB_COEF_11 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R5)) & 0x00001fff ) >> 0) #define GET_RG_GEMINIA_BW20_HB_COEF_10 (((REG32(ADR_GEMINIA_TX_UP8X_COEF_R5)) & 0x1fff0000 ) >> 16) #define GET_RG_GEMINIA_PHASE_STEP_VALUE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x0000ffff ) >> 0) #define GET_RG_GEMINIA_PHASE_MANUAL (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_ALPHA_SEL (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x00300000 ) >> 20) #define GET_RG_GEMINIA_SPECTRUM_BW (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x03000000 ) >> 24) #define GET_RG_GEMINIA_SPECTRUM_EN (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_RX_RCCAL_TARG (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x000003ff ) >> 0) #define GET_RG_GEMINIA_RX_DC_POLAR_INV (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_RCCAL_POLAR_INV (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00002000 ) >> 13) #define GET_RO_GEMINIA_WF_DCCAL_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00010000 ) >> 16) #define GET_RO_GEMINIA_BT_DCCAL_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00020000 ) >> 17) #define GET_RO_GEMINIA_RCCAL_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00040000 ) >> 18) #define GET_RO_GEMINIA_TXDC_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00080000 ) >> 19) #define GET_RO_GEMINIA_TXIQ_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00100000 ) >> 20) #define GET_RO_GEMINIA_RXIQ_DONE (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_PHASE_17P5M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R2)) & 0x0000ffff ) >> 0) #define GET_RG_GEMINIA_PHASE_2P5M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R2)) & 0xffff0000 ) >> 16) #define GET_RG_GEMINIA_PHASE_RXIQ_1M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R3)) & 0x0000ffff ) >> 0) #define GET_RG_GEMINIA_PHASE_1M (((REG32(ADR_GEMINIA_RF_D_CAL_TOP_R3)) & 0xffff0000 ) >> 16) #define GET_RG_GEMINIA_EN_LDO_XO_BYP (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_EN_LDO_XO_IQUP (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_XO_LDO_LEVEL (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x0000001c ) >> 2) #define GET_RG_GEMINIA_XO_CBANKI (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00001fe0 ) >> 5) #define GET_RG_GEMINIA_XO_CBANKO (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x001fe000 ) >> 13) #define GET_RG_GEMINIA_EN_FDB (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_FDB_BYPASS (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_FDB_DUTY_LTH (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x01800000 ) >> 23) #define GET_RG_GEMINIA_EN_XOTEST (((REG32(ADR_GEMINIA_PMU_REG_1)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_EN_FDB_DCC_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_EN_FDB_DELAYC_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_EN_FDB_DELAYF_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_EN_FDB_PHASESWAP_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000008 ) >> 3) #define GET_RG_GEMINIA_FDB_PHASESWAP_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_FDB_CDELAY_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_FDB_FDELAY_MUAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x0000f000 ) >> 12) #define GET_RG_GEMINIA_XO_TIMMER (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x003f0000 ) >> 16) #define GET_RG_GEMINIA_DPL_SETTLING_TIMMER (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x00c00000 ) >> 22) #define GET_RG_GEMINIA_FDB_RDELAYF (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x03000000 ) >> 24) #define GET_RG_GEMINIA_FDB_RDELAYS (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x0c000000 ) >> 26) #define GET_RG_GEMINIA_FDB_RECAL_TIMMER (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x30000000 ) >> 28) #define GET_RG_GEMINIA_EN_FDB_RECAL (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_LOAD_RFTABLE_RDY (((REG32(ADR_GEMINIA_PMU_REG_2)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_DCDC_MODE (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_BUCK_LEVEL (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x0000000e ) >> 1) #define GET_RG_GEMINIA_DLDO_LEVEL (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000070 ) >> 4) #define GET_RG_GEMINIA_DLDO_BOOST_IQ (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_BUCK_EN_PSM (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_BUCK_PSM_VTH (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_BUCK_VREF_SEL (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00000800 ) >> 11) #define GET_RG_GEMINIA_LDO_LEVEL_EFUSE (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00007000 ) >> 12) #define GET_RG_GEMINIA_EN_LDO_EFUSE (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_DCDC_PULLLOW_CON (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_DCDC_RES2_CON (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00080000 ) >> 19) #define GET_RG_GEMINIA_DCDC_RES_CON (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_RTC_RS1 (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_RTC_RS2 (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_DCDC_CLK (((REG32(ADR_GEMINIA_PMU_REG_3)) & 0x03000000 ) >> 24) #define GET_RG_GEMINIA_RTC_OFFSET (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x000000ff ) >> 0) #define GET_RG_GEMINIA_RTC_CAL_TARGET_COUNT (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x000fff00 ) >> 8) #define GET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x3ff00000 ) >> 20) #define GET_RG_GEMINIA_RTC_CAL_MODE (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_SEL_DPLL_CLK (((REG32(ADR_GEMINIA_PMU_REG_4)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_GEMINIA_PMU_REG_5)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_EN_RTC_CAL (((REG32(ADR_GEMINIA_PMU_REG_5)) & 0x00000002 ) >> 1) #define GET_RO_GEMINIA_RTC_OSC_RES_SW (((REG32(ADR_GEMINIA_PMU_REG_6)) & 0x03ff0000 ) >> 16) #define GET_RO_GEMINIA_RTC_OSC_CAL_RES_RDY (((REG32(ADR_GEMINIA_PMU_REG_6)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_BT_CLK_SW (((REG32(ADR_GEMINIA_PMU_BT_CLK)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_BT_CLK32K_CAL_DONE (((REG32(ADR_GEMINIA_PMU_BT_CLK)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_SLEEP_WAKE_CNT (((REG32(ADR_GEMINIA_PMU_SLEEP_REG)) & 0x00ffffff ) >> 0) #define GET_RG_GEMINIA_PMU_ENTER_SLEEP_MODE (((REG32(ADR_GEMINIA_PMU_SLEEP_REG)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_RTC_EN (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_CLK_RTC_SW (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x00000002 ) >> 1) #define GET_RO_GEMINIA_PMU_WAKE_TRIG_EVENT (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x00003000 ) >> 12) #define GET_RO_GEMINIA_RTC_TICK_CNT (((REG32(ADR_GEMINIA_PMU_RTC_REG_0)) & 0x7fff0000 ) >> 16) #define GET_RG_GEMINIA_RTC_INT_SEC_MASK (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_RTC_INT_ALARM_MASK (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00000002 ) >> 1) #define GET_RO_GEMINIA_RTC_INT_SEC (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00010000 ) >> 16) #define GET_RO_GEMINIA_RTC_INT_ALARM (((REG32(ADR_GEMINIA_PMU_RTC_REG_1)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_RTC_SEC_START_CNT (((REG32(ADR_GEMINIA_PMU_RTC_REG_2)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RTC_SEC_ALARM_VALUE (((REG32(ADR_GEMINIA_PMU_RTC_REG_3)) & 0xffffffff ) >> 0) #define GET_RO_GEMINIA_FDB_CDELAY (((REG32(ADR_GEMINIA_PMU_FDB_REG_0)) & 0x00f00000 ) >> 20) #define GET_RO_GEMINIA_FDB_FDELAY (((REG32(ADR_GEMINIA_PMU_FDB_REG_0)) & 0x0f000000 ) >> 24) #define GET_RO_GEMINIA_FDB_PHASESWAP (((REG32(ADR_GEMINIA_PMU_FDB_REG_0)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_GPIO16_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_GPIO16_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_GPIO16_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_GPIO17_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_GPIO17_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_GPIO17_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_GPIO18_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_GPIO18_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_GPIO18_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_GPIO19_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_GPIO19_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_GPIO19_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_GPIO20_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_GPIO20_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_GPIO20_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_SPIS_MISO_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_FPGA_CLK_REF_40M_DS (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_FPGA_CLK_REF_40M_PD (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_FPGA_CLK_REF_40M_OE (((REG32(ADR_GEMINIA_IO_REG_0)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_GPIO08_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_GPIO08_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_GPIO08_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_GPIO09_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_GPIO09_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_GPIO09_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_GPIO10_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_GPIO10_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_GPIO10_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_GPIO11_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_GPIO11_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_GPIO11_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_GPIO12_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_GPIO12_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_GPIO12_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_GPIO13_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_GPIO13_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_GPIO13_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_GPIO14_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_GPIO14_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_GPIO14_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_GPIO15_DS (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_GPIO15_PD (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_GPIO15_OE (((REG32(ADR_GEMINIA_IO_REG_1)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_GPIO00_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000001 ) >> 0) #define GET_RG_GEMINIA_GPIO00_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000002 ) >> 1) #define GET_RG_GEMINIA_GPIO00_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000004 ) >> 2) #define GET_RG_GEMINIA_GPIO01_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000010 ) >> 4) #define GET_RG_GEMINIA_GPIO01_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000020 ) >> 5) #define GET_RG_GEMINIA_GPIO01_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000040 ) >> 6) #define GET_RG_GEMINIA_GPIO02_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000100 ) >> 8) #define GET_RG_GEMINIA_GPIO02_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000200 ) >> 9) #define GET_RG_GEMINIA_GPIO02_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00000400 ) >> 10) #define GET_RG_GEMINIA_GPIO03_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00001000 ) >> 12) #define GET_RG_GEMINIA_GPIO03_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00002000 ) >> 13) #define GET_RG_GEMINIA_GPIO03_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00004000 ) >> 14) #define GET_RG_GEMINIA_GPIO04_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00010000 ) >> 16) #define GET_RG_GEMINIA_GPIO04_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00020000 ) >> 17) #define GET_RG_GEMINIA_GPIO04_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00040000 ) >> 18) #define GET_RG_GEMINIA_GPIO05_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00100000 ) >> 20) #define GET_RG_GEMINIA_GPIO05_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00200000 ) >> 21) #define GET_RG_GEMINIA_GPIO05_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x00400000 ) >> 22) #define GET_RG_GEMINIA_GPIO06_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x01000000 ) >> 24) #define GET_RG_GEMINIA_GPIO06_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x02000000 ) >> 25) #define GET_RG_GEMINIA_GPIO06_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x04000000 ) >> 26) #define GET_RG_GEMINIA_GPIO07_DS (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x10000000 ) >> 28) #define GET_RG_GEMINIA_GPIO07_PD (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x20000000 ) >> 29) #define GET_RG_GEMINIA_GPIO07_OE (((REG32(ADR_GEMINIA_IO_REG_2)) & 0x40000000 ) >> 30) #define GET_RG_GEMINIA_RF_PHY_MODE_SEL (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00000003 ) >> 0) #define GET_RG_GEMINIA_RF_PHY_MODE_WIFI_MAC (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00000070 ) >> 4) #define GET_RG_GEMINIA_PAD_MUX_SEL (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00000f00 ) >> 8) #define GET_RG_GEMINIA_MODE_LATCH_LMT (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x00007000 ) >> 12) #define GET_RG_GEMINIA_EXT_MCU_PWRUP (((REG32(ADR_GEMINIA_MCU_REG_0)) & 0x80000000 ) >> 31) #define GET_RG_GEMINIA_RAM_00 (((REG32(ADR_GEMINIA_PMU_RAM_00)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_01 (((REG32(ADR_GEMINIA_PMU_RAM_01)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_02 (((REG32(ADR_GEMINIA_PMU_RAM_02)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_03 (((REG32(ADR_GEMINIA_PMU_RAM_03)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_04 (((REG32(ADR_GEMINIA_PMU_RAM_04)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_05 (((REG32(ADR_GEMINIA_PMU_RAM_05)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_06 (((REG32(ADR_GEMINIA_PMU_RAM_06)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_07 (((REG32(ADR_GEMINIA_PMU_RAM_07)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_08 (((REG32(ADR_GEMINIA_PMU_RAM_08)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_09 (((REG32(ADR_GEMINIA_PMU_RAM_09)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_10 (((REG32(ADR_GEMINIA_PMU_RAM_10)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_11 (((REG32(ADR_GEMINIA_PMU_RAM_11)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_12 (((REG32(ADR_GEMINIA_PMU_RAM_12)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_13 (((REG32(ADR_GEMINIA_PMU_RAM_13)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_14 (((REG32(ADR_GEMINIA_PMU_RAM_14)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_15 (((REG32(ADR_GEMINIA_PMU_RAM_15)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_16 (((REG32(ADR_GEMINIA_PMU_RAM_16)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_17 (((REG32(ADR_GEMINIA_PMU_RAM_17)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_18 (((REG32(ADR_GEMINIA_PMU_RAM_18)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_19 (((REG32(ADR_GEMINIA_PMU_RAM_19)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_20 (((REG32(ADR_GEMINIA_PMU_RAM_20)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_21 (((REG32(ADR_GEMINIA_PMU_RAM_21)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_22 (((REG32(ADR_GEMINIA_PMU_RAM_22)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_23 (((REG32(ADR_GEMINIA_PMU_RAM_23)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_24 (((REG32(ADR_GEMINIA_PMU_RAM_24)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_25 (((REG32(ADR_GEMINIA_PMU_RAM_25)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_26 (((REG32(ADR_GEMINIA_PMU_RAM_26)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_27 (((REG32(ADR_GEMINIA_PMU_RAM_27)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_28 (((REG32(ADR_GEMINIA_PMU_RAM_28)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_29 (((REG32(ADR_GEMINIA_PMU_RAM_29)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_30 (((REG32(ADR_GEMINIA_PMU_RAM_30)) & 0xffffffff ) >> 0) #define GET_RG_GEMINIA_RAM_31 (((REG32(ADR_GEMINIA_PMU_RAM_31)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_HW_PINSEL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_HS_3WIRE_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_MODE_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_RX_GAIN_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_TX_GAIN_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_TXGAIN_PHYCTRL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_RX_AGC (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_MODE (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_CAL_INDEX (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_RFG (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_PGAG (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x003c0000 ) >> 18) #define GET_RG_TURISMO_TRX_BW_HT40 (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_BW_MANUAL (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_TX_GAIN (((REG32(ADR_TURISMO_TRX_MODE_REGISTER)) & 0x7f000000 ) >> 24) #define GET_RG_TURISMO_TRX_TX_TRSW_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_EN_TX_TRSW (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_RX_LNA_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_EN_RX_LNA (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_RX_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_EN_RX_MIXER (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_RX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_EN_RX_DIV2 (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_RX_LOBUF_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_EN_RX_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_RX_TZ_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_EN_RX_TZ (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_RX_FILTER_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_RX_FILTER (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_RX_ADC_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_EN_RX_ADC (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_RX_RSSI_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_EN_RX_RSSI (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_TX_PA_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_EN_TX_PA (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_TX_MOD_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_EN_TX_MOD (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_TX_DAC_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_EN_TX_DAC (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_TX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_EN_TX_DIV2 (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_EN_TX_DIV2_BUF (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_TX_BT_PA_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_EN_TX_BT_PA (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_EN_IOT_ADC_BUF (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_EN_IOT_ADC (((REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_EN_LDO_RX_FE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_EN_LDO_AFE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_IREF_RX (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_TX_DAC_CAL_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_EN_TX_DAC_CAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_EN_TX_SELF_MIXER (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_RX_IQCAL_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_EN_RX_IQCAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_TX_DPD_MANUAL (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_TX_DPD (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_TX_TSSI (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_EN_SARADC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_EN_TX_VTOI_2ND (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_TXLPF_BYPASS (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_TX_EN_VOLTAGE_IN (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_EN_TX_DAC_OUT (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_EN_TX_DAC_VOUT (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_EN_RX_TESTNODE (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_EN_RX_PADSW (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_EN_LDO_RX_FE_FC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_FC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_RX_SQDC (((REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_LDO_LEVEL_RX_FE (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_EN_LDO_RX_FE_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_LDO_LEVEL_AFE (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_TX_PA_LDO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_DP_LDO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_LDO_DP_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_SX_LDO_CP_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_EN_LDO_CP_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_SX_LDO_LO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_TURISMO_TRX_EN_LDO_LO_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_SX_LDO_VCO_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_LDO_DIV_LEVEL (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_TURISMO_TRX_EN_LDO_DIV_BYP (((REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_WF_RX_ABBCTUNE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_RX_FILTERI_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_WF_RX_FILTERI1ST (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_WF_RX_FILTERI2ND (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_RX_FILTERI3RD (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_WF_RX_ABBCFIX (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_RX_ABB_N_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_WF_RX_ABB_BT_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_WF_RX_ABB_IDIV3 (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_RX_EN_LOOPA (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_WF_RX_FILTERVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_RX_OUTVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_TURISMO_TRX_WF_N_RX_ABBCTUNE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI1ST (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI2ND (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_N_RX_FILTERI3RD (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_WF_N_RX_ABBCFIX (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3 (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_N_RX_EN_LOOPA (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_WF_N_RX_FILTERVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_N_RX_OUTVCM (((REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_TURISMO_TRX_BT_RX_ABBCTUNE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_RX_FILTERI_COARSE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_BT_RX_FILTERI1ST (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_BT_RX_FILTERI2ND (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_RX_FILTERI3RD (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_BT_RX_ABBCFIX (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_RX_ABB_N_MODE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_BT_RX_ABB_BT_MODE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_BT_RX_ABB_IDIV3 (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_BT_RX_EN_LOOPA (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_BT_RX_FILTERVCM (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_RX_OUTVCM (((REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_TURISMO_TRX_RX_ADCRSSI_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_RX_REC_LPFCORNER (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_RSSI_CLOCK_GATING (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_TX_DPDGM_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_TX_DPD_DIV (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_TX_TSSI_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_TX_TSSI_DIV (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_TX_TSSI_TEST (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_TX_TSSI_TESTMODE (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x0e000000 ) >> 25) #define GET_RG_TURISMO_TRX_RX_LNA_TRI_SEL (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_TURISMO_TRX_RX_LNA_SETTLE (((REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_TURISMO_TRX_WF_TXPGA_CAPSW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_WF_TX_DIV_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_WF_TX_LOBUF_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_WF_TX_BTPASW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_WF_EN_TX_PA_VIN33 (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_BT_TXPGA_CAPSW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_TX_DIV_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_BT_TX_LOBUF_VSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_TX_BTPASW (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_BT_EN_TX_PA_VIN33 (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_TX_PA_LDO_SEL_RES (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_EN_LDO_TX_PA (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_EN_TX_PA_LDO_FC (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_EN_TX_PA_LDO_VTH (((REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_WF_PACELL_EN (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_WF_PABIAS_CTRL (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_WF_TX_PA1_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_WF_TX_PA2_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_TX_PA3_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_PABIAS_2X (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_BT_PABIAS_CTRL (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_TX_PA_VCAS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_TURISMO_TRX_BT_TX_MOD_CS (((REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_TURISMO_TRX_TXPGA_MAIN (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_TXPGA_STEER (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_TURISMO_TRX_TXMOD_GMCELL (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_TXLPF_GMCELL (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_WF_TX_GAIN_OFFSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_TX_GAIN_OFFSET (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_TX_VTOI_CURRENT (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_TX_VTOI_GM (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_TURISMO_TRX_TX_VTOI_OPTION (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_TURISMO_TRX_TX_VTOI_FS (((REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_WF_RX_HG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_WF_RX_HG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_RX_HG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_WF_RX_HG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_WF_RX_MG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_WF_RX_MG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_RX_MG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_WF_RX_MG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_WF_RX_LG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_WF_RX_LG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_RX_LG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_WF_RX_LG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_WF_RX_ULG_LNA_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_WF_RX_ULG_LOBUF (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_RX_ULG_TZI (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM (((REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_BT_RX_HG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_BT_RX_HG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_RX_HG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_BT_RX_HG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_BT_RX_MG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_BT_RX_MG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_RX_MG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_BT_RX_MG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_BT_RX_LG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_BT_RX_LG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_RX_LG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_BT_RX_LG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_BT_RX_ULG_LNA_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_BT_RX_ULG_LOBUF (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_RX_ULG_TZI (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM (((REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_RX_ADC_CLKSEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_RX_ADC_DNLEN (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_RX_ADC_METAEN (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_RX_ADC_TFLAG (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_RX_ADC_TSEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_WF_RX_ADC_ICMP (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_WF_RX_ADC_VCMI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_WF_RX_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_RX_ADC_ICMP (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_RX_ADC_VCMI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_TURISMO_TRX_BT_RX_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_SARADC_5G_TSSI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_SARADC_VRSEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_EN_SAR_TEST (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_TURISMO_TRX_SARADC_THERMAL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_SARADC_TSSI (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_CLK_SAR_SEL (((REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_TURISMO_TRX_WF_TX_DACI1ST (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_WF_TX_DACLPF_IFINE (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_WF_TX_DACLPF_VCM (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_TURISMO_TRX_WF_TX_DAC_IBIAS (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_WF_TX_DAC_IATTN (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_WF_TXLPF_BOOSTI (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_WF_TX_DAC_RCAL (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_WF_TX_DAC_OS (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_TX_DAC_IOFFSET (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_WF_TX_DAC_QOFFSET (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_TX_DAC_TSEL (((REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) & 0xf0000000 ) >> 28) #define GET_RG_TURISMO_TRX_BT_TX_DACI1ST (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_BT_TX_DACLPF_IFINE (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_BT_TX_DACLPF_VCM (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_TURISMO_TRX_BT_TX_DAC_IBIAS (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_BT_TX_DAC_IATTN (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_BT_TXLPF_BOOSTI (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_BT_TX_DAC_RCAL (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_BT_TX_DAC_OS (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_TX_DAC_IOFFSET (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_BT_TX_DAC_QOFFSET (((REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SX_EN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_SX_CP_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_EN_SX_CP (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_EN_SX_DIV_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_EN_SX_DIV (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_EN_SX_VCO_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_EN_SX_VCO (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_SX_PFD_RST_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_SX_PFD_RST (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX_UOP_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_SX_UOP_EN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_VCOBF_TXMB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_EN_VCOBF_TXOB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_EN_VCOBF_RXMB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_EN_VCOBF_RXOB (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_EN_VCOBF_DIVCK (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_SX_SBCAL_DIS (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_SX_SBCAL_AW (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_AAC_DIS (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_SX_TTL_DIS (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_SX_CAL_INIT (((REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_EN_SX_LDO_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_EN_LDO_CP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_LDO_DIV (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_EN_LDO_LO (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_EN_LDO_VCO (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_EN_LDO_VCO_PSW (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_EN_LDO_VCO_VDD33 (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_EN_LDO_CP_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_LDO_DIV_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_LDO_LO_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_EN_LDO_VCO_IQUP (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_SX_LDO_FCOFFT (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_LDO_CP_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_LDO_CP_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_LDO_DIV_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_LDO_DIV_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_LDO_LO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_LDO_LO_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_LDO_VCO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_LDO_VCO_FC (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_LDO_VCO_RCF (((REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_TURISMO_TRX_SX_RFCTRL_F (((REG32(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0) #define GET_RG_TURISMO_TRX_SX_RFCTRL_CH_7_0 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_RFCTRL_CH_10_8 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_SX_RFCH_MAP_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_SX_XTAL_FREQ (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000060 ) >> 5) #define GET_RG_TURISMO_TRX_SX_FREF_DOUB (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_SX_BTRX_SIDE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_SX_LO_TIMES (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX_CHANNEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0007f800 ) >> 11) #define GET_RG_TURISMO_TRX_SX_CP_ISEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SX_CP_ISEL50U_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_SX_CP_KP_DOUB_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_SX_CP_ISEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000780 ) >> 7) #define GET_RG_TURISMO_TRX_SX_CP_ISEL50U_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_SX_CP_KP_DOUB_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_SX_CP_IOST_POL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_SX_CP_IOST (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_SX_PFD_SEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_SX_PFD_SET (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_SX_PFD_SET1 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_PFD_SET2 (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_SX_PFD_REF_EDGE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_SX_PFD_DIV_EDGE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_SX_PFD_TRUP (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_SX_PFD_TRDN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_SX_PFD_TLSEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_SX_LPF_C1_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SX_LPF_C2_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_SX_LPF_C3_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_SX_LPF_R2_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x00001e00 ) >> 9) #define GET_RG_TURISMO_TRX_SX_LPF_R3_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x0000e000 ) >> 13) #define GET_RG_TURISMO_TRX_SX_LPF_C1_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_SX_LPF_C2_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_SX_LPF_C3_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_LPF_R2_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0x1e000000 ) >> 25) #define GET_RG_TURISMO_TRX_SX_LPF_R3_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_SX_VCO_ISEL_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SX_VCO_ISEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x0000001e ) >> 1) #define GET_RG_TURISMO_TRX_SX_VCO_LPM_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x000001c0 ) >> 6) #define GET_RG_TURISMO_TRX_SX_VCO_KVDOUB_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX_VCO_ISEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00003c00 ) >> 10) #define GET_RG_TURISMO_TRX_SX_VCO_LPM_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00038000 ) >> 15) #define GET_RG_TURISMO_TRX_SX_VCO_KVDOUB_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SX_VCO_VARBSEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00600000 ) >> 21) #define GET_RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_SX_VCO_CS_AWH (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_VOBF_TXMBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_VOBF_TXOBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_VOBF_RXMBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_VOBF_RXOBSEL_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x000000c0 ) >> 6) #define GET_RG_TURISMO_TRX_VOBF_TXMBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_VOBF_TXOBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_VOBF_RXMBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_VOBF_RXOBSEL_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_VOBF_DIVBFSEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_SX_VCO_TXOB_AW (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_SX_VCO_RXOB_AW (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_VOBF_CAPIMB_POL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_VOBF_CAPIMB (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x38000000 ) >> 27) #define GET_RG_TURISMO_TRX_EN_SX_VCOMON (((REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_SX_DIV_PREVDD (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SX_DIV_PSCVDD (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_SX_DIV_RST_H (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX_DIV_SDM_EDGE (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_SX_DIV_DMYBUF_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_SX_MOD (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_EN_SX_DITHER (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SX_MOD_ORDER (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00180000 ) >> 19) #define GET_RG_TURISMO_TRX_SX_DITHER_WEIGHT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) & 0x00600000 ) >> 21) #define GET_RG_TURISMO_TRX_SX_SUB_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SX_SUB_SEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x000001fe ) >> 1) #define GET_RG_TURISMO_TRX_SX_SUB_C0P5_DIS (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX_SBCAL_CT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_SX_SBCAL_WT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_SX_SBCAL_DIFFMIN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_SX_SBCAL_NTARG (((REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) & 0xffff0000 ) >> 16) #define GET_RG_TURISMO_TRX_VO_AAC_TAR_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_VO_AAC_IOST_BT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_VO_AAC_TAR_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00000780 ) >> 7) #define GET_RG_TURISMO_TRX_VO_AAC_IOST_WF (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00001800 ) >> 11) #define GET_RG_TURISMO_TRX_VO_AAC_IMAX (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x0003c000 ) >> 14) #define GET_RG_TURISMO_TRX_VO_AAC_INIT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x000c0000 ) >> 18) #define GET_RG_TURISMO_TRX_VO_AAC_EVA_TS (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_VO_AAC_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_VO_AAC_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_VO_AAC_EVA_MAN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_VO_AAC_EVA (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_VO_AAC_TEST_EN (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_VO_AAC_TEST_SEL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_SX_TTL_INIT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_SX_TTL_FPT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_SX_TTL_CPT (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_SX_TTL_ACCUM (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000180 ) >> 7) #define GET_RG_TURISMO_TRX_SX_TTL_SUB (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_SX_TTL_SUB_INV (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_SX_TTL_VH (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_SX_TTL_VL (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_SX_LPF_VTUNE_TEST (((REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_DP_BBPLL_PD (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_DP_BBPLL_BP (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_DP_MANUAL (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_DP_FREF_DOUB (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_DP_DAC320_DIVBY2 (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_EN_DPL_MOD (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_DPL_MOD_ORDER (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x00000600 ) >> 9) #define GET_RG_TURISMO_TRX_DP_REFDIV (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x0003f800 ) >> 11) #define GET_RG_TURISMO_TRX_DP_FODIV (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x01fc0000 ) >> 18) #define GET_RG_TURISMO_TRX_EN_LDO_DP_IQUP (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_DP_OD_TEST (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_DP_BBPLL_TESTSEL (((REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_TURISMO_TRX_DP_BBPLL_ICP (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_DP_BBPLL_IDUAL (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_DP_CP_IOSTPOL (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_DP_CP_IOST (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000060 ) >> 5) #define GET_RG_TURISMO_TRX_DP_PFD_PFDSEL (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_DP_BBPLL_PFD_DLY (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_DP_RP (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00003800 ) >> 11) #define GET_RG_TURISMO_TRX_DP_RHP (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_EN_DP_VT_MON (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_DP_VT_TH_HI (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_TURISMO_TRX_DP_VT_TH_LO (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_DP_BBPLL_BS (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x1f800000 ) >> 23) #define GET_RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE (((REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_DPL_RFCTRL_F (((REG32(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS)) & 0x00ffffff ) >> 0) #define GET_RG_TURISMO_TRX_DPL_RFCTRL_CH (((REG32(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS)) & 0xff000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_TXDAC_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_TXRF_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_TXPA_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_RXRF_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_TXBTPA_DELAY (((REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_TXDAC_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_TURISMO_TRX_TXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_TURISMO_TRX_TXPA_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_TURISMO_TRX_RXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_TURISMO_TRX_TXDAC_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_TURISMO_TRX_TXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_TURISMO_TRX_TXPA_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_TURISMO_TRX_RXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_TURISMO_TRX_WF_RX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_BT_RX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_TURISMO_TRX_RX_RCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_TX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_TX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_RX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_TURISMO_TRX_RX_N_RCCAL_DELAY (((REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_TURISMO_TRX_PGAG_RCCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_PGAG_TXCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_TX_GAIN_TXCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x00007f00 ) >> 8) #define GET_RG_TURISMO_TRX_RFG_RXIQCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_PGAG_RXIQCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x003c0000 ) >> 18) #define GET_RG_TURISMO_TRX_TX_GAIN_RXIQCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) & 0x1fc00000 ) >> 22) #define GET_RG_TURISMO_TRX_RFG_DPDCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_PGAG_DPDCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x0000003c ) >> 2) #define GET_RG_TURISMO_TRX_TX_GAIN_DPDCAL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00001fc0 ) >> 6) #define GET_RG_TURISMO_TRX_IOT_ADC_CLKSEL (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_IOT_ADC_DNLEN (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_IOT_ADC_METAEN (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_IOT_ADC_TFLAG (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_IOT_ADC_ICMP (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_IOT_ADC_VCMI (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_IOT_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_IOT_ADC_CLK_DIV (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x0c000000 ) >> 26) #define GET_RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY (((REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) & 0x10000000 ) >> 28) #define GET_DB_TURISMO_TRX_AD_ADC_I_OUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x000003ff ) >> 0) #define GET_DB_TURISMO_TRX_AD_ADC_Q_OUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x000ffc00 ) >> 10) #define GET_DB_TURISMO_TRX_AD_RX_RSSIADC (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x00f00000 ) >> 20) #define GET_DB_TURISMO_TRX_DA_SARADC_BIT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x3f000000 ) >> 24) #define GET_TURISMO_TRX_SAR_ADC_FSM_RDY (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) & 0x40000000 ) >> 30) #define GET_DB_TURISMO_TRX_DA_SX_SUB_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x000000ff ) >> 0) #define GET_DB_TURISMO_TRX_DA_SX_VCO_ISEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00000f00 ) >> 8) #define GET_DB_TURISMO_TRX_VO_AAC_COMPOUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00001000 ) >> 12) #define GET_DB_TURISMO_TRX_SX_TTL_VT_DET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x0000c000 ) >> 14) #define GET_DB_TURISMO_TRX_AD_DP_VT_MON_Q (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00030000 ) >> 16) #define GET_DB_TURISMO_TRX_AD_IOT_ADC_OUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x3ff00000 ) >> 20) #define GET_DB_TURISMO_TRX_SX_SBCAL_NCOUNT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0x0000ffff ) >> 0) #define GET_DB_TURISMO_TRX_SX_SBCAL_NTARGET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0xffff0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_TX_TRSW_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_5G_EN_TX_TRSW (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_5G_RX_LNA_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_5G_EN_RX_LNA (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_5G_RX_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_5G_EN_RX_MIXER (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_5G_RX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_5G_EN_RX_DIV2 (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_5G_EN_RX_LOBUF (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_5G_RX_TZ_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_5G_EN_RX_TZ (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_5G_TX_PA_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_EN_TX_PA (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_5G_TX_MOD_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_5G_EN_TX_MOD (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_5G_TX_DIV2_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_5G_EN_TX_DIV2 (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_EN_RX_IQCAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_5G_TX_DPD_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_5G_EN_TX_DPD (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_5G_EN_TX_TSSI (((REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_TURISMO_TRX_EN_LDO_5G_CP_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_EN_LDO_5G_LO_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_EN_IREF_RX (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP (((REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_5G_RX_SCA_MANUAL (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_5G_RX_SCA_MA (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x0000000e ) >> 1) #define GET_RG_TURISMO_TRX_5G_RX_SCA_LOAD (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000070 ) >> 4) #define GET_RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_5G_RX_LNA_SETTLE (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_5G_RX_GM_IDB (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_GM_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00006000 ) >> 13) #define GET_RG_TURISMO_TRX_5G_RX_DIV2_BUF (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RX_DIV2_CML (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x000c0000 ) >> 18) #define GET_RG_TURISMO_TRX_5G_RX_DIV_CMLISEL (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2 (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_5G_RX_TZ_COURSE (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_TX_DPDGM_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) & 0xf0000000 ) >> 28) #define GET_RG_TURISMO_TRX_5G_TX_DPD_DIV (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_5G_TX_TSSI_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00000070 ) >> 4) #define GET_RG_TURISMO_TRX_5G_TX_TSSI_DIV (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TX_TSSI_TEST (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_5G_RX_ADC_ICMP (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RX_ADC_VCMI (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x000c0000 ) >> 18) #define GET_RG_TURISMO_TRX_5G_RX_ADC_CLOAD (((REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_5G_TXPGA_CAPSW (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x0000000e ) >> 1) #define GET_RG_TURISMO_TRX_5G_TX_ADDGMCELL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_5G_PACELL_EN (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x000000e0 ) >> 5) #define GET_RG_TURISMO_TRX_5G_PABIAS_CTRL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TX_PAFB_EN (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_TX_PA1_VCAS (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x0000e000 ) >> 13) #define GET_RG_TURISMO_TRX_5G_TX_PA2_VCAS (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_TX_PA3_VCAS (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2 (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_5G_TX_DIV_CMLISEL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_TX_DIV_VSET (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_TURISMO_TRX_5G_TX_LOBUF_VSET (((REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_TURISMO_TRX_5G_TXPGA_MAIN (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_TXPGA_STEER (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_TURISMO_TRX_5G_TXMOD_GMCELL (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_TX_GAIN_OFFSET (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_TX_GAIN (((REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) & 0x07f00000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_RX_HG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RX_HG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_RX_HG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_RX_HG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_5G_RX_MG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RX_MG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_RX_MG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_RX_MG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_5G_RX_LG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RX_LG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_RX_LG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_RX_LG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_5G_RX_ULG_LNA_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RX_ULG_SQDC (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_RX_ULG_TZI (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM (((REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_5G_TX_DACI1ST (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_TURISMO_TRX_5G_TX_DACLPF_IFINE (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_5G_TX_DACLPF_VCM (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_TURISMO_TRX_5G_TX_DAC_IBIAS (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TX_DAC_IATTN (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_5G_TXLPF_BOOSTI (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_5G_TX_DAC_RCAL (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_5G_TX_DAC_OS (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_TX_DAC_IOFFSET (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_TX_DAC_QOFFSET (((REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX5GB_RFCTRL_F (((REG32(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0 (((REG32(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8 (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_SX5GB_LO_TIMES (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_SX5GB_CHANNEL (((REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0000ff00 ) >> 8) #define GET_RG_TURISMO_TRX_SX_5GB_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SX_5GB_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_SX5GB_CP_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_EN_SX5GB_CP (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_EN_SX5GB_DIV_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_EN_SX5GB_DIV (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_EN_SX5GB_VCO_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_EN_SX5GB_VCO (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_SX5GB_PFD_RST_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_SX5GB_PFD_RST (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX5GB_UOP_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_SX5GB_UOP_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_SX5GB_HSDIV (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_EN_SX_MIX_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_EN_SX_MIX (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_EN_SX_REP_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_EN_SX_REP (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_AW (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX5GB_VOAAC_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_SX5GB_MIXAAC_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_SX5GB_REPAAC_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_SX5GB_TTL_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_SX5GB_CAL_INIT (((REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0xe0000000 ) >> 29) #define GET_RG_TURISMO_TRX_EN_SX5GB_LDO_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_EN_LDO_5G_CP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_LDO_5G_DIV (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_EN_LDO_5G_LO (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33 (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_SX5GB_LDO_FCOFFT (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TURISMO_TRX_LDO_5G_CP_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_LDO_5G_CP_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_LDO_5G_DIV_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_LDO_5G_LO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_LDO_5G_LO_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_LDO_5G_VCO_FC (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_LDO_5G_VCO_RCF (((REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_TURISMO_TRX_SX5GB_CP_ISEL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_CP_ISEL50U (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_SX5GB_CP_KP_DOUB (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_SX5GB_CP_IOST_POL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000080 ) >> 7) #define GET_RG_TURISMO_TRX_SX5GB_CP_IOST (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_SX5GB_PFD_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_SX5GB_PFD_SET (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_SX5GB_PFD_SET1 (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_SX5GB_PFD_SET2 (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_SX5GB_PFD_TRUP (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_SX5GB_PFD_TRDN (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_SX5GB_PFD_TLSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE (((REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_SX5GB_LPF_C1 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_LPF_C2 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_SX5GB_LPF_C3 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_SX5GB_LPF_R2 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00001e00 ) >> 9) #define GET_RG_TURISMO_TRX_SX5GB_LPF_R3 (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x0000e000 ) >> 13) #define GET_RG_TURISMO_TRX_SX5GB_TTL_INIT (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_SX5GB_TTL_FPT (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x000c0000 ) >> 18) #define GET_RG_TURISMO_TRX_SX5GB_TTL_CPT (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_SX5GB_TTL_ACCUM (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_SX5GB_TTL_SUB (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX5GB_TTL_SUB_INV (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_SX5GB_TTL_VH (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x18000000 ) >> 27) #define GET_RG_TURISMO_TRX_SX5GB_TTL_VL (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x60000000 ) >> 29) #define GET_RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST (((REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_VCO_ISEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x0000001e ) >> 1) #define GET_RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x000001c0 ) >> 6) #define GET_RG_TURISMO_TRX_SX5GB_VCO_KVDOUB (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX5GB_VCO_VARBSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00001800 ) >> 11) #define GET_RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_SX5GB_VCO_CS_AWH (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_HSDIV_INBFSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00018000 ) >> 15) #define GET_RG_TURISMO_TRX_HSDIV_OBFMX_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_HSDIV_OBFSX_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_HSDIV_VRSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00180000 ) >> 19) #define GET_RG_TURISMO_TRX_SXMIX_IBIAS_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x00600000 ) >> 21) #define GET_RG_TURISMO_TRX_SXMIX_SWB_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x01800000 ) >> 23) #define GET_RG_TURISMO_TRX_SXMIX_GMSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x06000000 ) >> 25) #define GET_RG_TURISMO_TRX_SXREP_SWB_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x18000000 ) >> 27) #define GET_RG_TURISMO_TRX_SXREP_CSSEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x60000000 ) >> 29) #define GET_RG_TURISMO_TRX_EN_SX5GB_VCOMON (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_SX5GB_DIV_PREVDD (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_DIV_PSCVDD (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_SX5GB_DIV_RST_H (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_EN_SX5GB_MOD (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_EN_SX5GB_DITHER (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SX5GB_MOD_ORDER (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00180000 ) >> 19) #define GET_RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT (((REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) & 0x00600000 ) >> 21) #define GET_RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SX5GB_SUB_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x000001fe ) >> 1) #define GET_RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_CT (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_WT (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0x00008000 ) >> 15) #define GET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG (((REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) & 0xffff0000 ) >> 16) #define GET_RG_TURISMO_TRX_SX5GB_VOAAC_TAR (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_VO5GB_AAC_IOST (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_VO5GB_AAC_IMAX (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x000003c0 ) >> 6) #define GET_RG_TURISMO_TRX_SX5GB_AAC_ACCUMH (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000c00 ) >> 10) #define GET_RG_TURISMO_TRX_SX5GB_AAC_ACCUML (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_SX5GB_AAC_INIT (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000c000 ) >> 14) #define GET_RG_TURISMO_TRX_SX5GB_AAC_EVA_TS (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00030000 ) >> 16) #define GET_RG_TURISMO_TRX_SX5GB_AAC_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SX5GB_AAC_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_SX5GB_AAC_EVA (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_AAC5GB_TAR_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_EN_AAC5GB_VOPDSW (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_EN_AAC5GB_MXPDSW (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_EN_AAC5GB_RPPDSW (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_SX5GB_AAC_TEST_EN (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_SX5GB_MIXAAC_TAR (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_SXMIX_SCA_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x00000fc0 ) >> 6) #define GET_RG_TURISMO_TRX_SX5GB_REPAAC_TAR (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x0001e000 ) >> 13) #define GET_RG_TURISMO_TRX_SXREP_SCA_SEL_MAN (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SXREP_SCA_SEL (((REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) & 0x01f80000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0 (((REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24) #define GET_RG_TURISMO_TRX_SX5GB_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_5G_TXDAC_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_5G_TXRF_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TXPA_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_RXRF_DELAY (((REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_TURISMO_TRX_5G_TXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TXPA_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RXRF_T2R_DELAY (((REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_TURISMO_TRX_5G_TXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TXPA_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_RXRF_R2T_DELAY (((REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_RX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_5G_TX_DCCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TURISMO_TRX_5G_TX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_5G_RX_IQCAL_DELAY (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_5G_PGAG_TXCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_5G_TX_GAIN_TXCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x7f000000 ) >> 24) #define GET_RG_TURISMO_TRX_5G_PGAG_RCCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_5G_RFG_RXIQCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00000030 ) >> 4) #define GET_RG_TURISMO_TRX_5G_PGAG_RXIQCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x000003c0 ) >> 6) #define GET_RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0001fc00 ) >> 10) #define GET_RG_TURISMO_TRX_5G_RFG_DPDCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00060000 ) >> 17) #define GET_RG_TURISMO_TRX_5G_PGAG_DPDCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00780000 ) >> 19) #define GET_RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL (((REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) & 0x3f800000 ) >> 23) #define GET_DB_TURISMO_TRX_DA_SX5GB_SUB_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x000000ff ) >> 0) #define GET_DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00000f00 ) >> 8) #define GET_DB_TURISMO_TRX_DA_SXMIX_SCA_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x0007e000 ) >> 13) #define GET_DB_TURISMO_TRX_DA_SXMIX_GMSEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00180000 ) >> 19) #define GET_DB_TURISMO_TRX_DA_SXREP_SCA_SEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x07e00000 ) >> 21) #define GET_DB_TURISMO_TRX_DA_SXREP_CSSEL (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x18000000 ) >> 27) #define GET_DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0x20000000 ) >> 29) #define GET_DB_TURISMO_TRX_SX5GB_TTL_VT_DET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) & 0xc0000000 ) >> 30) #define GET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A1 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x0000003f ) >> 0) #define GET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A2 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x00001f80 ) >> 7) #define GET_DB_TURISMO_TRX_SXREP_SCA_SEL_B1 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x000fc000 ) >> 14) #define GET_DB_TURISMO_TRX_SXREP_SCA_SEL_B2 (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) & 0x07e00000 ) >> 21) #define GET_DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3)) & 0x0000ffff ) >> 0) #define GET_DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET (((REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3)) & 0xffff0000 ) >> 16) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP0 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP1 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP2 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP3 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP4 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP5 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_RX_SCAMA_STEP6 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP0 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP1 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP2 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP3 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP4 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP5 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_RX_SCALOAD_STEP6 (((REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP0 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x0000000f ) >> 0) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP1 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP2 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP3 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP4 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x000f0000 ) >> 16) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP5 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_TX_CAPSW_STEP6 (((REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_NFRAC_DELTA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) & 0x00ffffff ) >> 0) #define GET_RG_TURISMO_TRX_40M_MODE (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_LO_UP_CH (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_BT_TRX_IF (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_1)) & 0x07ff0000 ) >> 16) #define GET_RG_TURISMO_TRX_RX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x0000001f ) >> 0) #define GET_RG_TURISMO_TRX_RX_IQ_THETA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00001f00 ) >> 8) #define GET_RG_TURISMO_TRX_RX_IQ_MANUAL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_RXIQ_NOSHRK (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_RX_RSSIADC_TH (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x00f00000 ) >> 20) #define GET_RG_TURISMO_TRX_SUB_DC (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_IOT_ADC_EDGE_SEL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_RSSI_EDGE_SEL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_ADC_EDGE_SEL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_Q_INV (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_I_INV (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_IQ_SWAP (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_SIGN_SWAP (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_TX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x0000001f ) >> 0) #define GET_RG_TURISMO_TRX_TX_IQ_THETA (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00001f00 ) >> 8) #define GET_RG_TURISMO_TRX_TX_IQ_MANUAL (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_TXIQ_NOSHRK (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_TX_IQCAL_TIME (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_TX_FREQ_OFFSET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x0000ffff ) >> 0) #define GET_RG_TURISMO_TRX_TONE_SCALE (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x01ff0000 ) >> 16) #define GET_RG_TURISMO_TRX_BB_SIG_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_TONE_GEN_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_TX_UP8X_MAN_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_DIS_DAC_OFFSET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_CLK_320M_INV (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_DPLL_CLK320BY2 (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_CBW_20_40 (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_DAC_DC_Q (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5)) & 0x000003ff ) >> 0) #define GET_RG_TURISMO_TRX_DAC_DC_I (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5)) & 0x03ff0000 ) >> 16) #define GET_RG_TURISMO_TRX_DAC_Q_SET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x000003ff ) >> 0) #define GET_RG_TURISMO_TRX_DAC_MAN_Q_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_DAC_I_SET (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x03ff0000 ) >> 16) #define GET_RG_TURISMO_TRX_DAC_MAN_I_EN (((REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_01 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00)) & 0x00001fff ) >> 0) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_00 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00)) & 0x1fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_03 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01)) & 0x00001fff ) >> 0) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_02 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01)) & 0x1fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_05 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02)) & 0x00001fff ) >> 0) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_04 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02)) & 0x1fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_07 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03)) & 0x00001fff ) >> 0) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_06 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03)) & 0x1fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_09 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04)) & 0x00001fff ) >> 0) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_08 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04)) & 0x1fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_11 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05)) & 0x00001fff ) >> 0) #define GET_RG_TURISMO_TRX_BW20_HB_COEF_10 (((REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05)) & 0x1fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_PHASE_STEP_VALUE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x0000ffff ) >> 0) #define GET_RG_TURISMO_TRX_PHASE_MANUAL (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_ALPHA_SEL (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x00300000 ) >> 20) #define GET_RG_TURISMO_TRX_SPECTRUM_BW (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_SPECTRUM_EN (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) & 0x10000000 ) >> 28) #define GET_RO_TURISMO_TRX_WF_DCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00010000 ) >> 16) #define GET_RO_TURISMO_TRX_BT_DCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00020000 ) >> 17) #define GET_RO_TURISMO_TRX_RCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00040000 ) >> 18) #define GET_RO_TURISMO_TRX_TXDC_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00080000 ) >> 19) #define GET_RO_TURISMO_TRX_TXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00100000 ) >> 20) #define GET_RO_TURISMO_TRX_RXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00200000 ) >> 21) #define GET_RO_TURISMO_TRX_5G_TXDC_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00400000 ) >> 22) #define GET_RO_TURISMO_TRX_5G_TXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x00800000 ) >> 23) #define GET_RO_TURISMO_TRX_5G_RXIQ_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x01000000 ) >> 24) #define GET_RO_TURISMO_TRX_5G_DCCAL_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x02000000 ) >> 25) #define GET_RO_TURISMO_TRX_PRE_DC_DONE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_PHASE_17P5M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_2)) & 0x0000ffff ) >> 0) #define GET_RG_TURISMO_TRX_PHASE_2P5M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_2)) & 0xffff0000 ) >> 16) #define GET_RG_TURISMO_TRX_PHASE_RXIQ_1M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_3)) & 0x0000ffff ) >> 0) #define GET_RG_TURISMO_TRX_PHASE_1M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_3)) & 0xffff0000 ) >> 16) #define GET_RG_TURISMO_TRX_PHASE_PADPD (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_4)) & 0x0000ffff ) >> 0) #define GET_RG_TURISMO_TRX_PHASE_35M (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_4)) & 0xffff0000 ) >> 16) #define GET_RO_TURISMO_TRX_RX_IQ_THETA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x0000001f ) >> 0) #define GET_RO_TURISMO_TRX_RX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x00001f00 ) >> 8) #define GET_RO_TURISMO_TRX_TX_IQ_THETA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x001f0000 ) >> 16) #define GET_RO_TURISMO_TRX_TX_IQ_ALPHA (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) & 0x1f000000 ) >> 24) #define GET_RG_TURISMO_TRX_RX_RCCAL_TARG (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x000003ff ) >> 0) #define GET_RG_TURISMO_TRX_RX_DC_POLAR_INV (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_RCCAL_POLAR_INV (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_RX_DC_RESOLUTION (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_RX_RCCAL_40M_TARG (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) & 0x03ff0000 ) >> 16) #define GET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32 (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) & 0x000000ff ) >> 0) #define GET_RG_TURISMO_TRX_SPECTRUM_LO_FIX (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) & 0x00100000 ) >> 20) #define GET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0 (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_8)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_PROC_DELAY (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_PRE_DC_POLA_INV (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_PRE_DC_AUTO (((REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_HS3W_TX_RF_GAIN (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x0000007f ) >> 0) #define GET_RG_TURISMO_TRX_HS3W_PGAGC (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_HS3W_RFGC (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00003000 ) >> 12) #define GET_RG_TURISMO_TRX_HS3W_RXAGC (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_HS3W_RF_PHY_MODE (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_HS3W_MANUAL (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_HS3W_COMM_DATA (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x07000000 ) >> 24) #define GET_RG_TURISMO_TRX_HS3W_START_SENT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8 (((REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) & 0x0007f800 ) >> 11) #define GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT (((REG32(ADR_TURISMO_TRX_HS3W_CTRL3)) & 0x00ffffff ) >> 0) #define GET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0 (((REG32(ADR_TURISMO_TRX_HS3W_CTRL3)) & 0xff000000 ) >> 24) #define GET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE (((REG32(ADR_TURISMO_TRX_RF_D_MODE_CTRL)) & 0x00000001 ) >> 0) #define GET_RO_TURISMO_TRX_DC_CAL_Q (((REG32(ADR_TURISMO_TRX_RX_DC_CAL_RESULT)) & 0x0000007f ) >> 0) #define GET_RO_TURISMO_TRX_DC_CAL_I (((REG32(ADR_TURISMO_TRX_RX_DC_CAL_RESULT)) & 0x007f0000 ) >> 16) #define GET_RG_TURISMO_TRX_XO_LDO_LEVEL (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000007 ) >> 0) #define GET_RG_TURISMO_TRX_EN_LDO_XO_IQUP (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_EN_LDO_XO_BYP (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_EN_DLDO_BYP (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_XO_CBANKI (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x0001ff00 ) >> 8) #define GET_RG_TURISMO_TRX_XO_CBANKO (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x03fe0000 ) >> 17) #define GET_RG_TURISMO_TRX_EN_FDB (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_FDB_BYPASS (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x08000000 ) >> 27) #define GET_RG_TURISMO_TRX_FDB_DUTY_LTH (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x30000000 ) >> 28) #define GET_RG_TURISMO_TRX_EN_XOTEST (((REG32(ADR_TURISMO_TRX_PMU_REG_1)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_EN_FDB_DCC_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000008 ) >> 3) #define GET_RG_TURISMO_TRX_FDB_PHASESWAP_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_FDB_CDELAY_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_FDB_FDELAY_MUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x0000f000 ) >> 12) #define GET_RG_TURISMO_TRX_XO_TIMMER (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x003f0000 ) >> 16) #define GET_RG_TURISMO_TRX_DPL_SETTLING_TIMMER (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x00c00000 ) >> 22) #define GET_RG_TURISMO_TRX_FDB_RDELAYF (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x03000000 ) >> 24) #define GET_RG_TURISMO_TRX_FDB_RDELAYS (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x0c000000 ) >> 26) #define GET_RG_TURISMO_TRX_FDB_RECAL_TIMMER (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x30000000 ) >> 28) #define GET_RG_TURISMO_TRX_EN_FDB_RECAL (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY (((REG32(ADR_TURISMO_TRX_PMU_REG_2)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_DCDC_MODE (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_DLDO_LEVEL (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x0000000e ) >> 1) #define GET_RG_TURISMO_TRX_BUCK_LEVEL (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x000000f0 ) >> 4) #define GET_RG_TURISMO_TRX_DLDO_BOOST_IQ (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_BUCK_EN_PSM (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_BUCK_PSM_VTH (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_BUCK_VREF_SEL (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00000800 ) >> 11) #define GET_RG_TURISMO_TRX_LDO_LEVEL_EFUSE (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_EN_LDO_EFUSE (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_DCDC_PULLLOW_CON (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_DCDC_RES2_CON (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00080000 ) >> 19) #define GET_RG_TURISMO_TRX_DCDC_RES_CON (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_RTC_RS1 (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_RTC_RS2 (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_DCDC_CLK (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x0f000000 ) >> 24) #define GET_RG_TURISMO_TRX_BUCK_RCZERO (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_BUCK_SLOP (((REG32(ADR_TURISMO_TRX_PMU_REG_3)) & 0x60000000 ) >> 29) #define GET_RG_TURISMO_TRX_RTC_OFFSET (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x000000ff ) >> 0) #define GET_RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x000fff00 ) >> 8) #define GET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x3ff00000 ) >> 20) #define GET_RG_TURISMO_TRX_RTC_CAL_MODE (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_SEL_DPLL_CLK (((REG32(ADR_TURISMO_TRX_PMU_REG_4)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_TURISMO_TRX_PMU_REG_5)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_EN_RTC_CAL (((REG32(ADR_TURISMO_TRX_PMU_REG_5)) & 0x00000002 ) >> 1) #define GET_RO_TURISMO_TRX_FDB_CDELAY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x0000000f ) >> 0) #define GET_RO_TURISMO_TRX_FDB_FDELAY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x000000f0 ) >> 4) #define GET_RO_TURISMO_TRX_FDB_PHASESWAP (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x00000100 ) >> 8) #define GET_RO_TURISMO_TRX_XO_RDY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x00000200 ) >> 9) #define GET_RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x00000400 ) >> 10) #define GET_RO_TURISMO_TRX_RTC_OSC_RES_SW (((REG32(ADR_TURISMO_TRX_PMU_REG_6)) & 0x001ff800 ) >> 11) #define GET_RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_SLEEP_METHOD (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_INT_PMU_MASK (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_SLEEP_WAKE_CNT (((REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_2)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_SEC_CNT_VALUE (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) & 0x00007fff ) >> 0) #define GET_RG_TURISMO_TRX_RTC_EN (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) & 0x00008000 ) >> 15) #define GET_RO_TURISMO_TRX_RTC_TICK_CNT (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) & 0x7fff0000 ) >> 16) #define GET_RG_TURISMO_TRX_RTC_INT_SEC_MASK (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_RTC_INT_ALARM_MASK (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00000002 ) >> 1) #define GET_RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00007000 ) >> 12) #define GET_RO_TURISMO_TRX_RTC_INT_SEC (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00010000 ) >> 16) #define GET_RO_TURISMO_TRX_RTC_INT_ALARM (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_RTC_SEC_START_CNT (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_2)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE (((REG32(ADR_TURISMO_TRX_PMU_RTC_REG_3)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN (((REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_CLK_RTC_SW (((REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_PHY_RST_N (((REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) & 0x00000010 ) >> 4) #define GET_RO_TURISMO_TRX_PMU_STATE (((REG32(ADR_TURISMO_TRX_PMU_STATE_REG)) & 0x00000007 ) >> 0) #define GET_RO_TURISMO_TRX_AD_VBAT_OK (((REG32(ADR_TURISMO_TRX_PMU_STATE_REG)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_BT_CLK_SW (((REG32(ADR_TURISMO_TRX_PMU_BT_CLK)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_BT_CLK32K_CAL_DONE (((REG32(ADR_TURISMO_TRX_PMU_BT_CLK)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_GPIO16_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_GPIO16_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_GPIO16_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_GPIO17_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_GPIO17_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_GPIO17_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_GPIO18_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_GPIO18_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_GPIO18_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_GPIO19_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_GPIO19_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_GPIO19_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_GPIO20_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_GPIO20_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_GPIO20_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_SPIS_MISO_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE (((REG32(ADR_TURISMO_TRX_IO_REG_0)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_GPIO08_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_GPIO08_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_GPIO08_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_GPIO09_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_GPIO09_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_GPIO09_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_GPIO10_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_GPIO10_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_GPIO10_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_GPIO11_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_GPIO11_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_GPIO11_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_GPIO12_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_GPIO12_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_GPIO12_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_GPIO13_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_GPIO13_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_GPIO13_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_GPIO14_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_GPIO14_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_GPIO14_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_GPIO15_DS (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_GPIO15_PD (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_GPIO15_OE (((REG32(ADR_TURISMO_TRX_IO_REG_1)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_GPIO00_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000001 ) >> 0) #define GET_RG_TURISMO_TRX_GPIO00_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000002 ) >> 1) #define GET_RG_TURISMO_TRX_GPIO00_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000004 ) >> 2) #define GET_RG_TURISMO_TRX_GPIO01_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000010 ) >> 4) #define GET_RG_TURISMO_TRX_GPIO01_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000020 ) >> 5) #define GET_RG_TURISMO_TRX_GPIO01_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000040 ) >> 6) #define GET_RG_TURISMO_TRX_GPIO02_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000100 ) >> 8) #define GET_RG_TURISMO_TRX_GPIO02_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000200 ) >> 9) #define GET_RG_TURISMO_TRX_GPIO02_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00000400 ) >> 10) #define GET_RG_TURISMO_TRX_GPIO03_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00001000 ) >> 12) #define GET_RG_TURISMO_TRX_GPIO03_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00002000 ) >> 13) #define GET_RG_TURISMO_TRX_GPIO03_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00004000 ) >> 14) #define GET_RG_TURISMO_TRX_GPIO04_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00010000 ) >> 16) #define GET_RG_TURISMO_TRX_GPIO04_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00020000 ) >> 17) #define GET_RG_TURISMO_TRX_GPIO04_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00040000 ) >> 18) #define GET_RG_TURISMO_TRX_GPIO05_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00100000 ) >> 20) #define GET_RG_TURISMO_TRX_GPIO05_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00200000 ) >> 21) #define GET_RG_TURISMO_TRX_GPIO05_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x00400000 ) >> 22) #define GET_RG_TURISMO_TRX_GPIO06_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x01000000 ) >> 24) #define GET_RG_TURISMO_TRX_GPIO06_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x02000000 ) >> 25) #define GET_RG_TURISMO_TRX_GPIO06_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x04000000 ) >> 26) #define GET_RG_TURISMO_TRX_GPIO07_DS (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x10000000 ) >> 28) #define GET_RG_TURISMO_TRX_GPIO07_PD (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x20000000 ) >> 29) #define GET_RG_TURISMO_TRX_GPIO07_OE (((REG32(ADR_TURISMO_TRX_IO_REG_2)) & 0x40000000 ) >> 30) #define GET_RG_TURISMO_TRX_RF_PHY_MODE_SEL (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00000003 ) >> 0) #define GET_RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00000070 ) >> 4) #define GET_RG_TURISMO_TRX_PAD_MUX_SEL (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00000f00 ) >> 8) #define GET_RG_TURISMO_TRX_MODE_LATCH_LMT (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00007000 ) >> 12) #define GET_RG_TURISMO_TRX_CLK_MON_SEL (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x00070000 ) >> 16) #define GET_RG_TURISMO_TRX_EXT_MCU_PWRUP (((REG32(ADR_TURISMO_TRX_MCU_REG_0)) & 0x80000000 ) >> 31) #define GET_RG_TURISMO_TRX_RAM_00 (((REG32(ADR_TURISMO_TRX_PMU_RAM_00)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_01 (((REG32(ADR_TURISMO_TRX_PMU_RAM_01)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_02 (((REG32(ADR_TURISMO_TRX_PMU_RAM_02)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_03 (((REG32(ADR_TURISMO_TRX_PMU_RAM_03)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_04 (((REG32(ADR_TURISMO_TRX_PMU_RAM_04)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_05 (((REG32(ADR_TURISMO_TRX_PMU_RAM_05)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_06 (((REG32(ADR_TURISMO_TRX_PMU_RAM_06)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_07 (((REG32(ADR_TURISMO_TRX_PMU_RAM_07)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_08 (((REG32(ADR_TURISMO_TRX_PMU_RAM_08)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_09 (((REG32(ADR_TURISMO_TRX_PMU_RAM_09)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_10 (((REG32(ADR_TURISMO_TRX_PMU_RAM_10)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_11 (((REG32(ADR_TURISMO_TRX_PMU_RAM_11)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_12 (((REG32(ADR_TURISMO_TRX_PMU_RAM_12)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_13 (((REG32(ADR_TURISMO_TRX_PMU_RAM_13)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_14 (((REG32(ADR_TURISMO_TRX_PMU_RAM_14)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_15 (((REG32(ADR_TURISMO_TRX_PMU_RAM_15)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_16 (((REG32(ADR_TURISMO_TRX_PMU_RAM_16)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_17 (((REG32(ADR_TURISMO_TRX_PMU_RAM_17)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_18 (((REG32(ADR_TURISMO_TRX_PMU_RAM_18)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_19 (((REG32(ADR_TURISMO_TRX_PMU_RAM_19)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_20 (((REG32(ADR_TURISMO_TRX_PMU_RAM_20)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_21 (((REG32(ADR_TURISMO_TRX_PMU_RAM_21)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_22 (((REG32(ADR_TURISMO_TRX_PMU_RAM_22)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_23 (((REG32(ADR_TURISMO_TRX_PMU_RAM_23)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_24 (((REG32(ADR_TURISMO_TRX_PMU_RAM_24)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_25 (((REG32(ADR_TURISMO_TRX_PMU_RAM_25)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_26 (((REG32(ADR_TURISMO_TRX_PMU_RAM_26)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_27 (((REG32(ADR_TURISMO_TRX_PMU_RAM_27)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_28 (((REG32(ADR_TURISMO_TRX_PMU_RAM_28)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_29 (((REG32(ADR_TURISMO_TRX_PMU_RAM_29)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_30 (((REG32(ADR_TURISMO_TRX_PMU_RAM_30)) & 0xffffffff ) >> 0) #define GET_RG_TURISMO_TRX_RAM_31 (((REG32(ADR_TURISMO_TRX_PMU_RAM_31)) & 0xffffffff ) >> 0) #define GET_RG_HW_PINSEL (((REG32(ADR_MODE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_HS_3WIRE_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_MODE_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_5G_TX_GAIN_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_RX_GAIN_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_TX_GAIN_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_TXGAIN_PHYCTRL (((REG32(ADR_MODE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_RX_AGC (((REG32(ADR_MODE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_MODE (((REG32(ADR_MODE_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_CAL_INDEX (((REG32(ADR_MODE_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_RFG (((REG32(ADR_MODE_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_PGAG (((REG32(ADR_MODE_REGISTER)) & 0x003c0000 ) >> 18) #define GET_RG_BW_HT40 (((REG32(ADR_MODE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_BW_MANUAL (((REG32(ADR_MODE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TX_GAIN (((REG32(ADR_MODE_REGISTER)) & 0x7f000000 ) >> 24) #define GET_RG_TX_TRSW_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_EN_TX_TRSW (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_RX_LNA_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_EN_RX_LNA (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_RX_MIXER_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_EN_RX_MIXER (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_RX_DIV2_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_EN_RX_DIV2 (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_RX_LOBUF_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_EN_RX_LOBUF (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_RX_TZ_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_EN_RX_TZ (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_RX_FILTER_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_EN_RX_FILTER (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_RX_ADC_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_EN_RX_ADC (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_RX_RSSI_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_EN_RX_RSSI (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TX_PA_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_EN_TX_PA (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_TX_MOD_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_EN_TX_MOD (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_TX_DAC_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_EN_TX_DAC (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_TX_DIV2_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_EN_TX_DIV2 (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_TX_DIV2_BUF_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_EN_TX_DIV2_BUF (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_TX_BT_PA_MANUAL (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_EN_TX_BT_PA (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_EN_IOT_ADC_BUF (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_EN_IOT_ADC (((REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_EN_LDO_RX_FE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_EN_LDO_AFE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_EN_IREF_RX (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_TX_DAC_CAL_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_EN_TX_DAC_CAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_RX_TZ_OUT_TRISTATE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TX_SELF_MIXER_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_EN_TX_SELF_MIXER (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_RX_IQCAL_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_EN_RX_IQCAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_TX_DPD_MANUAL (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_EN_TX_DPD (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_EN_TX_TSSI (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_EN_SARADC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_EN_TX_VTOI_2ND (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_TXLPF_BYPASS (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_TX_EN_VOLTAGE_IN (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_EN_TX_DAC_OUT (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_EN_TX_DAC_VOUT (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_RX_ABBOUT_TRI_STATE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_EN_RX_TESTNODE (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_EN_RX_PADSW (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_EN_LDO_RX_FE_FC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_EN_LDO_RX_AFE_FC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_EN_LDO_RX_FE_IQUP (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_EN_LDO_RX_AFE_IQUP (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_RX_SQDC (((REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_LDO_LEVEL_RX_FE (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_EN_LDO_RX_FE_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_LDO_LEVEL_AFE (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_EN_LDO_RX_AFE_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_SX_LDO_CP_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_EN_LDO_CP_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_SX_LDO_LO_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_EN_LDO_LO_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_SX_LDO_VCO_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_SX_LDO_DIV_LEVEL (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_EN_LDO_DIV_BYP (((REG32(ADR_2_4G_LDO_REGISTER)) & 0x80000000 ) >> 31) #define GET_RG_WF_RX_ABBCTUNE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_WF_RX_TZ_CMZ_C (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_WF_RX_FILTERI_COARSE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_WF_RX_FILTERI1ST (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_WF_RX_FILTERI2ND (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_WF_RX_FILTERI3RD (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_WF_RX_ABBCFIX (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_WF_RX_ABB_N_MODE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_WF_RX_ABB_BT_MODE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_WF_RX_ABB_IDIV3 (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_WF_RX_EN_IDACA_COARSE (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_WF_RX_EN_LOOPA (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_WF_RX_TZ_CMZ_R (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_WF_RX_FILTERVCM (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_WF_RX_OUTVCM (((REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_WF_N_RX_ABBCTUNE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_WF_N_RX_TZ_CMZ_C (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_WF_N_RX_FILTERI_COARSE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_WF_N_RX_FILTERI1ST (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_WF_N_RX_FILTERI2ND (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_WF_N_RX_FILTERI3RD (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_WF_N_RX_ABBCFIX (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_WF_N_RX_ABB_N_MODE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_WF_N_RX_ABB_BT_MODE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_WF_N_RX_ABB_IDIV3 (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_WF_N_RX_EN_IDACA_COARSE (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_WF_N_RX_EN_LOOPA (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_WF_N_RX_TZ_CMZ_R (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_WF_N_RX_FILTERVCM (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_WF_N_RX_OUTVCM (((REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_BT_RX_ABBCTUNE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_BT_RX_TZ_CMZ_C (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_BT_RX_FILTERI_COARSE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_BT_RX_FILTERI1ST (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_BT_RX_FILTERI2ND (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_BT_RX_FILTERI3RD (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_BT_RX_ABBCFIX (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00010000 ) >> 16) #define GET_RG_BT_RX_ABB_N_MODE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00020000 ) >> 17) #define GET_RG_BT_RX_ABB_BT_MODE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_BT_RX_ABB_IDIV3 (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_BT_RX_EN_IDACA_COARSE (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_BT_RX_EN_LOOPA (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_BT_RX_TZ_CMZ_R (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_BT_RX_FILTERVCM (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_BT_RX_OUTVCM (((REG32(ADR_BT_RX_FILTER_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_RX_ADCRSSI_VCM (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_RX_REC_LPFCORNER (((REG32(ADR_2_4G_RX_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_RX_ADCRSSI_CLKSEL (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_RSSI_CLOCK_GATING (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_RX_IDACA_COARSE_PMOS_ON (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_TX_DPDGM_BIAS (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_TX_DPD_DIV (((REG32(ADR_2_4G_RX_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_TX_TSSI_BIAS (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_TX_TSSI_DIV (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_TX_TSSI_TEST (((REG32(ADR_2_4G_RX_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_TX_TSSI_TESTMODE (((REG32(ADR_2_4G_RX_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_EN_RX_RSSI_TESTNODE (((REG32(ADR_2_4G_RX_REGISTER)) & 0x0e000000 ) >> 25) #define GET_RG_RX_LNA_TRI_SEL (((REG32(ADR_2_4G_RX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_RX_LNA_SETTLE (((REG32(ADR_2_4G_RX_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_WF_TXPGA_CAPSW (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_WF_TX_DIV_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_WF_TX_LOBUF_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_WF_TXMOD_GMCELL_FINE (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_BT_TXPGA_CAPSW (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_BT_TX_DIV_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_BT_TX_LOBUF_VSET (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_BT_TXMOD_GMCELL_FINE (((REG32(ADR_2_4G_TX_FE_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_WF_PACELL_EN (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_WF_PABIAS_CTRL (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_WF_TX_PA1_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_WF_TX_PA2_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_WF_TX_PA3_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_WF_BTPASW (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_BTRX_BTPASW (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_BTTX_BTPASW (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_BT_PABIAS_2X (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_BT_PABIAS_CTRL (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_BT_TX_PA_VCAS (((REG32(ADR_2_4G_TX_PA_REGISTER)) & 0x70000000 ) >> 28) #define GET_RG_TXPGA_MAIN (((REG32(ADR_2_4G_TX_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_TXPGA_STEER (((REG32(ADR_2_4G_TX_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_TXMOD_GMCELL (((REG32(ADR_2_4G_TX_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_TXLPF_GMCELL (((REG32(ADR_2_4G_TX_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_WF_TX_GAIN_OFFSET (((REG32(ADR_2_4G_TX_REGISTER)) & 0x000f0000 ) >> 16) #define GET_RG_BT_TX_GAIN_OFFSET (((REG32(ADR_2_4G_TX_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_TX_VTOI_CURRENT (((REG32(ADR_2_4G_TX_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_TX_VTOI_GM (((REG32(ADR_2_4G_TX_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_TX_VTOI_OPTION (((REG32(ADR_2_4G_TX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_TX_VTOI_FS (((REG32(ADR_2_4G_TX_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_WF_RX_HG_LNA_GC (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_WF_RX_HG_TZ_GC (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_WF_RX_HG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_WF_RX_HG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_WF_RX_HG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_WF_RX_HG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_WF_RX_HG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_WF_RX_HG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_WF_RX_HG_LOBUF (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_WF_RX_HG_TZI (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_WF_RX_HG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_WF_RX_MG_LNA_GC (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_WF_RX_MG_TZ_GC (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_WF_RX_MG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_WF_RX_MG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_WF_RX_MG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_WF_RX_MG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_WF_RX_MG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_WF_RX_MG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_WF_RX_MG_LOBUF (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_WF_RX_MG_TZI (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_WF_RX_MG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_WF_RX_LG_LNA_GC (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_WF_RX_LG_TZ_GC (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_WF_RX_LG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_WF_RX_LG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_WF_RX_LG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_WF_RX_LG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_WF_RX_LG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_WF_RX_LG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_WF_RX_LG_LOBUF (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_WF_RX_LG_TZI (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_WF_RX_LG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_WF_RX_ULG_LNA_GC (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_WF_RX_ULG_TZ_GC (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_WF_RX_ULG_LNAHGN_BIAS (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_WF_RX_ULG_LNAHGP_BIAS (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_WF_RX_ULG_LNALG_BIAS (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_WF_RX_ULG_TZ_CAP (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_WF_RX_ULG_TZ_GC_BOOST (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_WF_RX_ULG_DIV2_CORE (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_WF_RX_ULG_LOBUF (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_WF_RX_ULG_TZI (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_WF_RX_ULG_TZ_VCM (((REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_BT_RX_HG_LNA_GC (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_BT_RX_HG_TZ_GC (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_BT_RX_HG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_BT_RX_HG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_BT_RX_HG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_BT_RX_HG_TZ_CAP (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_BT_RX_HG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_BT_RX_HG_DIV2_CORE (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_BT_RX_HG_LOBUF (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_BT_RX_HG_TZI (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_BT_RX_HG_TZ_VCM (((REG32(ADR_BT_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_BT_RX_MG_LNA_GC (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_BT_RX_MG_TZ_GC (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_BT_RX_MG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_BT_RX_MG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_BT_RX_MG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_BT_RX_MG_TZ_CAP (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_BT_RX_MG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_BT_RX_MG_DIV2_CORE (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_BT_RX_MG_LOBUF (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_BT_RX_MG_TZI (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_BT_RX_MG_TZ_VCM (((REG32(ADR_BT_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_BT_RX_LG_LNA_GC (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_BT_RX_LG_TZ_GC (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_BT_RX_LG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_BT_RX_LG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_BT_RX_LG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_BT_RX_LG_TZ_CAP (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_BT_RX_LG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_BT_RX_LG_DIV2_CORE (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_BT_RX_LG_LOBUF (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_BT_RX_LG_TZI (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_BT_RX_LG_TZ_VCM (((REG32(ADR_BT_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_BT_RX_ULG_LNA_GC (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_BT_RX_ULG_TZ_GC (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_BT_RX_ULG_LNAHGN_BIAS (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_BT_RX_ULG_LNAHGP_BIAS (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_BT_RX_ULG_LNALG_BIAS (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_BT_RX_ULG_TZ_CAP (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_BT_RX_ULG_TZ_GC_BOOST (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_BT_RX_ULG_DIV2_CORE (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_BT_RX_ULG_LOBUF (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_BT_RX_ULG_TZI (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_BT_RX_ULG_TZ_VCM (((REG32(ADR_BT_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_RX_ADC_CLKSEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_RX_ADC_DNLEN (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_RX_ADC_METAEN (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_RX_ADC_TFLAG (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_RX_ADC_TSEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_WF_RX_ADC_ICMP (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_WF_RX_ADC_VCMI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00000c00 ) >> 10) #define GET_RG_WF_RX_ADC_CLOAD (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_WF_RX_ADC_PSW (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_BT_RX_ADC_ICMP (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00030000 ) >> 16) #define GET_RG_BT_RX_ADC_VCMI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x000c0000 ) >> 18) #define GET_RG_BT_RX_ADC_CLOAD (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00300000 ) >> 20) #define GET_RG_BT_RX_ADC_PSW (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_SARADC_5G_TSSI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_SARADC_VRSEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_EN_SAR_TEST (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_SARADC_THERMAL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_SARADC_TSSI (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_CLK_SAR_SEL (((REG32(ADR_WBT_RX_ADC_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_WF_TX_DACI1ST (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_WF_TX_DACLPF_ICOARSE (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_WF_TX_DACLPF_IFINE (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_WF_TX_DACLPF_VCM (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_WF_TX_DAC_IBIAS (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_WF_TX_DAC_IATTN (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_WF_TXLPF_BOOSTI (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_WF_TX_DAC_RCAL (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_WF_TX_DAC_CKEDGE_SEL (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_WF_TX_DAC_OS (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_WF_TX_DAC_IOFFSET (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_WF_TX_DAC_QOFFSET (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_TX_DAC_TSEL (((REG32(ADR_WIFI_TX_DAC_REGISTER)) & 0xf0000000 ) >> 28) #define GET_RG_BT_TX_DACI1ST (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_BT_TX_DACLPF_ICOARSE (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_BT_TX_DACLPF_IFINE (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_BT_TX_DACLPF_VCM (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_BT_TX_DAC_IBIAS (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_BT_TX_DAC_IATTN (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_BT_TXLPF_BOOSTI (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_BT_TX_DAC_RCAL (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_BT_TX_DAC_CKEDGE_SEL (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_BT_TX_DAC_OS (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_BT_TX_DAC_IOFFSET (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_BT_TX_DAC_QOFFSET (((REG32(ADR_BT_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_SX_EN_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000001 ) >> 0) #define GET_RG_SX_EN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000002 ) >> 1) #define GET_RG_EN_SX_CP_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000004 ) >> 2) #define GET_RG_EN_SX_CP (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000008 ) >> 3) #define GET_RG_EN_SX_DIV_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000010 ) >> 4) #define GET_RG_EN_SX_DIV (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000020 ) >> 5) #define GET_RG_EN_SX_VCO_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000040 ) >> 6) #define GET_RG_EN_SX_VCO (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000080 ) >> 7) #define GET_RG_SX_PFD_RST_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000100 ) >> 8) #define GET_RG_SX_PFD_RST (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000200 ) >> 9) #define GET_RG_SX_UOP_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000400 ) >> 10) #define GET_RG_SX_UOP_EN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00000800 ) >> 11) #define GET_RG_EN_VCOBF_TXMB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00001000 ) >> 12) #define GET_RG_EN_VCOBF_TXMB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00002000 ) >> 13) #define GET_RG_EN_VCOBF_TXOB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00004000 ) >> 14) #define GET_RG_EN_VCOBF_TXOB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00008000 ) >> 15) #define GET_RG_EN_VCOBF_RXMB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00010000 ) >> 16) #define GET_RG_EN_VCOBF_RXMB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00020000 ) >> 17) #define GET_RG_EN_VCOBF_RXOB_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00040000 ) >> 18) #define GET_RG_EN_VCOBF_RXOB (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00080000 ) >> 19) #define GET_RG_EN_VCOBF_DIVCK_MAN (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00100000 ) >> 20) #define GET_RG_EN_VCOBF_DIVCK (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00200000 ) >> 21) #define GET_RG_SX_SBCAL_DIS (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x00800000 ) >> 23) #define GET_RG_SX_SBCAL_AW (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x01000000 ) >> 24) #define GET_RG_SX_AAC_DIS (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x04000000 ) >> 26) #define GET_RG_SX_TTL_DIS (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0x08000000 ) >> 27) #define GET_RG_SX_CAL_INIT (((REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) & 0xe0000000 ) >> 29) #define GET_RG_EN_SX_LDO_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_EN_LDO_CP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_EN_LDO_DIV (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_EN_LDO_LO (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_EN_LDO_VCO (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_EN_LDO_VCO_PSW (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_EN_LDO_VCO_VDD33 (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_EN_LDO_CP_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_EN_LDO_DIV_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_EN_LDO_LO_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_EN_LDO_VCO_IQUP (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_SX_LDO_FCOFFT (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_LDO_CP_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_LDO_CP_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_LDO_DIV_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_LDO_DIV_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_LDO_LO_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_LDO_LO_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_LDO_VCO_FC_MAN (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_LDO_VCO_FC (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_LDO_VCO_RCF (((REG32(ADR_SX_2_4G_LDO_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_SX_RFCTRL_F (((REG32(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0) #define GET_RG_SX_RFCTRL_CH_7_0 (((REG32(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24) #define GET_RG_SX_RFCTRL_CH_10_8 (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0) #define GET_RG_SX_RFCH_MAP_EN (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000008 ) >> 3) #define GET_RG_SX_FREF_DOUB_MAN (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000040 ) >> 6) #define GET_RG_SX_FREF_DOUB (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000080 ) >> 7) #define GET_RG_SX_BTRX_SIDE (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000100 ) >> 8) #define GET_RG_SX_LO_TIMES (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000200 ) >> 9) #define GET_RG_SX_CHANNEL (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0007f800 ) >> 11) #define GET_RG_SX_XTAL_FREQ (((REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00f00000 ) >> 20) #define GET_RG_SX_CP_ISEL_BT (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x0000000f ) >> 0) #define GET_RG_SX_CP_ISEL50U_BT (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000010 ) >> 4) #define GET_RG_SX_CP_KP_DOUB_BT (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000020 ) >> 5) #define GET_RG_SX_CP_ISEL_WF (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000780 ) >> 7) #define GET_RG_SX_CP_ISEL50U_WF (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00000800 ) >> 11) #define GET_RG_SX_CP_KP_DOUB_WF (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00001000 ) >> 12) #define GET_RG_SX_CP_IOST_POL (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00008000 ) >> 15) #define GET_RG_SX_CP_IOST (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00070000 ) >> 16) #define GET_RG_SX_PFD_SEL (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00400000 ) >> 22) #define GET_RG_SX_PFD_SET (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x00800000 ) >> 23) #define GET_RG_SX_PFD_SET1 (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x01000000 ) >> 24) #define GET_RG_SX_PFD_SET2 (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x02000000 ) >> 25) #define GET_RG_SX_PFD_REF_EDGE (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x04000000 ) >> 26) #define GET_RG_SX_PFD_DIV_EDGE (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x08000000 ) >> 27) #define GET_RG_SX_PFD_TRUP (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x10000000 ) >> 28) #define GET_RG_SX_PFD_TRDN (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x20000000 ) >> 29) #define GET_RG_SX_PFD_TLSEL (((REG32(ADR_SX_2_4GB_PFD_CHP_)) & 0x40000000 ) >> 30) #define GET_RG_SX_LPF_C1_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x0000000f ) >> 0) #define GET_RG_SX_LPF_C2_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x000000f0 ) >> 4) #define GET_RG_SX_LPF_C3_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x00000100 ) >> 8) #define GET_RG_SX_LPF_R2_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x00001e00 ) >> 9) #define GET_RG_SX_LPF_R3_BT (((REG32(ADR_SX_2_4GB_LPF)) & 0x0000e000 ) >> 13) #define GET_RG_SX_LPF_C1_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x000f0000 ) >> 16) #define GET_RG_SX_LPF_C2_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x00f00000 ) >> 20) #define GET_RG_SX_LPF_C3_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x01000000 ) >> 24) #define GET_RG_SX_LPF_R2_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0x1e000000 ) >> 25) #define GET_RG_SX_LPF_R3_WF (((REG32(ADR_SX_2_4GB_LPF)) & 0xe0000000 ) >> 29) #define GET_RG_SX_VCO_ISEL_MAN (((REG32(ADR_SX_2_4GB_VCO)) & 0x00000001 ) >> 0) #define GET_RG_SX_VCO_ISEL_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x0000001e ) >> 1) #define GET_RG_SX_VCO_LPM_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x00000020 ) >> 5) #define GET_RG_SX_VCO_VCCBSEL_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x000001c0 ) >> 6) #define GET_RG_SX_VCO_KVDOUB_BT (((REG32(ADR_SX_2_4GB_VCO)) & 0x00000200 ) >> 9) #define GET_RG_SX_VCO_ISEL_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00003c00 ) >> 10) #define GET_RG_SX_VCO_LPM_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00004000 ) >> 14) #define GET_RG_SX_VCO_VCCBSEL_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00038000 ) >> 15) #define GET_RG_SX_VCO_KVDOUB_WF (((REG32(ADR_SX_2_4GB_VCO)) & 0x00040000 ) >> 18) #define GET_RG_SX_VCO_VARBSEL (((REG32(ADR_SX_2_4GB_VCO)) & 0x00600000 ) >> 21) #define GET_RG_SX_VCO_RTAIL_SHIFT (((REG32(ADR_SX_2_4GB_VCO)) & 0x00800000 ) >> 23) #define GET_RG_SX_VCO_CS_AWH (((REG32(ADR_SX_2_4GB_VCO)) & 0x01000000 ) >> 24) #define GET_RG_VOBF_TXMBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00000003 ) >> 0) #define GET_RG_VOBF_TXOBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x0000000c ) >> 2) #define GET_RG_VOBF_RXMBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00000030 ) >> 4) #define GET_RG_VOBF_RXOBSEL_BT (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x000000c0 ) >> 6) #define GET_RG_VOBF_TXMBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00000c00 ) >> 10) #define GET_RG_VOBF_TXOBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00003000 ) >> 12) #define GET_RG_VOBF_RXMBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x0000c000 ) >> 14) #define GET_RG_VOBF_RXOBSEL_WF (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00030000 ) >> 16) #define GET_RG_VOBF_DIVBFSEL (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00080000 ) >> 19) #define GET_RG_SX_VCO_TXOB_AW (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00100000 ) >> 20) #define GET_RG_SX_VCO_RXOB_AW (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x00200000 ) >> 21) #define GET_RG_VOBF_CAPIMB_POL (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x04000000 ) >> 26) #define GET_RG_VOBF_CAPIMB (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x38000000 ) >> 27) #define GET_RG_EN_SX_VCOMON (((REG32(ADR_SX_2_4GB_VCOBF)) & 0x80000000 ) >> 31) #define GET_RG_SX_DIV_PREVDD (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x0000000f ) >> 0) #define GET_RG_SX_DIV_PSCVDD (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x000000f0 ) >> 4) #define GET_RG_SX_DIV_RST_H (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00000200 ) >> 9) #define GET_RG_SX_DIV_SDM_EDGE (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00000400 ) >> 10) #define GET_RG_SX_DIV_DMYBUF_EN (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00000800 ) >> 11) #define GET_RG_EN_SX_MOD (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00020000 ) >> 17) #define GET_RG_EN_SX_DITHER (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00040000 ) >> 18) #define GET_RG_SX_MOD_ORDER (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00180000 ) >> 19) #define GET_RG_SX_DITHER_WEIGHT (((REG32(ADR_SX_2_4GB_DIV_SDM)) & 0x00600000 ) >> 21) #define GET_RG_SX_SUB_SEL_MAN (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00000001 ) >> 0) #define GET_RG_SX_SUB_SEL (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x000001fe ) >> 1) #define GET_RG_SX_SUB_C0P5_DIS (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00000200 ) >> 9) #define GET_RG_SX_SBCAL_CT (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00000c00 ) >> 10) #define GET_RG_SX_SBCAL_WT (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00001000 ) >> 12) #define GET_RG_SX_SBCAL_DIFFMIN (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00002000 ) >> 13) #define GET_RG_SX_SBCAL_NTARG_MAN (((REG32(ADR_SX_2_4GB_SBCAL)) & 0x00008000 ) >> 15) #define GET_RG_SX_SBCAL_NTARG (((REG32(ADR_SX_2_4GB_SBCAL)) & 0xffff0000 ) >> 16) #define GET_RG_VO_AAC_TAR_BT (((REG32(ADR_SX_2_4GB_AAC)) & 0x0000000f ) >> 0) #define GET_RG_VO_AAC_IOST_BT (((REG32(ADR_SX_2_4GB_AAC)) & 0x00000030 ) >> 4) #define GET_RG_VO_AAC_TAR_WF (((REG32(ADR_SX_2_4GB_AAC)) & 0x00000780 ) >> 7) #define GET_RG_VO_AAC_IOST_WF (((REG32(ADR_SX_2_4GB_AAC)) & 0x00001800 ) >> 11) #define GET_RG_VO_AAC_IMAX (((REG32(ADR_SX_2_4GB_AAC)) & 0x0003c000 ) >> 14) #define GET_RG_VO_AAC_INIT (((REG32(ADR_SX_2_4GB_AAC)) & 0x000c0000 ) >> 18) #define GET_RG_VO_AAC_EVA_TS (((REG32(ADR_SX_2_4GB_AAC)) & 0x00300000 ) >> 20) #define GET_RG_VO_AAC_EN_MAN (((REG32(ADR_SX_2_4GB_AAC)) & 0x00800000 ) >> 23) #define GET_RG_VO_AAC_EN (((REG32(ADR_SX_2_4GB_AAC)) & 0x01000000 ) >> 24) #define GET_RG_VO_AAC_EVA_MAN (((REG32(ADR_SX_2_4GB_AAC)) & 0x02000000 ) >> 25) #define GET_RG_VO_AAC_EVA (((REG32(ADR_SX_2_4GB_AAC)) & 0x04000000 ) >> 26) #define GET_RG_VO_AAC_TEST_EN (((REG32(ADR_SX_2_4GB_AAC)) & 0x10000000 ) >> 28) #define GET_RG_VO_AAC_TEST_SEL (((REG32(ADR_SX_2_4GB_AAC)) & 0x20000000 ) >> 29) #define GET_RG_SX_TTL_INIT (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000003 ) >> 0) #define GET_RG_SX_TTL_FPT (((REG32(ADR_SX_2_4GB_TTL)) & 0x0000000c ) >> 2) #define GET_RG_SX_TTL_CPT (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000030 ) >> 4) #define GET_RG_SX_TTL_ACCUM (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000180 ) >> 7) #define GET_RG_SX_TTL_SUB (((REG32(ADR_SX_2_4GB_TTL)) & 0x00000c00 ) >> 10) #define GET_RG_SX_TTL_SUB_INV (((REG32(ADR_SX_2_4GB_TTL)) & 0x00001000 ) >> 12) #define GET_RG_SX_TTL_VH (((REG32(ADR_SX_2_4GB_TTL)) & 0x0000c000 ) >> 14) #define GET_RG_SX_TTL_VL (((REG32(ADR_SX_2_4GB_TTL)) & 0x00030000 ) >> 16) #define GET_RG_SX_LPF_VTUNE_TEST (((REG32(ADR_SX_2_4GB_TTL)) & 0x00080000 ) >> 19) #define GET_DPLL_TOP_REGISTER (((REG32(ADR_DPLL_TOP_REGISTER)) & 0xffffffff ) >> 0) #define GET_DPLL_CKT_REGISTER (((REG32(ADR_DPLL_CKT_REGISTER)) & 0xffffffff ) >> 0) #define GET_DPLL_FB_DIVISION__REGISTERS (((REG32(ADR_DPLL_FB_DIVISION__REGISTERS)) & 0xffffffff ) >> 0) #define GET_RG_WF_IDACAI_TZ0_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ0_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ0_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ0_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ0_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG15 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG14 (((REG32(ADR_WF_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG13 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG12 (((REG32(ADR_WF_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG11 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG10 (((REG32(ADR_WF_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG9 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG8 (((REG32(ADR_WF_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG7 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG6 (((REG32(ADR_WF_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG5 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_WF_IDACAI_TZ1_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_WF_IDACAQ_TZ1_PGAG1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_WF_IDACAI_TZ1_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_WF_IDACAQ_TZ1_PGAG0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_IDACAI_TZ0_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0) #define GET_RG_IDACAQ_TZ0_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8) #define GET_RG_IDACAI_TZ0_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16) #define GET_RG_IDACAQ_TZ0_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24) #define GET_RG_IDACAI_TZ0_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0) #define GET_RG_IDACAQ_TZ0_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8) #define GET_RG_IDACAI_TZ0_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16) #define GET_RG_IDACAQ_TZ0_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24) #define GET_RG_IDACAI_TZ0_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0) #define GET_RG_IDACAQ_TZ0_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8) #define GET_RG_IDACAI_TZ1_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16) #define GET_RG_IDACAQ_TZ1_COARSE4 (((REG32(ADR_WF_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24) #define GET_RG_IDACAI_TZ1_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0) #define GET_RG_IDACAQ_TZ1_COARSE3 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8) #define GET_RG_IDACAI_TZ1_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16) #define GET_RG_IDACAQ_TZ1_COARSE2 (((REG32(ADR_WF_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24) #define GET_RG_IDACAI_TZ1_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0) #define GET_RG_IDACAQ_TZ1_COARSE1 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8) #define GET_RG_IDACAI_TZ1_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16) #define GET_RG_IDACAQ_TZ1_COARSE0 (((REG32(ADR_WF_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ0_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ0_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ0_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ0_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG15 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG14 (((REG32(ADR_BT_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG13 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG12 (((REG32(ADR_BT_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG11 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG10 (((REG32(ADR_BT_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG9 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG8 (((REG32(ADR_BT_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG7 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG6 (((REG32(ADR_BT_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG5 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG4 (((REG32(ADR_BT_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG3 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG2 (((REG32(ADR_BT_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_BT_IDACAI_TZ1_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_BT_IDACAQ_TZ1_PGAG1 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_BT_IDACAI_TZ1_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_BT_IDACAQ_TZ1_PGAG0 (((REG32(ADR_BT_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_SX_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_TXDAC_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4) #define GET_RG_TXRF_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8) #define GET_RG_TXPA_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12) #define GET_RG_RXRF_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16) #define GET_RG_TXBTPA_DELAY (((REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) & 0x00f00000 ) >> 20) #define GET_RG_TXDAC_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_TXRF_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_TXPA_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_RXRF_T2R_DELAY (((REG32(ADR_WIFI_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_TXDAC_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_TXRF_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_TXPA_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_RXRF_R2T_DELAY (((REG32(ADR_WIFI_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_WF_RX_DCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_BT_RX_DCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_RX_RCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_TX_DCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_TX_IQCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_RX_IQCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_RX_N_RCCAL_DELAY (((REG32(ADR_CALIBRATION_TIMER_REGISTER)) & 0x07000000 ) >> 24) #define GET_RG_PGAG_RCCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x0000000f ) >> 0) #define GET_RG_PGAG_TXCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x000000f0 ) >> 4) #define GET_RG_TX_GAIN_TXCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x00007f00 ) >> 8) #define GET_RG_RFG_RXIQCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x00030000 ) >> 16) #define GET_RG_PGAG_RXIQCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x003c0000 ) >> 18) #define GET_RG_TX_GAIN_RXIQCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER0)) & 0x1fc00000 ) >> 22) #define GET_RG_RFG_DPDCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00000003 ) >> 0) #define GET_RG_PGAG_DPDCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x0000003c ) >> 2) #define GET_RG_TX_GAIN_DPDCAL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00001fc0 ) >> 6) #define GET_RG_IOT_ADC_CLKSEL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00010000 ) >> 16) #define GET_RG_IOT_ADC_DNLEN (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00020000 ) >> 17) #define GET_RG_IOT_ADC_METAEN (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00040000 ) >> 18) #define GET_RG_IOT_ADC_TFLAG (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00080000 ) >> 19) #define GET_RG_IOT_ADC_ICMP (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00300000 ) >> 20) #define GET_RG_IOT_ADC_VCMI (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x00c00000 ) >> 22) #define GET_RG_IOT_ADC_CLOAD (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x03000000 ) >> 24) #define GET_RG_IOT_ADC_CLK_DIV (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x0c000000 ) >> 26) #define GET_RG_IOT_ADC_CLK_SH_DUTY (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x10000000 ) >> 28) #define GET_RG_IOT_ADC_VSEN_SEL (((REG32(ADR_CALIBRATION_GAIN_REGISTER1)) & 0x60000000 ) >> 29) #define GET_DB_AD_ADC_I_OUT (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x000003ff ) >> 0) #define GET_DB_AD_ADC_Q_OUT (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x000ffc00 ) >> 10) #define GET_DB_AD_RX_RSSIADC (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x00f00000 ) >> 20) #define GET_DB_DA_SARADC_BIT (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x3f000000 ) >> 24) #define GET_SAR_ADC_FSM_RDY (((REG32(ADR_READ_ONLY_FLAGS_ADC)) & 0x40000000 ) >> 30) #define GET_DB_DA_SX_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x000000ff ) >> 0) #define GET_DB_DA_SX_VCO_ISEL (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00000f00 ) >> 8) #define GET_DB_VO_AAC_COMPOUT (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00001000 ) >> 12) #define GET_DB_SX_TTL_VT_DET (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x0000c000 ) >> 14) #define GET_DB_AD_DP_VT_MON_Q (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x00030000 ) >> 16) #define GET_DB_AD_IOT_ADC_OUT (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) & 0x3ff00000 ) >> 20) #define GET_DB_SX_SBCAL_NCOUNT (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0x0000ffff ) >> 0) #define GET_DB_SX_SBCAL_NTARGET (((REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_2)) & 0xffff0000 ) >> 16) #define GET_RG_5G_TX_TRSW_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_5G_EN_TX_TRSW (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_5G_RX_LNA_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_5G_EN_RX_LNA (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_5G_RX_MIXER_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_5G_EN_RX_MIXER (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000020 ) >> 5) #define GET_RG_5G_RX_DIV2_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_5G_EN_RX_DIV2 (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_5G_RX_LOBUF_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000100 ) >> 8) #define GET_RG_5G_EN_RX_LOBUF (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_5G_RX_TZ_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_5G_EN_RX_TZ (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_5G_TX_PA_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_5G_EN_TX_PA (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_5G_TX_MOD_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_5G_EN_TX_MOD (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00008000 ) >> 15) #define GET_RG_5G_TX_DIV2_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00040000 ) >> 18) #define GET_RG_5G_EN_TX_DIV2 (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_5G_TX_DIV2_BUF_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00100000 ) >> 20) #define GET_RG_5G_EN_TX_DIV2_BUF (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00200000 ) >> 21) #define GET_RG_5G_RX_TZ_OUT_TRISTATE_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_5G_RX_TZ_OUT_TRISTATE (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_5G_TX_SELF_MIXER_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_5G_EN_TX_SELF_MIXER (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_5G_RX_IQCAL_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_5G_EN_RX_IQCAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_5G_TX_DPD_MANUAL (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_5G_EN_TX_DPD (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_5G_EN_TX_TSSI (((REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) & 0x40000000 ) >> 30) #define GET_RG_5G_LDO_LEVEL_RX_FE (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_5G_EN_LDO_RX_FE_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_SX5GB_LDO_CP_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000070 ) >> 4) #define GET_RG_EN_LDO_5G_CP_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_SX5GB_LDO_LO_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_EN_LDO_5G_LO_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_SX5GB_LDO_VCO_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_SX5GB_LDO_DIV_LEVEL (((REG32(ADR_5G_LDO_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_EN_LDO_5G_DIV_BYP (((REG32(ADR_5G_LDO_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_5G_EN_LDO_RX_FE (((REG32(ADR_5G_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_5G_EN_IREF_RX (((REG32(ADR_5G_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_5G_EN_LDO_RX_FE_FC (((REG32(ADR_5G_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_5G_EN_LDO_RX_FE_IQUP (((REG32(ADR_5G_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_5G_RX_SCA_MANUAL (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000001 ) >> 0) #define GET_RG_5G_RX_SCA_MA (((REG32(ADR_5G_RX_REGISTER1)) & 0x0000000e ) >> 1) #define GET_RG_5G_RX_SCA_LOAD (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000070 ) >> 4) #define GET_RG_5G_RX_LNA_TRI_SEL (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000300 ) >> 8) #define GET_RG_5G_RX_LNA_SETTLE (((REG32(ADR_5G_RX_REGISTER1)) & 0x00000c00 ) >> 10) #define GET_RG_5G_GM_BIAS (((REG32(ADR_5G_RX_REGISTER1)) & 0x00007000 ) >> 12) #define GET_RG_5G_RX_DIV2_BUF (((REG32(ADR_5G_RX_REGISTER1)) & 0x00030000 ) >> 16) #define GET_RG_5G_RX_DIV2_CML (((REG32(ADR_5G_RX_REGISTER1)) & 0x000c0000 ) >> 18) #define GET_RG_5G_RX_DIV_CMLISEL (((REG32(ADR_5G_RX_REGISTER1)) & 0x00300000 ) >> 20) #define GET_RG_5G_RX_DIV_PREBUFS2 (((REG32(ADR_5G_RX_REGISTER1)) & 0x00400000 ) >> 22) #define GET_RG_5G_RX_TZ_COURSE (((REG32(ADR_5G_RX_REGISTER1)) & 0x03000000 ) >> 24) #define GET_RG_5G_TX_DPDGM_BIAS (((REG32(ADR_5G_RX_REGISTER1)) & 0xf0000000 ) >> 28) #define GET_RG_5G_TX_DPD_DIV (((REG32(ADR_5G_RX_REGISTER2)) & 0x0000000f ) >> 0) #define GET_RG_5G_TX_TSSI_BIAS (((REG32(ADR_5G_RX_REGISTER2)) & 0x00000070 ) >> 4) #define GET_RG_5G_TX_TSSI_DIV (((REG32(ADR_5G_RX_REGISTER2)) & 0x00000700 ) >> 8) #define GET_RG_5G_TX_TSSI_TEST (((REG32(ADR_5G_RX_REGISTER2)) & 0x00003000 ) >> 12) #define GET_RG_5G_TX_TSSI_TESTMODE (((REG32(ADR_5G_RX_REGISTER2)) & 0x00004000 ) >> 14) #define GET_RG_5G_RX_ADC_ICMP (((REG32(ADR_5G_RX_REGISTER2)) & 0x00030000 ) >> 16) #define GET_RG_5G_RX_ADC_VCMI (((REG32(ADR_5G_RX_REGISTER2)) & 0x000c0000 ) >> 18) #define GET_RG_5G_RX_ADC_CLOAD (((REG32(ADR_5G_RX_REGISTER2)) & 0x00300000 ) >> 20) #define GET_RG_5G_RX_ADC_PSW (((REG32(ADR_5G_RX_REGISTER2)) & 0x00400000 ) >> 22) #define GET_RG_5G_RX_TZ_CMZ_C (((REG32(ADR_5G_RX_REGISTER2)) & 0x01800000 ) >> 23) #define GET_RG_5G_RX_TZ_CMZ_R (((REG32(ADR_5G_RX_REGISTER2)) & 0x06000000 ) >> 25) #define GET_RG_5G_TXPAPGA_MANUAL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_5G_TXPGA_CAPSW (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x0000000e ) >> 1) #define GET_RG_5G_PACELL_EN (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x000000e0 ) >> 5) #define GET_RG_5G_PABIAS_CTRL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_5G_TX_PAFB_EN (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_5G_TX_PA1_VCAS (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x0000e000 ) >> 13) #define GET_RG_5G_TX_PA2_VCAS (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_PABIAS_2X (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00080000 ) >> 19) #define GET_RG_5G_TX_PA3_VCAS (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00700000 ) >> 20) #define GET_RG_5G_TX_DIV_PREBUFS2 (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_5G_TX_DIV_CMLISEL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_5G_TX_DIV_CMLVSEL (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x0c000000 ) >> 26) #define GET_RG_5G_TX_DIV_VSET (((REG32(ADR_5G_TX_FE_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_5G_TX_LOBUF_VSET (((REG32(ADR_5G_TX_FE_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_5G_TXPGA_MAIN (((REG32(ADR_5G_TX_REGISTER)) & 0x0000003f ) >> 0) #define GET_RG_5G_TXPGA_STEER (((REG32(ADR_5G_TX_REGISTER)) & 0x00000fc0 ) >> 6) #define GET_RG_5G_TXMOD_GMCELL (((REG32(ADR_5G_TX_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_5G_TXLPF_GMCELL (((REG32(ADR_5G_TX_REGISTER)) & 0x0000c000 ) >> 14) #define GET_RG_5G_TX_GAIN_OFFSET (((REG32(ADR_5G_TX_REGISTER)) & 0x000f0000 ) >> 16) #define GET_RG_5G_TX_GAIN (((REG32(ADR_5G_TX_REGISTER)) & 0x07f00000 ) >> 20) #define GET_RG_5G_TX_ADDGMCELL (((REG32(ADR_5G_TX_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_5G_TXMOD_LOBIAS (((REG32(ADR_5G_TX_REGISTER)) & 0x30000000 ) >> 28) #define GET_RG_5G_TXMOD_PGABIAS (((REG32(ADR_5G_TX_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_5G_RX_HG_LNA_GC (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_5G_RX_HG_TZ_GC (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_5G_RX_HG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_5G_RX_HG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_5G_RX_HG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_5G_RX_HG_TZ_CAP (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_RX_HG_SQDC (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_5G_RX_HG_DIV2_CORE (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_5G_RX_HG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_5G_RX_HG_TZI (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_5G_RX_HG_TZ_VCM (((REG32(ADR_5G_RX_FE_HG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_5G_RX_MG_LNA_GC (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_5G_RX_MG_TZ_GC (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_5G_RX_MG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_5G_RX_MG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_5G_RX_MG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_5G_RX_MG_TZ_CAP (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_RX_MG_SQDC (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_5G_RX_MG_DIV2_CORE (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_5G_RX_MG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_5G_RX_MG_TZI (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_5G_RX_MG_TZ_VCM (((REG32(ADR_5G_RX_FE_MG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_5G_RX_LG_LNA_GC (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_5G_RX_LG_TZ_GC (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_5G_RX_LG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_5G_RX_LG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_5G_RX_LG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_5G_RX_LG_TZ_CAP (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_RX_LG_SQDC (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_5G_RX_LG_DIV2_CORE (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_5G_RX_LG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_5G_RX_LG_TZI (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_5G_RX_LG_TZ_VCM (((REG32(ADR_5G_RX_FE_LG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_5G_RX_ULG_LNA_GC (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_5G_RX_ULG_TZ_GC (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_5G_RX_ULG_LNAHGN_BIAS (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x000000f0 ) >> 4) #define GET_RG_5G_RX_ULG_LNAHGP_BIAS (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00000f00 ) >> 8) #define GET_RG_5G_RX_ULG_LNALG_BIAS (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x0000f000 ) >> 12) #define GET_RG_5G_RX_ULG_TZ_CAP (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_RX_ULG_SQDC (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_5G_RX_ULG_DIV2_CORE (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x00c00000 ) >> 22) #define GET_RG_5G_RX_ULG_TZ_GC_BOOST (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x03000000 ) >> 24) #define GET_RG_5G_RX_ULG_TZI (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0x1c000000 ) >> 26) #define GET_RG_5G_RX_ULG_TZ_VCM (((REG32(ADR_5G_RX_FE_ULG_REGISTER)) & 0xe0000000 ) >> 29) #define GET_RG_5G_TX_DACI1ST (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000003 ) >> 0) #define GET_RG_5G_TX_DACLPF_ICOARSE (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x0000000c ) >> 2) #define GET_RG_5G_TX_DACLPF_IFINE (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000030 ) >> 4) #define GET_RG_5G_TX_DACLPF_VCM (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x000000c0 ) >> 6) #define GET_RG_5G_TX_DAC_IBIAS (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000300 ) >> 8) #define GET_RG_5G_TX_DAC_IATTN (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_5G_TXLPF_BOOSTI (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_5G_TX_DAC_RCAL (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00003000 ) >> 12) #define GET_RG_5G_TX_DAC_CKEDGE_SEL (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_5G_TX_DAC_OS (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_TX_DAC_IOFFSET (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_5G_TX_DAC_QOFFSET (((REG32(ADR_5G_TX_DAC_REGISTER)) & 0x0f000000 ) >> 24) #define GET_RG_SX5GB_RFCTRL_F (((REG32(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0x00ffffff ) >> 0) #define GET_RG_SX5GB_RFCTRL_CH_7_0 (((REG32(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) & 0xff000000 ) >> 24) #define GET_RG_SX5GB_RFCTRL_CH_10_8 (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000007 ) >> 0) #define GET_RG_SX5GB_RFCH_MAP_EN (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000010 ) >> 4) #define GET_RG_SX5GB_LO_TIMES (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x00000020 ) >> 5) #define GET_RG_SX5GB_CHANNEL (((REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) & 0x0000ff00 ) >> 8) #define GET_RG_SX_5GB_EN_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000001 ) >> 0) #define GET_RG_SX_5GB_EN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000002 ) >> 1) #define GET_RG_EN_SX5GB_CP_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000004 ) >> 2) #define GET_RG_EN_SX5GB_CP (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000008 ) >> 3) #define GET_RG_EN_SX5GB_DIV_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000010 ) >> 4) #define GET_RG_EN_SX5GB_DIV (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000020 ) >> 5) #define GET_RG_EN_SX5GB_VCO_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000040 ) >> 6) #define GET_RG_EN_SX5GB_VCO (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000080 ) >> 7) #define GET_RG_SX5GB_PFD_RST_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000100 ) >> 8) #define GET_RG_SX5GB_PFD_RST (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000200 ) >> 9) #define GET_RG_SX5GB_UOP_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000400 ) >> 10) #define GET_RG_SX5GB_UOP_EN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00000800 ) >> 11) #define GET_RG_EN_SX5GB_HSDIV_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00001000 ) >> 12) #define GET_RG_EN_SX5GB_HSDIV (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00002000 ) >> 13) #define GET_RG_EN_HSDIV_OBF_SX_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00004000 ) >> 14) #define GET_RG_EN_HSDIV_OBF_SX (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00008000 ) >> 15) #define GET_RG_EN_HSDIV_OBF_MX_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00010000 ) >> 16) #define GET_RG_EN_HSDIV_OBF_MX (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00020000 ) >> 17) #define GET_RG_EN_SX_MIX_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00040000 ) >> 18) #define GET_RG_EN_SX_MIX (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00080000 ) >> 19) #define GET_RG_EN_SX_REP_MAN (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00100000 ) >> 20) #define GET_RG_EN_SX_REP (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00200000 ) >> 21) #define GET_RG_SX5GB_SBCAL_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00400000 ) >> 22) #define GET_RG_SX5GB_SBCAL_2ND_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x00800000 ) >> 23) #define GET_RG_SX5GB_SBCAL_AW (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x01000000 ) >> 24) #define GET_RG_SX5GB_VOAAC_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x02000000 ) >> 25) #define GET_RG_SX5GB_MIXAAC_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x04000000 ) >> 26) #define GET_RG_SX5GB_REPAAC_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x08000000 ) >> 27) #define GET_RG_SX5GB_TTL_DIS (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0x10000000 ) >> 28) #define GET_RG_SX5GB_CAL_INIT (((REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) & 0xe0000000 ) >> 29) #define GET_RG_EN_SX5GB_LDO_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000001 ) >> 0) #define GET_RG_EN_LDO_5G_CP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000002 ) >> 1) #define GET_RG_EN_LDO_5G_DIV (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000004 ) >> 2) #define GET_RG_EN_LDO_5G_LO (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000008 ) >> 3) #define GET_RG_EN_LDO_5G_VCO (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000010 ) >> 4) #define GET_RG_EN_SXMIX_INBF_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000040 ) >> 6) #define GET_RG_EN_SXMIX_INBF (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000080 ) >> 7) #define GET_RG_EN_LDO_5G_VCO_PSW (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000200 ) >> 9) #define GET_RG_EN_LDO_5G_VCO_VDD33 (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000400 ) >> 10) #define GET_RG_EN_LDO_5G_CP_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00000800 ) >> 11) #define GET_RG_EN_LDO_5G_DIV_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00001000 ) >> 12) #define GET_RG_EN_LDO_5G_LO_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00002000 ) >> 13) #define GET_RG_EN_LDO_5G_VCO_IQUP (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00004000 ) >> 14) #define GET_RG_SX5GB_LDO_FCOFFT (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00380000 ) >> 19) #define GET_RG_LDO_5G_CP_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00400000 ) >> 22) #define GET_RG_LDO_5G_CP_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x00800000 ) >> 23) #define GET_RG_LDO_5G_DIV_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x01000000 ) >> 24) #define GET_RG_LDO_5G_DIV_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x02000000 ) >> 25) #define GET_RG_LDO_5G_LO_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x04000000 ) >> 26) #define GET_RG_LDO_5G_LO_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x08000000 ) >> 27) #define GET_RG_LDO_5G_VCO_FC_MAN (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x10000000 ) >> 28) #define GET_RG_LDO_5G_VCO_FC (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0x20000000 ) >> 29) #define GET_RG_LDO_5G_VCO_RCF (((REG32(ADR_SX_5GB_LDO_REGISTER)) & 0xc0000000 ) >> 30) #define GET_RG_SX5GB_CP_ISEL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x0000000f ) >> 0) #define GET_RG_SX5GB_CP_ISEL50U (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000010 ) >> 4) #define GET_RG_SX5GB_CP_KP_DOUB (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000020 ) >> 5) #define GET_RG_SX5GB_CP_IOST_POL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000080 ) >> 7) #define GET_RG_SX5GB_CP_IOST (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00000700 ) >> 8) #define GET_RG_SX5GB_PFD_SEL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00001000 ) >> 12) #define GET_RG_SX5GB_PFD_SET (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00002000 ) >> 13) #define GET_RG_SX5GB_PFD_SET1 (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00004000 ) >> 14) #define GET_RG_SX5GB_PFD_SET2 (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00008000 ) >> 15) #define GET_RG_SX5GB_PFD_TRUP (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00010000 ) >> 16) #define GET_RG_SX5GB_PFD_TRDN (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00020000 ) >> 17) #define GET_RG_SX5GB_PFD_TLSEL (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00040000 ) >> 18) #define GET_RG_SX5GB_PFD_REF_EDGE (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00080000 ) >> 19) #define GET_RG_SX5GB_PFD_DIV_EDGE (((REG32(ADR_SX_5GB_PFD_CHP_)) & 0x00100000 ) >> 20) #define GET_RG_SX5GB_LPF_C1 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x0000000f ) >> 0) #define GET_RG_SX5GB_LPF_C2 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x000000f0 ) >> 4) #define GET_RG_SX5GB_LPF_C3 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00000100 ) >> 8) #define GET_RG_SX5GB_LPF_R2 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00001e00 ) >> 9) #define GET_RG_SX5GB_LPF_R3 (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x0000e000 ) >> 13) #define GET_RG_SX5GB_TTL_INIT (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00030000 ) >> 16) #define GET_RG_SX5GB_TTL_FPT (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x000c0000 ) >> 18) #define GET_RG_SX5GB_TTL_CPT (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00300000 ) >> 20) #define GET_RG_SX5GB_TTL_ACCUM (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x00c00000 ) >> 22) #define GET_RG_SX5GB_TTL_SUB (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x03000000 ) >> 24) #define GET_RG_SX5GB_TTL_SUB_INV (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x04000000 ) >> 26) #define GET_RG_SX5GB_TTL_VH (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x18000000 ) >> 27) #define GET_RG_SX5GB_TTL_VL (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x60000000 ) >> 29) #define GET_RG_SX5GB_LPF_VTUNE_TEST (((REG32(ADR_SX_5GB_LPF_TTL)) & 0x80000000 ) >> 31) #define GET_RG_SX5GB_VCO_ISEL_MAN (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00000001 ) >> 0) #define GET_RG_SX5GB_VCO_ISEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x0000001e ) >> 1) #define GET_RG_SX5GB_VCO_VCCBSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x000001c0 ) >> 6) #define GET_RG_SX5GB_VCO_KVDOUB (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00000200 ) >> 9) #define GET_RG_SX5GB_VCO_VARBSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00001800 ) >> 11) #define GET_RG_SX5GB_VCO_RTAIL_SHIFT (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00002000 ) >> 13) #define GET_RG_SX5GB_VCO_CS_AWH (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00004000 ) >> 14) #define GET_RG_HSDIV_INBFSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00018000 ) >> 15) #define GET_RG_HSDIV_OBFMX_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00020000 ) >> 17) #define GET_RG_HSDIV_OBFSX_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00040000 ) >> 18) #define GET_RG_HSDIV_VRSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00180000 ) >> 19) #define GET_RG_SXMIX_IBIAS_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x00600000 ) >> 21) #define GET_RG_SXMIX_SWB_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x01800000 ) >> 23) #define GET_RG_SXMIX_GMSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x06000000 ) >> 25) #define GET_RG_SXREP_SWB_SEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x18000000 ) >> 27) #define GET_RG_SXREP_CSSEL (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x60000000 ) >> 29) #define GET_RG_EN_SX5GB_VCOMON (((REG32(ADR_SX_5GB_VCO_LOGEN)) & 0x80000000 ) >> 31) #define GET_RG_SX5GB_DIV_PREVDD (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x0000000f ) >> 0) #define GET_RG_SX5GB_DIV_PSCVDD (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x000000f0 ) >> 4) #define GET_RG_SX5GB_DIV_RST_H (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00000200 ) >> 9) #define GET_RG_SX5GB_DIV_SDM_EDGE (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00000400 ) >> 10) #define GET_RG_SX5GB_DIV_DMYBUF_EN (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00000800 ) >> 11) #define GET_RG_EN_SX5GB_MOD (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00020000 ) >> 17) #define GET_RG_EN_SX5GB_DITHER (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00040000 ) >> 18) #define GET_RG_SX5GB_MOD_ORDER (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00180000 ) >> 19) #define GET_RG_SX5GB_DITHER_WEIGHT (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x00600000 ) >> 21) #define GET_RG_SXMIX_INBF_SEL (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x03000000 ) >> 24) #define GET_RG_SXMIX_GMBIAS_OP1 (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x04000000 ) >> 26) #define GET_RG_SXMIX_SWBIAS_OP1 (((REG32(ADR_SX_5GB_DIV_SDM)) & 0x08000000 ) >> 27) #define GET_RG_SX5GB_SUB_SEL_MAN (((REG32(ADR_SX_5GB_SBCAL)) & 0x00000001 ) >> 0) #define GET_RG_SX5GB_SUB_SEL (((REG32(ADR_SX_5GB_SBCAL)) & 0x000001fe ) >> 1) #define GET_RG_SX5GB_SUB_C0P5_DIS (((REG32(ADR_SX_5GB_SBCAL)) & 0x00000200 ) >> 9) #define GET_RG_SX5GB_SBCAL_CT (((REG32(ADR_SX_5GB_SBCAL)) & 0x00000c00 ) >> 10) #define GET_RG_SX5GB_SBCAL_WT (((REG32(ADR_SX_5GB_SBCAL)) & 0x00001000 ) >> 12) #define GET_RG_SX5GB_SBCAL_DIFFMIN (((REG32(ADR_SX_5GB_SBCAL)) & 0x00002000 ) >> 13) #define GET_RG_SX5GB_SBCAL_NTARG_MAN (((REG32(ADR_SX_5GB_SBCAL)) & 0x00008000 ) >> 15) #define GET_RG_SX5GB_SBCAL_NTARG (((REG32(ADR_SX_5GB_SBCAL)) & 0xffff0000 ) >> 16) #define GET_RG_SX5GB_VOAAC_TAR (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0) #define GET_RG_VO5GB_AAC_IOST (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000030 ) >> 4) #define GET_RG_VO5GB_AAC_IMAX (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x000003c0 ) >> 6) #define GET_RG_SX5GB_AAC_ACCUMH (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00000c00 ) >> 10) #define GET_RG_SX5GB_AAC_ACCUML (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00003000 ) >> 12) #define GET_RG_SX5GB_AAC_INIT (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x0000c000 ) >> 14) #define GET_RG_SX5GB_AAC_EVA_TS (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00030000 ) >> 16) #define GET_RG_SX5GB_AAC_EN_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18) #define GET_RG_SX5GB_AAC_EN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00080000 ) >> 19) #define GET_RG_SX5GB_AAC_EVA_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00100000 ) >> 20) #define GET_RG_SX5GB_AAC_EVA (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00200000 ) >> 21) #define GET_RG_AAC5GB_TAR_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x00400000 ) >> 22) #define GET_RG_AAC5GB_PDSW_EN_MAN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x01000000 ) >> 24) #define GET_RG_EN_AAC5GB_VOPDSW (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x02000000 ) >> 25) #define GET_RG_EN_AAC5GB_MXPDSW (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x04000000 ) >> 26) #define GET_RG_EN_AAC5GB_RPPDSW (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x08000000 ) >> 27) #define GET_RG_SX5GB_AAC_TEST_EN (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x40000000 ) >> 30) #define GET_RG_SX5GB_AAC_TEST_SEL (((REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) & 0x80000000 ) >> 31) #define GET_RG_SX5GB_MIXAAC_TAR (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x0000000f ) >> 0) #define GET_RG_SXMIX_SCA_SEL_MAN (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x00000020 ) >> 5) #define GET_RG_SXMIX_SCA_SEL (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x00000fc0 ) >> 6) #define GET_RG_SX5GB_REPAAC_TAR (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x0001e000 ) >> 13) #define GET_RG_SXREP_SCA_SEL_MAN (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x00040000 ) >> 18) #define GET_RG_SXREP_SCA_SEL (((REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) & 0x01f80000 ) >> 19) #define GET_RG_5G_IDACAI_TZ0_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER1)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER2)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER3)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER4)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER5)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER6)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER7)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER8)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG15 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG14 (((REG32(ADR_5G_DCOC_IDAC_REGISTER9)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG13 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG12 (((REG32(ADR_5G_DCOC_IDAC_REGISTER10)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG11 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG10 (((REG32(ADR_5G_DCOC_IDAC_REGISTER11)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG9 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG8 (((REG32(ADR_5G_DCOC_IDAC_REGISTER12)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG7 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG6 (((REG32(ADR_5G_DCOC_IDAC_REGISTER13)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG5 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER14)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER15)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_PGAG1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_PGAG0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER16)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER17)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ0_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ0_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER18)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ0_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ0_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_COARSE4 (((REG32(ADR_5G_DCOC_IDAC_REGISTER19)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_COARSE3 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_COARSE2 (((REG32(ADR_5G_DCOC_IDAC_REGISTER20)) & 0x3f000000 ) >> 24) #define GET_RG_5G_IDACAI_TZ1_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x0000003f ) >> 0) #define GET_RG_5G_IDACAQ_TZ1_COARSE1 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x00003f00 ) >> 8) #define GET_RG_5G_IDACAI_TZ1_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x003f0000 ) >> 16) #define GET_RG_5G_IDACAQ_TZ1_COARSE0 (((REG32(ADR_5G_DCOC_IDAC_REGISTER21)) & 0x3f000000 ) >> 24) #define GET_RG_SX5GB_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_5G_TXDAC_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000000f0 ) >> 4) #define GET_RG_5G_TXRF_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x00000f00 ) >> 8) #define GET_RG_5G_TXPA_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x0000f000 ) >> 12) #define GET_RG_5G_RXRF_DELAY (((REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) & 0x000f0000 ) >> 16) #define GET_RG_5G_TXDAC_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_5G_TXRF_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_5G_TXPA_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_5G_RXRF_T2R_DELAY (((REG32(ADR_5G_T2R_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_5G_TXDAC_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x0000001f ) >> 0) #define GET_RG_5G_TXRF_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x00001f00 ) >> 8) #define GET_RG_5G_TXPA_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x001f0000 ) >> 16) #define GET_RG_5G_RXRF_R2T_DELAY (((REG32(ADR_5G_R2T_TIMER_REGISTER)) & 0x1f000000 ) >> 24) #define GET_RG_5G_RX_DCCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000007 ) >> 0) #define GET_RG_5G_TX_DCCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00000700 ) >> 8) #define GET_RG_5G_TX_IQCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00007000 ) >> 12) #define GET_RG_5G_RX_IQCAL_DELAY (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00070000 ) >> 16) #define GET_RG_5G_PGAG_TXCAL (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x00f00000 ) >> 20) #define GET_RG_5G_TX_GAIN_TXCAL (((REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) & 0x7f000000 ) >> 24) #define GET_RG_5G_PGAG_RCCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0000000f ) >> 0) #define GET_RG_5G_RFG_RXIQCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00000030 ) >> 4) #define GET_RG_5G_PGAG_RXIQCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x000003c0 ) >> 6) #define GET_RG_5G_TX_GAIN_RXIQCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x0001fc00 ) >> 10) #define GET_RG_5G_RFG_DPDCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00060000 ) >> 17) #define GET_RG_5G_PGAG_DPDCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x00780000 ) >> 19) #define GET_RG_5G_TX_GAIN_DPDCAL (((REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) & 0x3f800000 ) >> 23) #define GET_DB_DA_SX5GB_SUB_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x000000ff ) >> 0) #define GET_DB_DA_SX5GB_VCO_ISEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00000f00 ) >> 8) #define GET_DB_DA_SXMIX_SCA_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x0007e000 ) >> 13) #define GET_DB_DA_SXMIX_GMSEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x00180000 ) >> 19) #define GET_DB_DA_SXREP_SCA_SEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x07e00000 ) >> 21) #define GET_DB_DA_SXREP_CSSEL (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x18000000 ) >> 27) #define GET_DB_AD_SX5GB_AAC_COMPOUT (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0x20000000 ) >> 29) #define GET_DB_SX5GB_TTL_VT_DET (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) & 0xc0000000 ) >> 30) #define GET_DB_SXMIX_SCA_SEL_A1 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x0000003f ) >> 0) #define GET_DB_SXMIX_SCA_SEL_A2 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x00001f80 ) >> 7) #define GET_DB_SXREP_SCA_SEL_B1 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x000fc000 ) >> 14) #define GET_DB_SXREP_SCA_SEL_B2 (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) & 0x07e00000 ) >> 21) #define GET_DB_SX5GB_SBCAL_NCOUNT (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_3)) & 0x0000ffff ) >> 0) #define GET_DB_SX5GB_SBCAL_NTARGET (((REG32(ADR_READ_ONLY_FLAGS_SX_5GB_3)) & 0xffff0000 ) >> 16) #define GET_RG_RX_SCAMA_STEP0 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000000f ) >> 0) #define GET_RG_RX_SCAMA_STEP1 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000000f0 ) >> 4) #define GET_RG_RX_SCAMA_STEP2 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00000f00 ) >> 8) #define GET_RG_RX_SCAMA_STEP3 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0000f000 ) >> 12) #define GET_RG_RX_SCAMA_STEP4 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x000f0000 ) >> 16) #define GET_RG_RX_SCAMA_STEP5 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x00f00000 ) >> 20) #define GET_RG_RX_SCAMA_STEP6 (((REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) & 0x0f000000 ) >> 24) #define GET_RG_RX_SCALOAD_STEP0 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000000f ) >> 0) #define GET_RG_RX_SCALOAD_STEP1 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000000f0 ) >> 4) #define GET_RG_RX_SCALOAD_STEP2 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00000f00 ) >> 8) #define GET_RG_RX_SCALOAD_STEP3 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0000f000 ) >> 12) #define GET_RG_RX_SCALOAD_STEP4 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x000f0000 ) >> 16) #define GET_RG_RX_SCALOAD_STEP5 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x00f00000 ) >> 20) #define GET_RG_RX_SCALOAD_STEP6 (((REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) & 0x0f000000 ) >> 24) #define GET_RG_5G_TXPGA_CAPSW_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00000007 ) >> 0) #define GET_RG_5G_PABIAS_CTRL_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00000078 ) >> 3) #define GET_RG_5G_TX_PA1_VCAS_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00000380 ) >> 7) #define GET_RG_5G_TX_PA2_VCAS_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00001c00 ) >> 10) #define GET_RG_5G_TX_PA3_VCAS_F0 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x0000e000 ) >> 13) #define GET_RG_5G_TXPGA_CAPSW_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00070000 ) >> 16) #define GET_RG_5G_PABIAS_CTRL_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x00780000 ) >> 19) #define GET_RG_5G_TX_PA1_VCAS_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x03800000 ) >> 23) #define GET_RG_5G_TX_PA2_VCAS_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0x1c000000 ) >> 26) #define GET_RG_5G_TX_PA3_VCAS_F1 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) & 0xe0000000 ) >> 29) #define GET_RG_5G_TXPGA_CAPSW_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00000007 ) >> 0) #define GET_RG_5G_PABIAS_CTRL_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00000078 ) >> 3) #define GET_RG_5G_TX_PA1_VCAS_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00000380 ) >> 7) #define GET_RG_5G_TX_PA2_VCAS_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00001c00 ) >> 10) #define GET_RG_5G_TX_PA3_VCAS_F2 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x0000e000 ) >> 13) #define GET_RG_5G_TXPGA_CAPSW_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00070000 ) >> 16) #define GET_RG_5G_PABIAS_CTRL_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x00780000 ) >> 19) #define GET_RG_5G_TX_PA1_VCAS_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x03800000 ) >> 23) #define GET_RG_5G_TX_PA2_VCAS_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0x1c000000 ) >> 26) #define GET_RG_5G_TX_PA3_VCAS_F3 (((REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) & 0xe0000000 ) >> 29) #define GET_RG_5G_TX_PAFB_EN_F0 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000001 ) >> 0) #define GET_RG_5G_TX_PAFB_EN_F1 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000002 ) >> 1) #define GET_RG_5G_TX_PAFB_EN_F2 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000004 ) >> 2) #define GET_RG_5G_TX_PAFB_EN_F3 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x00000008 ) >> 3) #define GET_RG_5G_TX_GAIN_F0 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x000007f0 ) >> 4) #define GET_RG_5G_TX_GAIN_F1 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x0003f800 ) >> 11) #define GET_RG_5G_TX_GAIN_F2 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0x01fc0000 ) >> 18) #define GET_RG_5G_TX_GAIN_F3 (((REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) & 0xfe000000 ) >> 25) #define GET_RG_NFRAC_DELTA (((REG32(ADR_DIGITAL_ADD_ON_0)) & 0x00ffffff ) >> 0) #define GET_RG_40M_MODE (((REG32(ADR_DIGITAL_ADD_ON_0)) & 0x01000000 ) >> 24) #define GET_RG_LO_UP_CH (((REG32(ADR_DIGITAL_ADD_ON_0)) & 0x10000000 ) >> 28) #define GET_RG_BT_TRX_IF (((REG32(ADR_DIGITAL_ADD_ON_1)) & 0x07ff0000 ) >> 16) #define GET_RG_RX_IQ_ALPHA (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x0000001f ) >> 0) #define GET_RG_RX_IQ_THETA (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00001f00 ) >> 8) #define GET_RG_RX_IQ_MANUAL (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00010000 ) >> 16) #define GET_RG_RXIQ_NOSHRK (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00020000 ) >> 17) #define GET_RG_RX_RSSIADC_TH (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x00f00000 ) >> 20) #define GET_RG_SUB_DC (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x01000000 ) >> 24) #define GET_RG_RSSI_EDGE_SEL (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x04000000 ) >> 26) #define GET_RG_ADC_EDGE_SEL (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x08000000 ) >> 27) #define GET_RG_Q_INV (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x10000000 ) >> 28) #define GET_RG_I_INV (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x20000000 ) >> 29) #define GET_RG_IQ_SWAP (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x40000000 ) >> 30) #define GET_RG_SIGN_SWAP (((REG32(ADR_DIGITAL_ADD_ON_2)) & 0x80000000 ) >> 31) #define GET_RG_TX_IQ_ALPHA (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x0000001f ) >> 0) #define GET_RG_TX_IQ_THETA (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00001f00 ) >> 8) #define GET_RG_TX_IQ_MANUAL (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00010000 ) >> 16) #define GET_RG_TXIQ_NOSHRK (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00020000 ) >> 17) #define GET_RG_TX_IQCAL_TIME (((REG32(ADR_DIGITAL_ADD_ON_3)) & 0x00300000 ) >> 20) #define GET_RG_TX_FREQ_OFFSET (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x0000ffff ) >> 0) #define GET_RG_TONE_SCALE (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x01ff0000 ) >> 16) #define GET_RG_BB_SIG_EN (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x02000000 ) >> 25) #define GET_RG_TONE_GEN_EN (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x04000000 ) >> 26) #define GET_RG_TX_UP8X_MAN_EN (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x08000000 ) >> 27) #define GET_RG_DIS_DAC_OFFSET (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x10000000 ) >> 28) #define GET_RG_CLK_320M_INV (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x20000000 ) >> 29) #define GET_RG_DPLL_CLK320BY2 (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x40000000 ) >> 30) #define GET_RG_CBW_20_40 (((REG32(ADR_DIGITAL_ADD_ON_4)) & 0x80000000 ) >> 31) #define GET_RG_DAC_DC_Q (((REG32(ADR_DIGITAL_ADD_ON_5)) & 0x000003ff ) >> 0) #define GET_RG_DAC_DC_I (((REG32(ADR_DIGITAL_ADD_ON_5)) & 0x03ff0000 ) >> 16) #define GET_RG_DAC_Q_SET (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x000003ff ) >> 0) #define GET_RG_DAC_MAN_Q_EN (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x00001000 ) >> 12) #define GET_RG_DAC_I_SET (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x03ff0000 ) >> 16) #define GET_RG_DAC_MAN_I_EN (((REG32(ADR_DIGITAL_ADD_ON_6)) & 0x10000000 ) >> 28) #define GET_RG_WF_RX_ABBCTUNE_TUNE (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x0000007f ) >> 0) #define GET_RG_WF_RX_ABBCTUNE_TUNE_EN (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x00000100 ) >> 8) #define GET_RG_WF_N_RX_ABBCTUNE_TUNE (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x007f0000 ) >> 16) #define GET_RG_WF_N_RX_ABBCTUNE_TUNE_EN (((REG32(ADR_RX_RC_VALUE_TUNE)) & 0x01000000 ) >> 24) #define GET_RG_RX_IQ_2500_ALPHA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x0000001f ) >> 0) #define GET_RG_RX_IQ_2500_THETA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x00001f00 ) >> 8) #define GET_RG_TX_IQ_2500_ALPHA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x001f0000 ) >> 16) #define GET_RG_TX_IQ_2500_THETA (((REG32(ADR_TRX_IQ_COMP_2G)) & 0x1f000000 ) >> 24) #define GET_RG_RX_IQ_5100_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x0000001f ) >> 0) #define GET_RG_RX_IQ_5100_THETA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x00001f00 ) >> 8) #define GET_RG_TX_IQ_5100_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x001f0000 ) >> 16) #define GET_RG_TX_IQ_5100_THETA (((REG32(ADR_TRX_IQ_COMP_5G_0)) & 0x1f000000 ) >> 24) #define GET_RG_RX_IQ_5500_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x0000001f ) >> 0) #define GET_RG_RX_IQ_5500_THETA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x00001f00 ) >> 8) #define GET_RG_TX_IQ_5500_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x001f0000 ) >> 16) #define GET_RG_TX_IQ_5500_THETA (((REG32(ADR_TRX_IQ_COMP_5G_1)) & 0x1f000000 ) >> 24) #define GET_RG_RX_IQ_5700_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x0000001f ) >> 0) #define GET_RG_RX_IQ_5700_THETA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x00001f00 ) >> 8) #define GET_RG_TX_IQ_5700_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x001f0000 ) >> 16) #define GET_RG_TX_IQ_5700_THETA (((REG32(ADR_TRX_IQ_COMP_5G_2)) & 0x1f000000 ) >> 24) #define GET_RG_RX_IQ_5900_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x0000001f ) >> 0) #define GET_RG_RX_IQ_5900_THETA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x00001f00 ) >> 8) #define GET_RG_TX_IQ_5900_ALPHA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x001f0000 ) >> 16) #define GET_RG_TX_IQ_5900_THETA (((REG32(ADR_TRX_IQ_COMP_5G_3)) & 0x1f000000 ) >> 24) #define GET_RG_PHASE_STEP_VALUE (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x0000ffff ) >> 0) #define GET_RG_PHASE_MANUAL (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x00010000 ) >> 16) #define GET_RG_ALPHA_SEL (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x00300000 ) >> 20) #define GET_RG_SPECTRUM_BW (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x03000000 ) >> 24) #define GET_RG_SPECTRUM_EN (((REG32(ADR_RF_D_CAL_TOP_0)) & 0x10000000 ) >> 28) #define GET_RO_WF_DCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00010000 ) >> 16) #define GET_RO_BT_DCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00020000 ) >> 17) #define GET_RO_RCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00040000 ) >> 18) #define GET_RO_TXDC_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00080000 ) >> 19) #define GET_RO_TXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00100000 ) >> 20) #define GET_RO_RXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00200000 ) >> 21) #define GET_RO_5G_TXDC_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00400000 ) >> 22) #define GET_RO_5G_TXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x00800000 ) >> 23) #define GET_RO_5G_RXIQ_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x01000000 ) >> 24) #define GET_RO_5G_DCCAL_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x02000000 ) >> 25) #define GET_RO_PRE_DC_DONE (((REG32(ADR_RF_D_CAL_TOP_1)) & 0x04000000 ) >> 26) #define GET_RG_PHASE_17P5M (((REG32(ADR_RF_D_CAL_TOP_2)) & 0x0000ffff ) >> 0) #define GET_RG_PHASE_2P5M (((REG32(ADR_RF_D_CAL_TOP_2)) & 0xffff0000 ) >> 16) #define GET_RG_PHASE_RXIQ_1M (((REG32(ADR_RF_D_CAL_TOP_3)) & 0x0000ffff ) >> 0) #define GET_RG_PHASE_1M (((REG32(ADR_RF_D_CAL_TOP_3)) & 0xffff0000 ) >> 16) #define GET_RG_PHASE_35M (((REG32(ADR_RF_D_CAL_TOP_4)) & 0xffff0000 ) >> 16) #define GET_RO_RX_IQ_THETA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x0000001f ) >> 0) #define GET_RO_RX_IQ_ALPHA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x00001f00 ) >> 8) #define GET_RO_TX_IQ_THETA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x001f0000 ) >> 16) #define GET_RO_TX_IQ_ALPHA (((REG32(ADR_RF_D_CAL_TOP_5)) & 0x1f000000 ) >> 24) #define GET_RG_RX_RCCAL_TARG (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x000003ff ) >> 0) #define GET_RG_RX_DC_POLAR_INV (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x00001000 ) >> 12) #define GET_RG_RCCAL_POLAR_INV (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x00002000 ) >> 13) #define GET_RG_RX_DC_RESOLUTION (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x00004000 ) >> 14) #define GET_RG_RX_RCCAL_40M_TARG (((REG32(ADR_RF_D_CAL_TOP_6)) & 0x03ff0000 ) >> 16) #define GET_RO_SPECTRUM_IQ_PWR_39_32 (((REG32(ADR_RF_D_CAL_TOP_7)) & 0x000000ff ) >> 0) #define GET_RG_SPECTRUM_LO_FIX (((REG32(ADR_RF_D_CAL_TOP_7)) & 0x00010000 ) >> 16) #define GET_RG_SPECTRUM_PWR_UPDATE (((REG32(ADR_RF_D_CAL_TOP_7)) & 0x00100000 ) >> 20) #define GET_RO_SPECTRUM_IQ_PWR_31_0 (((REG32(ADR_RF_D_CAL_TOP_8)) & 0xffffffff ) >> 0) #define GET_RG_PROC_DELAY (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000007 ) >> 0) #define GET_RG_PRE_DC_POLA_INV (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000010 ) >> 4) #define GET_RG_RX_PRE_DC_RESOLUTION (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000020 ) >> 5) #define GET_RG_PRE_DC_AUTO (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000040 ) >> 6) #define GET_RG_FILTER_AVERAGE_EN (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000080 ) >> 7) #define GET_RG_PHASE_RND_EN (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000100 ) >> 8) #define GET_RG_RCCAL_DATA_SEL (((REG32(ADR_RF_D_CAL_TOP_9)) & 0x00000200 ) >> 9) #define GET_RG_HS3W_TX_RF_GAIN (((REG32(ADR_HS3W_CTRL1)) & 0x0000007f ) >> 0) #define GET_RG_HS3W_PGAGC (((REG32(ADR_HS3W_CTRL1)) & 0x00000f00 ) >> 8) #define GET_RG_HS3W_RFGC (((REG32(ADR_HS3W_CTRL1)) & 0x00003000 ) >> 12) #define GET_RG_HS3W_RXAGC (((REG32(ADR_HS3W_CTRL1)) & 0x00004000 ) >> 14) #define GET_RG_HS3W_RF_PHY_MODE (((REG32(ADR_HS3W_CTRL1)) & 0x00070000 ) >> 16) #define GET_RG_HS3W_MANUAL (((REG32(ADR_HS3W_CTRL1)) & 0x00100000 ) >> 20) #define GET_RG_HS3W_COMM_DATA (((REG32(ADR_HS3W_CTRL1)) & 0x07000000 ) >> 24) #define GET_RG_HS3W_START_SENT (((REG32(ADR_HS3W_CTRL1)) & 0x10000000 ) >> 28) #define GET_RG_HS3W_SX_RFCTRL_CH_INT_10_8 (((REG32(ADR_HS3W_CTRL2)) & 0x00000007 ) >> 0) #define GET_RG_HS3W_SX_RFCH_MAP_EN_INT (((REG32(ADR_HS3W_CTRL2)) & 0x00000010 ) >> 4) #define GET_RG_HS3W_SX_CHANNEL_INT (((REG32(ADR_HS3W_CTRL2)) & 0x0007f800 ) >> 11) #define GET_RG_HS3W_SX_RFCTRL_F_INT (((REG32(ADR_HS3W_CTRL3)) & 0x00ffffff ) >> 0) #define GET_RG_HS3W_SX_RFCTRL_CH_INT_7_0 (((REG32(ADR_HS3W_CTRL3)) & 0xff000000 ) >> 24) #define GET_RG_MODE_BY_HS_3WIRE (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00000001 ) >> 0) #define GET_RG_MODE_BY_PHY (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00000010 ) >> 4) #define GET_RG_MODE_BY_HWPIN (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00000100 ) >> 8) #define GET_RO_RF_PHY_MODE (((REG32(ADR_RF_D_MODE_CTRL)) & 0x00070000 ) >> 16) #define GET_RO_HS3W_SX_CHANNEL (((REG32(ADR_HS3W_READ_OUT_1)) & 0x000000ff ) >> 0) #define GET_RO_HS3W_SX_RFCH_MAP_EN (((REG32(ADR_HS3W_READ_OUT_1)) & 0x00000100 ) >> 8) #define GET_RO_GAIN_TX (((REG32(ADR_HS3W_READ_OUT_1)) & 0x007f0000 ) >> 16) #define GET_RO_ABBPGA (((REG32(ADR_HS3W_READ_OUT_1)) & 0x0f000000 ) >> 24) #define GET_RO_RFPGA (((REG32(ADR_HS3W_READ_OUT_1)) & 0x30000000 ) >> 28) #define GET_RO_DA_RX_AGC (((REG32(ADR_HS3W_READ_OUT_1)) & 0x80000000 ) >> 31) #define GET_RO_HS3W_SX_RFCTRL_CH (((REG32(ADR_HS3W_READ_OUT_2_)) & 0x000007ff ) >> 0) #define GET_RO_HS3W_SX_RFCTRL_F (((REG32(ADR_HS3W_READ_OUT_3)) & 0x00ffffff ) >> 0) #define GET_RO_REFREG_KHZ_OUT (((REG32(ADR_SX_LOCK_FREQ_1)) & 0x007fffff ) >> 0) #define GET_RO_RF_CH_FREQ (((REG32(ADR_SX_LOCK_FREQ_2)) & 0x00001fff ) >> 0) #define GET_RO_DC_CAL_Q (((REG32(ADR_RX_DC_CAL_RESULT)) & 0x0000007f ) >> 0) #define GET_RO_DC_CAL_I (((REG32(ADR_RX_DC_CAL_RESULT)) & 0x007f0000 ) >> 16) #define GET_RG_AUDIO_VOLUME (((REG32(ADR_AUDIO_CTRL_REG)) & 0x000003ff ) >> 0) #define GET_RG_AUDIO_ALPHA (((REG32(ADR_AUDIO_CTRL_REG)) & 0x00003000 ) >> 12) #define GET_RG_AUDIO_FIL_EN (((REG32(ADR_AUDIO_CTRL_REG)) & 0x00010000 ) >> 16) #define GET_RG_IOT_ADC_SIGN_SWAP (((REG32(ADR_AUDIO_CTRL_REG)) & 0x01000000 ) >> 24) #define GET_RG_IOT_ADC_EDGE_SEL (((REG32(ADR_AUDIO_CTRL_REG)) & 0x02000000 ) >> 25) #define GET_RG_BYPASS_AUDIO_LWDF (((REG32(ADR_AUDIO_CTRL_REG)) & 0x10000000 ) >> 28) #define GET_RG_PDM_EDGE_SEL (((REG32(ADR_AUDIO_CTRL_REG)) & 0x20000000 ) >> 29) #define GET_RG_AUDIO_TYPE (((REG32(ADR_AUDIO_CTRL_REG)) & 0x40000000 ) >> 30) #define GET_RG_PDM_LOW_LEVEL (((REG32(ADR_AUDIO_PDM_REG)) & 0x00003fff ) >> 0) #define GET_RG_PDM_HIGH_LEVEL (((REG32(ADR_AUDIO_PDM_REG)) & 0x3fff0000 ) >> 16) #define GET_RG_5G_TX_BAND_F1 (((REG32(ADR_RF_5G_TX_PARTITION_BAND1)) & 0x00001fff ) >> 0) #define GET_RG_5G_TX_BAND_F0 (((REG32(ADR_RF_5G_TX_PARTITION_BAND1)) & 0x1fff0000 ) >> 16) #define GET_RG_5G_TX_BAND_F2 (((REG32(ADR_RF_5G_TX_PARTITION_BAND2)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_020_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG0)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_040_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_060_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG1)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_080_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG1)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG2)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG2)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG3)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG3)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG4)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_100_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG4)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_110_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG5)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_120_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG5)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_130_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG6)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_140_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG6)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_150_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG7)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_160_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG7)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_170_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG8)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_180_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG8)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_190_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG9)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REG9)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGA)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGA)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGB)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGB)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGC)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5100_200_GAIN (((REG32(ADR_WIFI_PADPD_5100_GAIN_REGC)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5100_020_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG0)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_040_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG0)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_060_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG1)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_080_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG1)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_0A0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG2)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_0C0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG2)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_0D0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG3)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_0E0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG3)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_0F0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG4)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_100_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG4)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_110_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG5)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_120_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG5)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_130_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG6)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_140_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG6)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_150_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG7)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_160_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG7)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_170_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG8)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_180_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG8)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_190_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG9)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_1A0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REG9)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_1B0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGA)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_1C0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGA)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_1D0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGB)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_1E0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGB)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5100_1F0_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGC)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5100_200_PH (((REG32(ADR_WIFI_PADPD_5100_PHASE_REGC)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_020_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG0)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_040_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_060_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG1)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_080_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG1)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG2)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG2)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG3)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG3)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG4)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_100_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG4)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_110_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG5)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_120_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG5)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_130_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG6)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_140_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG6)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_150_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG7)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_160_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG7)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_170_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG8)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_180_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG8)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_190_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG9)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REG9)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGA)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGA)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGB)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGB)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGC)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5500_200_GAIN (((REG32(ADR_WIFI_PADPD_5500_GAIN_REGC)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5500_020_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG0)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_040_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG0)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_060_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG1)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_080_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG1)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_0A0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG2)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_0C0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG2)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_0D0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG3)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_0E0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG3)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_0F0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG4)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_100_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG4)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_110_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG5)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_120_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG5)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_130_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG6)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_140_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG6)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_150_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG7)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_160_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG7)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_170_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG8)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_180_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG8)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_190_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG9)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_1A0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REG9)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_1B0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGA)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_1C0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGA)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_1D0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGB)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_1E0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGB)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5500_1F0_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGC)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5500_200_PH (((REG32(ADR_WIFI_PADPD_5500_PHASE_REGC)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_020_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG0)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_040_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_060_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG1)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_080_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG1)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG2)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG2)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG3)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG3)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG4)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_100_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG4)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_110_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG5)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_120_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG5)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_130_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG6)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_140_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG6)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_150_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG7)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_160_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG7)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_170_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG8)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_180_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG8)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_190_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG9)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REG9)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGA)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGA)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGB)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGB)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGC)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5700_200_GAIN (((REG32(ADR_WIFI_PADPD_5700_GAIN_REGC)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5700_020_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG0)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_040_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG0)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_060_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG1)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_080_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG1)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_0A0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG2)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_0C0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG2)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_0D0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG3)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_0E0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG3)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_0F0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG4)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_100_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG4)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_110_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG5)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_120_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG5)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_130_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG6)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_140_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG6)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_150_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG7)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_160_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG7)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_170_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG8)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_180_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG8)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_190_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG9)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_1A0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REG9)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_1B0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGA)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_1C0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGA)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_1D0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGB)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_1E0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGB)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5700_1F0_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGC)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5700_200_PH (((REG32(ADR_WIFI_PADPD_5700_PHASE_REGC)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_020_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG0)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_040_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_060_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG1)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_080_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG1)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_0A0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG2)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_0C0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG2)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_0D0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG3)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_0E0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG3)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_0F0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG4)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_100_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG4)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_110_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG5)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_120_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG5)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_130_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG6)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_140_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG6)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_150_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG7)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_160_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG7)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_170_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG8)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_180_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG8)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_190_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG9)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_1A0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REG9)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_1B0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGA)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_1C0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGA)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_1D0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGB)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_1E0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGB)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_1F0_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGC)) & 0x000003ff ) >> 0) #define GET_RG_DPD_5900_200_GAIN (((REG32(ADR_WIFI_PADPD_5900_GAIN_REGC)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_5900_020_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG0)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_040_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG0)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_060_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG1)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_080_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG1)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_0A0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG2)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_0C0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG2)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_0D0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG3)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_0E0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG3)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_0F0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG4)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_100_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG4)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_110_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG5)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_120_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG5)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_130_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG6)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_140_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG6)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_150_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG7)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_160_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG7)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_170_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG8)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_180_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG8)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_190_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG9)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_1A0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REG9)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_1B0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGA)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_1C0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGA)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_1D0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGB)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_1E0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGB)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_5900_1F0_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGC)) & 0x00001fff ) >> 0) #define GET_RG_DPD_5900_200_PH (((REG32(ADR_WIFI_PADPD_5900_PHASE_REGC)) & 0x1fff0000 ) >> 16) #define GET_RG_TONE_SEL (((REG32(ADR_WIFI_PADPD_CAL_TONEGEN_REG)) & 0x00000003 ) >> 0) #define GET_RG_TONE_1_RATE (((REG32(ADR_WIFI_PADPD_CAL_TONEGEN_REG)) & 0xffff0000 ) >> 16) #define GET_RG_RX_PADPD_EN (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00000001 ) >> 0) #define GET_RG_RX_PADPD_LEAKY_FACTOR (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00000070 ) >> 4) #define GET_RG_RX_PADPD_LATCH (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00000100 ) >> 8) #define GET_RG_RX_PADPD_DATA_SEL (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00001000 ) >> 12) #define GET_RG_RX_PADPD_TONE_SEL (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0x00002000 ) >> 13) #define GET_RG_RX_PADPD_RATE (((REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) & 0xffff0000 ) >> 16) #define GET_RO_RX_PHI (((REG32(ADR_WIFI_PADPD_CAL_RX_RO)) & 0x00001fff ) >> 0) #define GET_RO_RX_AMP (((REG32(ADR_WIFI_PADPD_CAL_RX_RO)) & 0x01ff0000 ) >> 16) #define GET_RG_CFR_GAIN (((REG32(ADR_WIFI_PADPD_CFR)) & 0x000003ff ) >> 0) #define GET_RG_CFR_PEAK (((REG32(ADR_WIFI_PADPD_CFR)) & 0x03ff0000 ) >> 16) #define GET_RG_CFR_EN (((REG32(ADR_WIFI_PADPD_CFR)) & 0x80000000 ) >> 31) #define GET_RG_RX_PADPD_DC_RM_LEAKY_FACTOR (((REG32(ADR_WIFI_PADPD_DC_RM)) & 0x00000007 ) >> 0) #define GET_RG_RX_PADPD_DC_RM_BYP (((REG32(ADR_WIFI_PADPD_DC_RM)) & 0x00000010 ) >> 4) #define GET_RG_TXIQ_CLP_THD_I (((REG32(ADR_WIFI_PADPD_TXIQ_CLIP_REG)) & 0x000003ff ) >> 0) #define GET_RG_TXIQ_CLP_THD_Q (((REG32(ADR_WIFI_PADPD_TXIQ_CLIP_REG)) & 0x03ff0000 ) >> 16) #define GET_RG_TX_SCALE (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x000000ff ) >> 0) #define GET_RG_TX_IQ_SWP (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x00010000 ) >> 16) #define GET_RG_TX_BB_SCALE_MANUAL (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x00100000 ) >> 20) #define GET_RG_TX_IQ_SRC (((REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) & 0x03000000 ) >> 24) #define GET_RG_TX_I_DC (((REG32(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG)) & 0x000003ff ) >> 0) #define GET_RG_TX_Q_DC (((REG32(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG)) & 0x03ff0000 ) >> 16) #define GET_RG_TX_I_OFFSET (((REG32(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG)) & 0x00ff0000 ) >> 16) #define GET_RG_TX_Q_OFFSET (((REG32(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG)) & 0xff000000 ) >> 24) #define GET_RG_DPD_AM_EN (((REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) & 0x00000001 ) >> 0) #define GET_RG_DPD_PM_EN (((REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) & 0x00000002 ) >> 1) #define GET_RG_DPD_PM_AMSEL (((REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) & 0x00000004 ) >> 2) #define GET_RG_DPD_020_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG0)) & 0x000003ff ) >> 0) #define GET_RG_DPD_040_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_060_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG1)) & 0x000003ff ) >> 0) #define GET_RG_DPD_080_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG1)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_0A0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG2)) & 0x000003ff ) >> 0) #define GET_RG_DPD_0C0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG2)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_0D0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG3)) & 0x000003ff ) >> 0) #define GET_RG_DPD_0E0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG3)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_0F0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG4)) & 0x000003ff ) >> 0) #define GET_RG_DPD_100_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG4)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_110_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG5)) & 0x000003ff ) >> 0) #define GET_RG_DPD_120_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG5)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_130_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG6)) & 0x000003ff ) >> 0) #define GET_RG_DPD_140_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG6)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_150_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG7)) & 0x000003ff ) >> 0) #define GET_RG_DPD_160_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG7)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_170_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG8)) & 0x000003ff ) >> 0) #define GET_RG_DPD_180_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG8)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_190_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG9)) & 0x000003ff ) >> 0) #define GET_RG_DPD_1A0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REG9)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_1B0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGA)) & 0x000003ff ) >> 0) #define GET_RG_DPD_1C0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGA)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_1D0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGB)) & 0x000003ff ) >> 0) #define GET_RG_DPD_1E0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGB)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_1F0_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGC)) & 0x000003ff ) >> 0) #define GET_RG_DPD_200_GAIN (((REG32(ADR_WIFI_PADPD_2G_GAIN_REGC)) & 0x03ff0000 ) >> 16) #define GET_RG_DPD_020_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG0)) & 0x00001fff ) >> 0) #define GET_RG_DPD_040_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG0)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_060_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG1)) & 0x00001fff ) >> 0) #define GET_RG_DPD_080_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG1)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_0A0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG2)) & 0x00001fff ) >> 0) #define GET_RG_DPD_0C0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG2)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_0D0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG3)) & 0x00001fff ) >> 0) #define GET_RG_DPD_0E0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG3)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_0F0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG4)) & 0x00001fff ) >> 0) #define GET_RG_DPD_100_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG4)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_110_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG5)) & 0x00001fff ) >> 0) #define GET_RG_DPD_120_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG5)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_130_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG6)) & 0x00001fff ) >> 0) #define GET_RG_DPD_140_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG6)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_150_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG7)) & 0x00001fff ) >> 0) #define GET_RG_DPD_160_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG7)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_170_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG8)) & 0x00001fff ) >> 0) #define GET_RG_DPD_180_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG8)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_190_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG9)) & 0x00001fff ) >> 0) #define GET_RG_DPD_1A0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REG9)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_1B0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGA)) & 0x00001fff ) >> 0) #define GET_RG_DPD_1C0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGA)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_1D0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGB)) & 0x00001fff ) >> 0) #define GET_RG_DPD_1E0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGB)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_1F0_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGC)) & 0x00001fff ) >> 0) #define GET_RG_DPD_200_PH (((REG32(ADR_WIFI_PADPD_2G_PHASE_REGC)) & 0x1fff0000 ) >> 16) #define GET_RG_DPD_BB_SCALE_5900 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0x000000ff ) >> 0) #define GET_RG_DPD_BB_SCALE_5700 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0x0000ff00 ) >> 8) #define GET_RG_DPD_BB_SCALE_5500 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0x00ff0000 ) >> 16) #define GET_RG_DPD_BB_SCALE_5100 (((REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) & 0xff000000 ) >> 24) #define GET_RG_DPD_BB_SCALE_2500 (((REG32(ADR_WIFI_PADPD_2G_BB_GAIN_REG)) & 0x000000ff ) >> 0) #define GET_RG_TX_SCALE_11B (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0x000000ff ) >> 0) #define GET_RG_TX_SCALE_11B_P0D5 (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0x0000ff00 ) >> 8) #define GET_RG_TX_SCALE_11G (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0x00ff0000 ) >> 16) #define GET_RG_TX_SCALE_11G_P0D5 (((REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) & 0xff000000 ) >> 24) #define GET_RG_HS5W_M_MD_EN (((REG32(ADR_HS5W_MD_EN)) & 0x00000001 ) >> 0) #define GET_RG_HS5W_M_MAN (((REG32(ADR_HS5W_MAN)) & 0x00000001 ) >> 0) #define GET_RG_HS5W_M_CMD6_EN (((REG32(ADR_HS5W_MAN)) & 0x02000000 ) >> 25) #define GET_RG_HS5W_M_CMD5_EN (((REG32(ADR_HS5W_MAN)) & 0x04000000 ) >> 26) #define GET_RG_HS5W_M_CMD4_EN (((REG32(ADR_HS5W_MAN)) & 0x08000000 ) >> 27) #define GET_RG_HS5W_M_CMD3_EN (((REG32(ADR_HS5W_MAN)) & 0x10000000 ) >> 28) #define GET_RG_HS5W_M_CMD2_EN (((REG32(ADR_HS5W_MAN)) & 0x20000000 ) >> 29) #define GET_RG_HS5W_M_CMD1_EN (((REG32(ADR_HS5W_MAN)) & 0x40000000 ) >> 30) #define GET_RG_HS5W_M_CMD0_EN (((REG32(ADR_HS5W_MAN)) & 0x80000000 ) >> 31) #define GET_RG_HS5W_M_RF_PHY_MODE (((REG32(ADR_HS5W_MAN_SET_ADD0)) & 0x00000007 ) >> 0) #define GET_RG_HS5W_M_CAL_INDEX (((REG32(ADR_HS5W_MAN_SET_ADD1)) & 0x0000001f ) >> 0) #define GET_RG_HS5W_M_PGAGC (((REG32(ADR_HS5W_MAN_SET_ADD2)) & 0x0000000f ) >> 0) #define GET_RG_HS5W_M_RFGC (((REG32(ADR_HS5W_MAN_SET_ADD2)) & 0x00000030 ) >> 4) #define GET_RG_HS5W_M_TXPWRLVL (((REG32(ADR_HS5W_MAN_SET_ADD3)) & 0x0000003f ) >> 0) #define GET_RG_HS5W_M_SX_RFCTRL_CH (((REG32(ADR_HS5W_MAN_SET_ADD4_CH)) & 0x000007ff ) >> 0) #define GET_RG_HS5W_M_SX5GB_RFCTRL_CH (((REG32(ADR_HS5W_MAN_SET_ADD4_CH_5GB)) & 0x000007ff ) >> 0) #define GET_RG_HS5W_M_SX_RFCTRL_F (((REG32(ADR_HS5W_MAN_SET_ADD4_F)) & 0x00ffffff ) >> 0) #define GET_RG_HS5W_M_SX_RFCH_MAP_EN (((REG32(ADR_HS5W_MAN_SET_ADD4_F)) & 0x80000000 ) >> 31) #define GET_RG_HS5W_M_SX5GB_RFCTRL_F (((REG32(ADR_HS5W_MAN_SET_ADD4_F_5GB)) & 0x00ffffff ) >> 0) #define GET_RG_HS5W_M_SX5GB_RFCH_MAP_EN (((REG32(ADR_HS5W_MAN_SET_ADD4_F_5GB)) & 0x80000000 ) >> 31) #define GET_RG_HS5W_M_SX_CHANNEL (((REG32(ADR_HS5W_MAN_SET_ADD5)) & 0x000000ff ) >> 0) #define GET_RG_HS5W_M_SX5GB_CHANNEL (((REG32(ADR_HS5W_MAN_SET_ADD5_5GB)) & 0x000000ff ) >> 0) #define GET_RG_HS5W_M_PHY_BW (((REG32(ADR_HS5W_MAN_SET_ADD6)) & 0x00000003 ) >> 0) #define GET_RG_RESERVED_DPD (((REG32(ADR_WIFI_PADPD_RESERVED_REG)) & 0xffffffff ) >> 0) #define GET_RG_XO_LDO_LEVEL (((REG32(ADR_PMU_REG_1)) & 0x00000007 ) >> 0) #define GET_RG_EN_LDO_XO_IQUP (((REG32(ADR_PMU_REG_1)) & 0x00000010 ) >> 4) #define GET_RG_EN_LDO_XO_BYP (((REG32(ADR_PMU_REG_1)) & 0x00000020 ) >> 5) #define GET_RG_EN_DLDO_BYP (((REG32(ADR_PMU_REG_1)) & 0x00000040 ) >> 6) #define GET_RG_EN_DLDO_HALF_IQ (((REG32(ADR_PMU_REG_1)) & 0x00000080 ) >> 7) #define GET_RG_XO_CBANKI (((REG32(ADR_PMU_REG_1)) & 0x0001ff00 ) >> 8) #define GET_RG_XO_CBANKO (((REG32(ADR_PMU_REG_1)) & 0x03fe0000 ) >> 17) #define GET_RG_EN_FDB (((REG32(ADR_PMU_REG_1)) & 0x04000000 ) >> 26) #define GET_RG_FDB_BYPASS (((REG32(ADR_PMU_REG_1)) & 0x08000000 ) >> 27) #define GET_RG_FDB_DUTY_LTH (((REG32(ADR_PMU_REG_1)) & 0x30000000 ) >> 28) #define GET_RG_EN_XOTEST (((REG32(ADR_PMU_REG_1)) & 0x40000000 ) >> 30) #define GET_RG_HW_WAKE_XOSC (((REG32(ADR_PMU_REG_1)) & 0x80000000 ) >> 31) #define GET_RG_EN_FDB_DCC_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000001 ) >> 0) #define GET_RG_EN_FDB_DELAYC_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000002 ) >> 1) #define GET_RG_EN_FDB_DELAYF_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000004 ) >> 2) #define GET_RG_EN_FDB_PHASESWAP_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000008 ) >> 3) #define GET_RG_FDB_PHASESWAP_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000010 ) >> 4) #define GET_RG_CLOCK_BF_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000020 ) >> 5) #define GET_RG_FDB_CDELAY_MUAL (((REG32(ADR_PMU_REG_2)) & 0x00000f00 ) >> 8) #define GET_RG_FDB_FDELAY_MUAL (((REG32(ADR_PMU_REG_2)) & 0x0000f000 ) >> 12) #define GET_RG_XO_TIMMER (((REG32(ADR_PMU_REG_2)) & 0x003f0000 ) >> 16) #define GET_RG_DPL_SETTLING_TIMMER (((REG32(ADR_PMU_REG_2)) & 0x00c00000 ) >> 22) #define GET_RG_FDB_RDELAYF (((REG32(ADR_PMU_REG_2)) & 0x03000000 ) >> 24) #define GET_RG_FDB_RDELAYS (((REG32(ADR_PMU_REG_2)) & 0x0c000000 ) >> 26) #define GET_RG_FDB_RECAL_TIMMER (((REG32(ADR_PMU_REG_2)) & 0x30000000 ) >> 28) #define GET_RG_EN_FDB_RECAL (((REG32(ADR_PMU_REG_2)) & 0x40000000 ) >> 30) #define GET_RG_LOAD_RFTABLE_RDY (((REG32(ADR_PMU_REG_2)) & 0x80000000 ) >> 31) #define GET_RG_DCDC_MODE (((REG32(ADR_PMU_REG_3)) & 0x00000001 ) >> 0) #define GET_RG_DLDO_LEVEL (((REG32(ADR_PMU_REG_3)) & 0x0000000e ) >> 1) #define GET_RG_BUCK_LEVEL (((REG32(ADR_PMU_REG_3)) & 0x000000f0 ) >> 4) #define GET_RG_DLDO_BOOST_IQ (((REG32(ADR_PMU_REG_3)) & 0x00000100 ) >> 8) #define GET_RG_BUCK_EN_PSM (((REG32(ADR_PMU_REG_3)) & 0x00000200 ) >> 9) #define GET_RG_BUCK_PSM_VTH (((REG32(ADR_PMU_REG_3)) & 0x00000400 ) >> 10) #define GET_RG_BUCK_VREF_SEL (((REG32(ADR_PMU_REG_3)) & 0x00000800 ) >> 11) #define GET_RG_LDO_LEVEL_EFUSE (((REG32(ADR_PMU_REG_3)) & 0x00007000 ) >> 12) #define GET_RG_EN_LDO_EFUSE (((REG32(ADR_PMU_REG_3)) & 0x00010000 ) >> 16) #define GET_RG_DCDC_PULLLOW_CON (((REG32(ADR_PMU_REG_3)) & 0x00040000 ) >> 18) #define GET_RG_DCDC_RES2_CON (((REG32(ADR_PMU_REG_3)) & 0x00080000 ) >> 19) #define GET_RG_DCDC_RES_CON (((REG32(ADR_PMU_REG_3)) & 0x00100000 ) >> 20) #define GET_RG_RTC_RS1 (((REG32(ADR_PMU_REG_3)) & 0x00200000 ) >> 21) #define GET_RG_RTC_RS2 (((REG32(ADR_PMU_REG_3)) & 0x00400000 ) >> 22) #define GET_RG_DCDC_CLK (((REG32(ADR_PMU_REG_3)) & 0x0f000000 ) >> 24) #define GET_RG_BUCK_RCZERO (((REG32(ADR_PMU_REG_3)) & 0x10000000 ) >> 28) #define GET_RG_BUCK_SLOP (((REG32(ADR_PMU_REG_3)) & 0x60000000 ) >> 29) #define GET_RG_RTC_OFFSET (((REG32(ADR_PMU_REG_4)) & 0x000000ff ) >> 0) #define GET_RG_RTC_CAL_TARGET_COUNT (((REG32(ADR_PMU_REG_4)) & 0x000fff00 ) >> 8) #define GET_RG_RTC_OSC_RES_SW_MANUAL (((REG32(ADR_PMU_REG_4)) & 0x3ff00000 ) >> 20) #define GET_RG_RTC_CAL_MODE (((REG32(ADR_PMU_REG_4)) & 0x40000000 ) >> 30) #define GET_RG_SEL_DPLL_CLK (((REG32(ADR_PMU_REG_4)) & 0x80000000 ) >> 31) #define GET_RG_RTC_OSC_RES_SW_MANUAL_EN (((REG32(ADR_PMU_REG_5)) & 0x00000001 ) >> 0) #define GET_RG_EN_RTC_CAL (((REG32(ADR_PMU_REG_5)) & 0x00000002 ) >> 1) #define GET_RO_FDB_CDELAY (((REG32(ADR_PMU_REG_6)) & 0x0000000f ) >> 0) #define GET_RO_FDB_FDELAY (((REG32(ADR_PMU_REG_6)) & 0x000000f0 ) >> 4) #define GET_RO_FDB_PHASESWAP (((REG32(ADR_PMU_REG_6)) & 0x00000100 ) >> 8) #define GET_RO_XO_RDY (((REG32(ADR_PMU_REG_6)) & 0x00000200 ) >> 9) #define GET_RO_RTC_OSC_CAL_RES_RDY (((REG32(ADR_PMU_REG_6)) & 0x00000400 ) >> 10) #define GET_RO_RTC_OSC_RES_SW (((REG32(ADR_PMU_REG_6)) & 0x001ff800 ) >> 11) #define GET_RG_PMU_ENTER_SLEEP_MODE (((REG32(ADR_PMU_SLEEP_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_SLEEP_METHOD (((REG32(ADR_PMU_SLEEP_REG_1)) & 0x00000002 ) >> 1) #define GET_RG_INT_PMU_MASK (((REG32(ADR_PMU_SLEEP_REG_1)) & 0x00000004 ) >> 2) #define GET_RG_SLEEP_WAKE_CNT (((REG32(ADR_PMU_SLEEP_REG_2)) & 0xffffffff ) >> 0) #define GET_RG_SEC_CNT_VALUE (((REG32(ADR_PMU_RTC_REG_0)) & 0x00007fff ) >> 0) #define GET_RG_RTC_EN (((REG32(ADR_PMU_RTC_REG_0)) & 0x00008000 ) >> 15) #define GET_RO_RTC_TICK_CNT (((REG32(ADR_PMU_RTC_REG_0)) & 0x7fff0000 ) >> 16) #define GET_RG_RTC_INT_SEC_MASK (((REG32(ADR_PMU_RTC_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_RTC_INT_ALARM_MASK (((REG32(ADR_PMU_RTC_REG_1)) & 0x00000002 ) >> 1) #define GET_RO_PMU_WAKE_TRIG_EVENT (((REG32(ADR_PMU_RTC_REG_1)) & 0x00007000 ) >> 12) #define GET_RO_RTC_INT_SEC (((REG32(ADR_PMU_RTC_REG_1)) & 0x00010000 ) >> 16) #define GET_RO_RTC_INT_ALARM (((REG32(ADR_PMU_RTC_REG_1)) & 0x00020000 ) >> 17) #define GET_RG_RTC_SEC_START_CNT (((REG32(ADR_PMU_RTC_REG_2)) & 0xffffffff ) >> 0) #define GET_RG_RTC_SEC_ALARM_VALUE (((REG32(ADR_PMU_RTC_REG_3)) & 0xffffffff ) >> 0) #define GET_RG_FPGA_CLK_REF_40M_EN (((REG32(ADR_PMU_CTRL_REG)) & 0x00000001 ) >> 0) #define GET_RG_CLK_RTC_SW (((REG32(ADR_PMU_CTRL_REG)) & 0x00000002 ) >> 1) #define GET_RG_PHY_RST_N (((REG32(ADR_PMU_CTRL_REG)) & 0x00000010 ) >> 4) #define GET_RO_PMU_STATE (((REG32(ADR_PMU_STATE_REG)) & 0x00000007 ) >> 0) #define GET_RO_AD_VBAT_OK (((REG32(ADR_PMU_STATE_REG)) & 0x00000010 ) >> 4) #define GET_RG_DP_LDO_LEVEL (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000007 ) >> 0) #define GET_RG_EN_LDO_DP_BYP (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000008 ) >> 3) #define GET_RG_DP_AUTOMAP_EN (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000020 ) >> 5) #define GET_RG_EN_ADC_320M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000080 ) >> 7) #define GET_RG_EN_IOTADC_160M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000100 ) >> 8) #define GET_RG_EN_MAC_80M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000200 ) >> 9) #define GET_RG_EN_MAC_96M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000400 ) >> 10) #define GET_RG_EN_MAC_120M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00000800 ) >> 11) #define GET_RG_EN_PHY_80M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00001000 ) >> 12) #define GET_RG_EN_PHY_160M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00002000 ) >> 13) #define GET_RG_EN_PHY_320M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00004000 ) >> 14) #define GET_RG_EN_MAC_160M (((REG32(ADR_PMU_DPLL_REG_0)) & 0x00008000 ) >> 15) #define GET_RG_DP_XTAL_FREQ (((REG32(ADR_PMU_DPLL_REG_0)) & 0x000f0000 ) >> 16) #define GET_RG_DP_BBPLL_PD (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000001 ) >> 0) #define GET_RG_DP_BBPLL_BP (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000002 ) >> 1) #define GET_RG_EN_DP_MANUAL (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000004 ) >> 2) #define GET_RG_DP_FREF_DOUB (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000008 ) >> 3) #define GET_RG_DP_DAC320_DIVBY2 (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000010 ) >> 4) #define GET_RG_DP_ADC320_DIVBY2_BT (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000020 ) >> 5) #define GET_RG_DP_ADC320_DIVBY2_WF (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000040 ) >> 6) #define GET_RG_EN_DPL_MOD (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000100 ) >> 8) #define GET_RG_DPL_MOD_ORDER (((REG32(ADR_PMU_DPLL_REG_1)) & 0x00000600 ) >> 9) #define GET_RG_DP_REFDIV (((REG32(ADR_PMU_DPLL_REG_1)) & 0x0003f800 ) >> 11) #define GET_RG_DP_FODIV (((REG32(ADR_PMU_DPLL_REG_1)) & 0x01fc0000 ) >> 18) #define GET_RG_EN_LDO_DP_IQUP (((REG32(ADR_PMU_DPLL_REG_1)) & 0x04000000 ) >> 26) #define GET_RG_DP_OD_TEST (((REG32(ADR_PMU_DPLL_REG_1)) & 0x08000000 ) >> 27) #define GET_RG_DP_BBPLL_TESTSEL (((REG32(ADR_PMU_DPLL_REG_1)) & 0x70000000 ) >> 28) #define GET_RG_DP_BBPLL_ICP (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000003 ) >> 0) #define GET_RG_DP_BBPLL_IDUAL (((REG32(ADR_PMU_DPLL_REG_2)) & 0x0000000c ) >> 2) #define GET_RG_DP_CP_IOSTPOL (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000010 ) >> 4) #define GET_RG_DP_CP_IOST (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000060 ) >> 5) #define GET_RG_DP_PFD_PFDSEL (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000080 ) >> 7) #define GET_RG_DP_BBPLL_PFD_DLY (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00000300 ) >> 8) #define GET_RG_DP_RP (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00003800 ) >> 11) #define GET_RG_DP_RHP (((REG32(ADR_PMU_DPLL_REG_2)) & 0x0000c000 ) >> 14) #define GET_RG_EN_DP_VT_MON (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00020000 ) >> 17) #define GET_RG_DP_VT_TH_HI (((REG32(ADR_PMU_DPLL_REG_2)) & 0x000c0000 ) >> 18) #define GET_RG_DP_VT_TH_LO (((REG32(ADR_PMU_DPLL_REG_2)) & 0x00300000 ) >> 20) #define GET_RG_DP_BBPLL_BS (((REG32(ADR_PMU_DPLL_REG_2)) & 0x1f800000 ) >> 23) #define GET_RG_DP_BBPLL_SDM_EDGE (((REG32(ADR_PMU_DPLL_REG_2)) & 0x80000000 ) >> 31) #define GET_RG_DPL_RFCTRL_F (((REG32(ADR_PMU_DPLL_REG_3)) & 0x00ffffff ) >> 0) #define GET_RG_DPL_RFCTRL_CH (((REG32(ADR_PMU_DPLL_REG_3)) & 0xff000000 ) >> 24) #define GET_RG_DCDC_MODE_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x00000001 ) >> 0) #define GET_RG_DLDO_LEVEL_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x0000000e ) >> 1) #define GET_RG_BUCK_LEVEL_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x000000f0 ) >> 4) #define GET_RG_XO_CBANKI_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x0001ff00 ) >> 8) #define GET_RG_XO_CBANKO_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x03fe0000 ) >> 17) #define GET_RG_EN_DLDO_HALF_IQ_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x04000000 ) >> 26) #define GET_RG_EN_DLDO_BYP_AUTO (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x08000000 ) >> 27) #define GET_RG_HW_WAKE_XOSC_SLP (((REG32(ADR_PMU_SLEEP_MODE_REG)) & 0x80000000 ) >> 31) #define GET_RG_RAM_00 (((REG32(ADR_PMU_RAM_00)) & 0xffffffff ) >> 0) #define GET_RG_RAM_01 (((REG32(ADR_PMU_RAM_01)) & 0xffffffff ) >> 0) #define GET_RG_RAM_02 (((REG32(ADR_PMU_RAM_02)) & 0xffffffff ) >> 0) #define GET_RG_RAM_03 (((REG32(ADR_PMU_RAM_03)) & 0xffffffff ) >> 0) #define GET_RG_RAM_04 (((REG32(ADR_PMU_RAM_04)) & 0xffffffff ) >> 0) #define GET_RG_RAM_05 (((REG32(ADR_PMU_RAM_05)) & 0xffffffff ) >> 0) #define GET_RG_RAM_06 (((REG32(ADR_PMU_RAM_06)) & 0xffffffff ) >> 0) #define GET_RG_RAM_07 (((REG32(ADR_PMU_RAM_07)) & 0xffffffff ) >> 0) #define GET_RG_RAM_08 (((REG32(ADR_PMU_RAM_08)) & 0xffffffff ) >> 0) #define GET_RG_RAM_09 (((REG32(ADR_PMU_RAM_09)) & 0xffffffff ) >> 0) #define GET_RG_RAM_10 (((REG32(ADR_PMU_RAM_10)) & 0xffffffff ) >> 0) #define GET_RG_RAM_11 (((REG32(ADR_PMU_RAM_11)) & 0xffffffff ) >> 0) #define GET_RG_RAM_12 (((REG32(ADR_PMU_RAM_12)) & 0xffffffff ) >> 0) #define GET_RG_RAM_13 (((REG32(ADR_PMU_RAM_13)) & 0xffffffff ) >> 0) #define GET_RG_RAM_14 (((REG32(ADR_PMU_RAM_14)) & 0xffffffff ) >> 0) #define GET_RG_RAM_15 (((REG32(ADR_PMU_RAM_15)) & 0xffffffff ) >> 0) #define GET_RG_PMDLBK (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000001 ) >> 0) #define GET_RG_DAC_LBK_EDGE_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000002 ) >> 1) #define GET_RG_RSSI_EDGE_SEL_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000004 ) >> 2) #define GET_RG_SIGN_SWAP_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000010 ) >> 4) #define GET_RG_IQ_SWAP_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000020 ) >> 5) #define GET_RG_Q_INV_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000040 ) >> 6) #define GET_RG_I_INV_BB (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000080 ) >> 7) #define GET_RG_BYPASS_ACI (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000100 ) >> 8) #define GET_RG_LBK_ANA_PATH (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000200 ) >> 9) #define GET_RG_LBK_DIG_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000400 ) >> 10) #define GET_RG_RF_5G_BAND (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00000800 ) >> 11) #define GET_RG_PRIMARY_CH_SIDE (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00004000 ) >> 14) #define GET_RG_SYSTEM_BW (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00008000 ) >> 15) #define GET_RG_11B_ACI_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x00010000 ) >> 16) #define GET_RG_BB_CLK_SEL (((REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) & 0x80000000 ) >> 31) #define GET_RG_PHY_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000001 ) >> 0) #define GET_RG_PHYRX_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000002 ) >> 1) #define GET_RG_PHYTX_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000004 ) >> 2) #define GET_RG_PHY11GN_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000008 ) >> 3) #define GET_RG_PHY11B_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000010 ) >> 4) #define GET_RG_PHYRXFIFO_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000020 ) >> 5) #define GET_RG_PHYTXFIFO_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000040 ) >> 6) #define GET_RG_PHY11BGN_MD_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00000100 ) >> 8) #define GET_RG_FORCE_11GN_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00001000 ) >> 12) #define GET_RG_FORCE_11B_EN (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x00002000 ) >> 13) #define GET_RG_PHY_IQ_TRIG_SEL (((REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) & 0x000f0000 ) >> 16) #define GET_SVN_VERSION (((REG32(ADR_WIFI_PHY_COMMON_VERSION_REG)) & 0xffffffff ) >> 0) #define GET_RG_LENGTH (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x0000ffff ) >> 0) #define GET_RG_PKT_MODE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00070000 ) >> 16) #define GET_RG_CH_BW (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00380000 ) >> 19) #define GET_RG_PRM (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00400000 ) >> 22) #define GET_RG_SHORTGI (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x00800000 ) >> 23) #define GET_RG_RATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) & 0x7f000000 ) >> 24) #define GET_RG_L_LENGTH (((REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) & 0x00000fff ) >> 0) #define GET_RG_L_RATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) & 0x00007000 ) >> 12) #define GET_RG_SERVICE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) & 0xffff0000 ) >> 16) #define GET_RG_SMOOTHING (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000001 ) >> 0) #define GET_RG_NO_SOUND (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000002 ) >> 1) #define GET_RG_AGGREGATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000004 ) >> 2) #define GET_RG_STBC (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000018 ) >> 3) #define GET_RG_FEC (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00000020 ) >> 5) #define GET_RG_N_ESS (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x000000c0 ) >> 6) #define GET_RG_TXPWRLVL (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00007f00 ) >> 8) #define GET_RG_BB_SCALE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) & 0x00ff0000 ) >> 16) #define GET_RG_TX_START (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00000001 ) >> 0) #define GET_RG_IFS_TIME (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x000000fc ) >> 2) #define GET_RG_CONTINUOUS_DATA (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00000100 ) >> 8) #define GET_RG_DATA_SEL (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00000600 ) >> 9) #define GET_RG_TX_D (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0x00ff0000 ) >> 16) #define GET_RG_IFS_TIME_EXT (((REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) & 0xff000000 ) >> 24) #define GET_RG_TX_CNT_TARGET (((REG32(ADR_WIFI_PHY_COMMON_DES_REG4)) & 0xffffffff ) >> 0) #define GET_RG_TXD_SEL (((REG32(ADR_WIFI_PHY_COMMON_TX_CONTROL)) & 0x00000c00 ) >> 10) #define GET_RG_TX_FREQ_OFFSET_DES (((REG32(ADR_WIFI_PHY_COMMON_DES_REG5)) & 0x0000ffff ) >> 0) #define GET_RG_DES_RATE (((REG32(ADR_WIFI_PHY_COMMON_DES_REG6)) & 0x000000ff ) >> 0) #define GET_RG_DES_MAN_EN (((REG32(ADR_WIFI_PHY_COMMON_DES_REG6)) & 0x80000000 ) >> 31) #define GET_RG_PGA_REFDB_SAT_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0x0000007f ) >> 0) #define GET_RG_PGA_REFDB_TOP_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0x00007f00 ) >> 8) #define GET_RG_PGA_REF_UND_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_RF_REF_SAT_B (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) & 0xf0000000 ) >> 28) #define GET_RG_PGA_REFDB_SAT_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0x0000007f ) >> 0) #define GET_RG_PGA_REFDB_TOP_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0x00007f00 ) >> 8) #define GET_RG_PGA_REF_UND_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0x03ff0000 ) >> 16) #define GET_RG_RF_REF_SAT_GN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) & 0xf0000000 ) >> 28) #define GET_RG_PGAGC_SET (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x0000000f ) >> 0) #define GET_RG_PGAGC_OW (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00000010 ) >> 4) #define GET_RG_RFGC_SET (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00000060 ) >> 5) #define GET_RG_RFGC_OW (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00000080 ) >> 7) #define GET_RG_WAIT_T_RXAGC (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00003f00 ) >> 8) #define GET_RG_RXAGC_SET (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00004000 ) >> 14) #define GET_RG_RXAGC_OW (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x00008000 ) >> 15) #define GET_RG_WAIT_T_FINAL (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x003f0000 ) >> 16) #define GET_RG_WAIT_T (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) & 0x3f000000 ) >> 24) #define GET_RG_ULG_PGA_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x0000000f ) >> 0) #define GET_RG_LG_PGA_UND_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x000000f0 ) >> 4) #define GET_RG_LG_PGA_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x00000f00 ) >> 8) #define GET_RG_LG_RF_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x0000f000 ) >> 12) #define GET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x000f0000 ) >> 16) #define GET_RG_HG_PGA_SAT2_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x00f00000 ) >> 20) #define GET_RG_HG_PGA_SAT1_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0x0f000000 ) >> 24) #define GET_RG_HG_RF_SAT_PGA_GAIN (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) & 0xf0000000 ) >> 28) #define GET_RG_MG_PGA_JB_TH (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) & 0x0000000f ) >> 0) #define GET_RG_MA_PGA_LOW_TH_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) & 0x001f0000 ) >> 16) #define GET_RG_MA_PGA_HIGH_TH_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) & 0x1f000000 ) >> 24) #define GET_RG_AGC_THRESHOLD (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x00003fff ) >> 0) #define GET_RG_ACI_POINT_CNT_LMT_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x007f0000 ) >> 16) #define GET_RG_ACI_DAGC_LEAKY_FACTOR_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x03000000 ) >> 24) #define GET_RG_ACI_DAGC_PWR_SEL_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) & 0x10000000 ) >> 28) #define GET_RG_ACI_DAGC_TARGET_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x0000007f ) >> 0) #define GET_RG_ACI_GAIN_INI_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x0000ff00 ) >> 8) #define GET_RG_ACI_GAIN_SET_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x00ff0000 ) >> 16) #define GET_RG_ACI_GAIN_OW_11B (((REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) & 0x80000000 ) >> 31) #define GET_RG_ACI_POINT_CNT_LMT_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0x000000ff ) >> 0) #define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0x00000300 ) >> 8) #define GET_RG_ACI_DAGC_PWR_SEL_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0x00001000 ) >> 12) #define GET_RG_ACI_DAGC_DONE_CNT_LMT_11GN (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) & 0xff000000 ) >> 24) #define GET_RG_ACI_DAGC_TARGET_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) & 0x0000007f ) >> 0) #define GET_RG_ACI_GAIN_SET_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) & 0x01ff0000 ) >> 16) #define GET_RG_ACI_GAIN_OW_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) & 0x80000000 ) >> 31) #define GET_RO_CCA_PWR_MA_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x0000007f ) >> 0) #define GET_RO_CCA_PWR_MA_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x00007f00 ) >> 8) #define GET_RO_CCA_PWR_MA_11B (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x007f0000 ) >> 16) #define GET_RO_ED_STATE (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x01000000 ) >> 24) #define GET_RO_2ND_ED_STATE (((REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) & 0x02000000 ) >> 25) #define GET_RO_PGA_PWR_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x00003fff ) >> 0) #define GET_RO_RF_PWR_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x000f0000 ) >> 16) #define GET_RO_PGAGC_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x0f000000 ) >> 24) #define GET_RO_RFGC_FF1 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) & 0x30000000 ) >> 28) #define GET_RO_PGA_PWR_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x00003fff ) >> 0) #define GET_RO_RF_PWR_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x000f0000 ) >> 16) #define GET_RO_PGAGC_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x0f000000 ) >> 24) #define GET_RO_RFGC_FF2 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) & 0x30000000 ) >> 28) #define GET_RO_PGA_PWR_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x00003fff ) >> 0) #define GET_RO_RF_PWR_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x000f0000 ) >> 16) #define GET_RO_PGAGC_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x0f000000 ) >> 24) #define GET_RO_RFGC_FF3 (((REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) & 0x30000000 ) >> 28) #define GET_RG_5G_DC_RM_LEAKY_FACTOR_T3 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00000070 ) >> 4) #define GET_RG_5G_DC_RM_LEAKY_FACTOR_T2 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00000700 ) >> 8) #define GET_RG_5G_DC_RM_LEAKY_FACTOR_T1 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00007000 ) >> 12) #define GET_RG_DC_RM_BYP (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00010000 ) >> 16) #define GET_RG_DC_RM_LEAKY_FACTOR_T3 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x00700000 ) >> 20) #define GET_RG_DC_RM_LEAKY_FACTOR_T2 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x07000000 ) >> 24) #define GET_RG_DC_RM_LEAKY_FACTOR_T1 (((REG32(ADR_WIFI_PHY_COMMON_RXDC)) & 0x70000000 ) >> 28) #define GET_RO_Q_DC_OUT (((REG32(ADR_WIFI_PHY_COMMON_RXDC_RO)) & 0x000003ff ) >> 0) #define GET_RO_I_DC_OUT (((REG32(ADR_WIFI_PHY_COMMON_RXDC_RO)) & 0x03ff0000 ) >> 16) #define GET_RG_TBUS_SEL (((REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) & 0x0000000f ) >> 0) #define GET_RG_RSSI_OFFSET (((REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) & 0x00ff0000 ) >> 16) #define GET_RG_RSSI_INV (((REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) & 0x01000000 ) >> 24) #define GET_RO_MRX_EN_CNT (((REG32(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG)) & 0x0000ffff ) >> 0) #define GET_RG_MRX_EN_CNT_RST_N (((REG32(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG)) & 0x80000000 ) >> 31) #define GET_RG_EDCCA_AVG_T (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_0)) & 0x00000007 ) >> 0) #define GET_RG_EDCCA_STAT_EN (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_0)) & 0x00000010 ) >> 4) #define GET_RO_EDCCA_PRIMARY_PRD (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_1)) & 0x0000ffff ) >> 0) #define GET_RO_PRIMARY_EDCCA (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_1)) & 0xffff0000 ) >> 16) #define GET_RO_EDCCA_SECONDARY_PRD (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_2)) & 0x0000ffff ) >> 0) #define GET_RO_SECONDARY_EDCCA (((REG32(ADR_WIFI_PHY_COMMON_EDCCA_2)) & 0xffff0000 ) >> 16) #define GET_RG_AGC_RELOCK_PWR_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x00003fff ) >> 0) #define GET_RG_AGC_RELOCK_CNT_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x003f0000 ) >> 16) #define GET_RG_AGC_RELOCK_SEL (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x03000000 ) >> 24) #define GET_RG_AGC_RELOCK_EN (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x10000000 ) >> 28) #define GET_RG_AGC_RELOCK_11GN (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x40000000 ) >> 30) #define GET_RG_AGC_RELOCK_11B (((REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) & 0x80000000 ) >> 31) #define GET_RG_AGC_RELOCK_PWR_DIFFDB_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_2)) & 0x0000007f ) >> 0) #define GET_RG_AGC_RELOCK_CNT_DIFFDB_TH (((REG32(ADR_WIFI_PHY_AGC_RELOCK_2)) & 0x003f0000 ) >> 16) #define GET_RG_MTX_LEN_LOWER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0)) & 0x0000ffff ) >> 0) #define GET_RG_MTX_LEN_UPPER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0)) & 0xffff0000 ) >> 16) #define GET_RG_MTX_LEN_LOWER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1)) & 0x0000ffff ) >> 0) #define GET_RG_MTX_LEN_UPPER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1)) & 0xffff0000 ) >> 16) #define GET_RG_MRX_LEN_LOWER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0)) & 0x0000ffff ) >> 0) #define GET_RG_MRX_LEN_UPPER_TH_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0)) & 0xffff0000 ) >> 16) #define GET_RG_MRX_LEN_LOWER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1)) & 0x0000ffff ) >> 0) #define GET_RG_MRX_LEN_UPPER_TH_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1)) & 0xffff0000 ) >> 16) #define GET_RO_MTX_LEN_CNT_1 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO)) & 0x0000ffff ) >> 0) #define GET_RO_MTX_LEN_CNT_0 (((REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO)) & 0xffff0000 ) >> 16) #define GET_RO_MRX_LEN_CNT_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO)) & 0x0000ffff ) >> 0) #define GET_RO_MRX_LEN_CNT_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO)) & 0xffff0000 ) >> 16) #define GET_RG_MRX_TYPE (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x000000ff ) >> 0) #define GET_RG_MRX_TYPE_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x00001f00 ) >> 8) #define GET_RG_MTX_TYPE (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x00ff0000 ) >> 16) #define GET_RG_MTX_TYPE_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) & 0x1f000000 ) >> 24) #define GET_RO_MRX_TYPE_CNT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO)) & 0x0000ffff ) >> 0) #define GET_RO_MTX_TYPE_CNT (((REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO)) & 0xffff0000 ) >> 16) #define GET_RG_ACI_POINT_CNT_LMT_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) & 0x000000ff ) >> 0) #define GET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) & 0x00000300 ) >> 8) #define GET_RG_ACI_DAGC_PWR_SEL_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) & 0x00001000 ) >> 12) #define GET_RG_ACI_DAGC_TARGET_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) & 0x0000007f ) >> 0) #define GET_RG_ACI_GAIN_SET_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) & 0x01ff0000 ) >> 16) #define GET_RG_ACI_GAIN_OW_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) & 0x80000000 ) >> 31) #define GET_RG_ACI_GAIN_INI_11GN_HT40 (((REG32(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG)) & 0x000001ff ) >> 0) #define GET_RG_ACI_GAIN_INI_11GN_HT20 (((REG32(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG)) & 0x01ff0000 ) >> 16) #define GET_RG_MAC_PKT_MODE (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000001 ) >> 0) #define GET_RG_MAC_PKT_AGGREGATE (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000002 ) >> 1) #define GET_RG_MAC_PKT_ADDR4_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000010 ) >> 4) #define GET_RG_MAC_PKT_SEQ_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000020 ) >> 5) #define GET_RG_MAC_PKT_ADDR3_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000040 ) >> 6) #define GET_RG_MAC_PKT_ADDR2_ON (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000080 ) >> 7) #define GET_RG_MAC_PKT_AGGREGATE_NUM (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0x00000f00 ) >> 8) #define GET_RG_MAC_PKT_PLD_LENGTH (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) & 0xffff0000 ) >> 16) #define GET_RG_MAC_PKT_DUR (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1)) & 0x0000ffff ) >> 0) #define GET_RG_MAC_PKT_FC (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1)) & 0xffff0000 ) >> 16) #define GET_RG_MAC_PKT_ADDR1_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2)) & 0xffffffff ) >> 0) #define GET_RG_MAC_PKT_ADDR1_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3)) & 0x0000ffff ) >> 0) #define GET_RG_MAC_PKT_ADDR2_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4)) & 0xffffffff ) >> 0) #define GET_RG_MAC_PKT_ADDR2_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5)) & 0x0000ffff ) >> 0) #define GET_RG_MAC_PKT_ADDR3_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6)) & 0xffffffff ) >> 0) #define GET_RG_MAC_PKT_ADDR3_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7)) & 0x0000ffff ) >> 0) #define GET_RG_MAC_PKT_SEQ (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8)) & 0x0000ffff ) >> 0) #define GET_RG_MAC_PKT_ADDR4_31_0 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9)) & 0xffffffff ) >> 0) #define GET_RG_MAC_PKT_ADDR4_47_32 (((REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A)) & 0x0000ffff ) >> 0) #define GET_RG_BB_SCALE_BARKER_CCK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0)) & 0x000000ff ) >> 0) #define GET_RG_BB_SCALE_MAN_EN (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0)) & 0x00010000 ) >> 16) #define GET_RG_BB_SCALE_LEGACY_64QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0x000000ff ) >> 0) #define GET_RG_BB_SCALE_LEGACY_16QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0x0000ff00 ) >> 8) #define GET_RG_BB_SCALE_LEGACY_QPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0x00ff0000 ) >> 16) #define GET_RG_BB_SCALE_LEGACY_BPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) & 0xff000000 ) >> 24) #define GET_RG_BB_SCALE_HT20_64QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0x000000ff ) >> 0) #define GET_RG_BB_SCALE_HT20_16QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0x0000ff00 ) >> 8) #define GET_RG_BB_SCALE_HT20_QPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0x00ff0000 ) >> 16) #define GET_RG_BB_SCALE_HT20_BPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) & 0xff000000 ) >> 24) #define GET_RG_BB_SCALE_HT40_64QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0x000000ff ) >> 0) #define GET_RG_BB_SCALE_HT40_16QAM (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0x0000ff00 ) >> 8) #define GET_RG_BB_SCALE_HT40_QPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0x00ff0000 ) >> 16) #define GET_RG_BB_SCALE_HT40_BPSK (((REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) & 0xff000000 ) >> 24) #define GET_RG_RF_PWR_BARKER_CCK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0)) & 0x0000007f ) >> 0) #define GET_RG_RF_PWR_MAN_EN (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0)) & 0x00010000 ) >> 16) #define GET_RG_RF_PWR_LEGACY_64QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x0000007f ) >> 0) #define GET_RG_RF_PWR_LEGACY_16QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x00007f00 ) >> 8) #define GET_RG_RF_PWR_LEGACY_QPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x007f0000 ) >> 16) #define GET_RG_RF_PWR_LEGACY_BPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) & 0x7f000000 ) >> 24) #define GET_RG_RF_PWR_HT20_64QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x0000007f ) >> 0) #define GET_RG_RF_PWR_HT20_16QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x00007f00 ) >> 8) #define GET_RG_RF_PWR_HT20_QPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x007f0000 ) >> 16) #define GET_RG_RF_PWR_HT20_BPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) & 0x7f000000 ) >> 24) #define GET_RG_RF_PWR_HT40_64QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x0000007f ) >> 0) #define GET_RG_RF_PWR_HT40_16QAM (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x00007f00 ) >> 8) #define GET_RG_RF_PWR_HT40_QPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x007f0000 ) >> 16) #define GET_RG_RF_PWR_HT40_BPSK (((REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) & 0x7f000000 ) >> 24) #define GET_RG_RX_MONITOR_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000001 ) >> 0) #define GET_RG_RX_PKT_ADDR3_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000002 ) >> 1) #define GET_RG_RX_PKT_ADDR2_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000004 ) >> 2) #define GET_RG_RX_PKT_ADDR1_ON (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00000008 ) >> 3) #define GET_RG_RX_BEACON_TU (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0x00003ff0 ) >> 4) #define GET_RG_RX_PKT_TIMER_LMT (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) & 0xffff0000 ) >> 16) #define GET_RG_RX_BEACON_LOSS_CNT_LMT (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) & 0x000000ff ) >> 0) #define GET_RG_RX_BEACON_CRC_BYPASS (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) & 0x00000100 ) >> 8) #define GET_RG_RX_BEACON_INTERVAL (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) & 0xffff0000 ) >> 16) #define GET_RG_RX_PKT_FC (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_2)) & 0xffff0000 ) >> 16) #define GET_RG_RX_PKT_ADDR1_31_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_3)) & 0xffffffff ) >> 0) #define GET_RG_RX_PKT_ADDR1_47_32 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_4)) & 0x0000ffff ) >> 0) #define GET_RG_RX_PKT_ADDR2_31_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_5)) & 0xffffffff ) >> 0) #define GET_RG_RX_PKT_ADDR2_47_32 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_6)) & 0x0000ffff ) >> 0) #define GET_RG_RX_PKT_ADDR3_31_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_7)) & 0xffffffff ) >> 0) #define GET_RG_RX_PKT_ADDR3_47_32 (((REG32(ADR_WIFI_PHY_COMMON_RX_MON_8)) & 0x0000ffff ) >> 0) #define GET_RO_INTRP_RX_LOSS (((REG32(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO)) & 0x00000001 ) >> 0) #define GET_RO_RX_PKT_TIMER (((REG32(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO)) & 0xffff0000 ) >> 16) #define GET_RO_INTRP_RX_BEACON_LOSS (((REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) & 0x00000001 ) >> 0) #define GET_RO_RX_BEACON_LOSS_CNT (((REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) & 0x0000ff00 ) >> 8) #define GET_RO_RX_BEACON_CNT (((REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) & 0xffff0000 ) >> 16) #define GET_RG_RX_FIFO_FULL_CNT_EN (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL)) & 0x00000001 ) >> 0) #define GET_RG_TX_FIFO_EMPTY_CNT_EN (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL)) & 0x00000010 ) >> 4) #define GET_RO_RX_FIFO_FULL_CNT (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO)) & 0x0000ffff ) >> 0) #define GET_RO_TX_FIFO_EMPTY_CNT (((REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO)) & 0xffff0000 ) >> 16) #define GET_RG_BIST_EN_RX_FFT (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00000001 ) >> 0) #define GET_RG_BIST_MODE_RX_FFT (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00000010 ) >> 4) #define GET_RO_BIST_DONE_RX_FFT_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00010000 ) >> 16) #define GET_RO_BIST_FAIL_RX_FFT_1 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00020000 ) >> 17) #define GET_RO_BIST_DONE_RX_FFT_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00100000 ) >> 20) #define GET_RO_BIST_FAIL_RX_FFT_0 (((REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) & 0x00200000 ) >> 21) #define GET_RG_AUDIO_CLK_EN (((REG32(ADR_WIFI_PHY_AUDIO_CLK_CTRL)) & 0x00000001 ) >> 0) #define GET_RG_AUDIO_CLK_SEL (((REG32(ADR_WIFI_PHY_AUDIO_CLK_CTRL)) & 0x00000002 ) >> 1) #define GET_RO_CSTATE_PKT (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00000003 ) >> 0) #define GET_RO_MRX_RX_EN (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00000010 ) >> 4) #define GET_RO_CSTATE_AGC (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00000300 ) >> 8) #define GET_RO_AGC_START_80M (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00001000 ) >> 12) #define GET_RO_CSTATE_RX (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x000f0000 ) >> 16) #define GET_RO_TX_IP (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x00100000 ) >> 20) #define GET_RO_CSTATE_TX (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x0f000000 ) >> 24) #define GET_RO_MAC_PHY_TRX_EN_SYNC (((REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) & 0x10000000 ) >> 28) #define GET_RG_RESERVED_CMM (((REG32(ADR_WIFI_PHY_COMMON_RESERVED_REG)) & 0xffffffff ) >> 0) #define GET_RG_BB_RISE_TIME_11B_TX (((REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) & 0x000000ff ) >> 0) #define GET_RG_BB_FALL_TIME_11B_TX (((REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) & 0x0000ff00 ) >> 8) #define GET_RG_BP_SMB (((REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) & 0x00010000 ) >> 16) #define GET_RO_TX_CNT_R_11B_TX (((REG32(ADR_WIFI_11B_TX_PKT_CNT_SENT_REG)) & 0xffffffff ) >> 0) #define GET_RG_DEBUG_SEL_11B_TX (((REG32(ADR_WIFI_11B_TX_DEBUG_SEL_REG)) & 0x0000000f ) >> 0) #define GET_RG_RESERVED_11B_TX (((REG32(ADR_WIFI_11B_TX_RESERVED_REG)) & 0xffffffff ) >> 0) #define GET_RG_POS_DES_L_EXT_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_000)) & 0x0000000f ) >> 0) #define GET_RG_PRE_DES_DLY_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_000)) & 0x000000f0 ) >> 4) #define GET_RG_CCA_RE_CHK_BIT_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_000)) & 0x00000f00 ) >> 8) #define GET_RG_CNT_CCA_RE_CHK_LMT (((REG32(ADR_WIFI_11B_RX_REG_001)) & 0x000f0000 ) >> 16) #define GET_RG_BYPASS_DESCRAMBLER (((REG32(ADR_WIFI_11B_RX_REG_001)) & 0x20000000 ) >> 29) #define GET_RG_CCA_BIT_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_002)) & 0x000000f0 ) >> 4) #define GET_RG_CCA_SCALE_BF (((REG32(ADR_WIFI_11B_RX_REG_002)) & 0x007f0000 ) >> 16) #define GET_RG_PEAK_IDX_CNT_SEL (((REG32(ADR_WIFI_11B_RX_REG_002)) & 0x30000000 ) >> 28) #define GET_RG_TR_KI_T2 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00000007 ) >> 0) #define GET_RG_TR_KP_T2 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00000070 ) >> 4) #define GET_RG_TR_KI_T1 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00000700 ) >> 8) #define GET_RG_TR_KP_T1 (((REG32(ADR_WIFI_11B_RX_REG_003)) & 0x00007000 ) >> 12) #define GET_RG_CR_KI_T1 (((REG32(ADR_WIFI_11B_RX_REG_004)) & 0x00070000 ) >> 16) #define GET_RG_CR_KP_T1 (((REG32(ADR_WIFI_11B_RX_REG_004)) & 0x00700000 ) >> 20) #define GET_RG_CHIP_CNT_SLICER (((REG32(ADR_WIFI_11B_RX_REG_005)) & 0x0000001f ) >> 0) #define GET_RG_CE_T2_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_005)) & 0xff000000 ) >> 24) #define GET_RG_CE_MU_T1 (((REG32(ADR_WIFI_11B_RX_REG_006)) & 0x00000007 ) >> 0) #define GET_RG_CE_DLY_SEL (((REG32(ADR_WIFI_11B_RX_REG_006)) & 0x003f0000 ) >> 16) #define GET_RG_CE_MU_T4 (((REG32(ADR_WIFI_11B_RX_REG_007)) & 0x00000007 ) >> 0) #define GET_RG_CE_MU_T3 (((REG32(ADR_WIFI_11B_RX_REG_007)) & 0x00070000 ) >> 16) #define GET_RG_CE_MU_T2 (((REG32(ADR_WIFI_11B_RX_REG_007)) & 0x07000000 ) >> 24) #define GET_RG_EQ_MU_FB_T2 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x0000000f ) >> 0) #define GET_RG_EQ_MU_FF_T2 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x000000f0 ) >> 4) #define GET_RG_EQ_MU_FB_T1 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x000f0000 ) >> 16) #define GET_RG_EQ_MU_FF_T1 (((REG32(ADR_WIFI_11B_RX_REG_008)) & 0x00f00000 ) >> 20) #define GET_RG_EQ_MU_FB_T4 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x0000000f ) >> 0) #define GET_RG_EQ_MU_FF_T4 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x000000f0 ) >> 4) #define GET_RG_EQ_MU_FB_T3 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x000f0000 ) >> 16) #define GET_RG_EQ_MU_FF_T3 (((REG32(ADR_WIFI_11B_RX_REG_009)) & 0x00f00000 ) >> 20) #define GET_RG_EQ_KI_T2 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00000700 ) >> 8) #define GET_RG_EQ_KP_T2 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00007000 ) >> 12) #define GET_RG_EQ_KI_T1 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00070000 ) >> 16) #define GET_RG_EQ_KP_T1 (((REG32(ADR_WIFI_11B_RX_REG_010)) & 0x00700000 ) >> 20) #define GET_RG_TR_LPF_RATE (((REG32(ADR_WIFI_11B_RX_REG_011)) & 0x003fffff ) >> 0) #define GET_RG_CE_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x0000007f ) >> 0) #define GET_RG_CE_CH_MAIN_SET (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x00000080 ) >> 7) #define GET_RG_TC_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x00007f00 ) >> 8) #define GET_RG_CR_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x007f0000 ) >> 16) #define GET_RG_TR_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_012)) & 0x7f000000 ) >> 24) #define GET_RG_EQ_MAIN_TAP_MAN (((REG32(ADR_WIFI_11B_RX_REG_013)) & 0x00000001 ) >> 0) #define GET_RG_EQ_MAIN_TAP_COEF (((REG32(ADR_WIFI_11B_RX_REG_013)) & 0x07ff0000 ) >> 16) #define GET_RG_CCK_TR_KI_T2 (((REG32(ADR_WIFI_11B_RX_REG_014)) & 0x00000007 ) >> 0) #define GET_RG_CCK_TR_KP_T2 (((REG32(ADR_WIFI_11B_RX_REG_014)) & 0x00000070 ) >> 4) #define GET_RG_PWRON_DLY_TH_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_039)) & 0x000000ff ) >> 0) #define GET_RG_SFD_BIT_CNT_LMT (((REG32(ADR_WIFI_11B_RX_REG_039)) & 0x00ff0000 ) >> 16) #define GET_RG_PWR_TH (((REG32(ADR_WIFI_11B_RX_REG_040)) & 0x0000ffff ) >> 0) #define GET_RG_PWR_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_040)) & 0x001f0000 ) >> 16) #define GET_RG_PWR_BIT_CNT_TH (((REG32(ADR_WIFI_11B_RX_REG_040)) & 0x0f000000 ) >> 24) #define GET_RG_PSDU_TIME_OFFSET_11B (((REG32(ADR_WIFI_11B_RX_REG_041)) & 0x0000ffff ) >> 0) #define GET_RG_RESERVED_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_240)) & 0xffffffff ) >> 0) #define GET_RG_INTRUP_RX_11B_CLEAR (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00000001 ) >> 0) #define GET_RG_INTRUP_RX_11B_MASK (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00000010 ) >> 4) #define GET_RG_INTRUP_RX_11B_TRIG (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00000f00 ) >> 8) #define GET_RO_INTRUP_RX_11B (((REG32(ADR_WIFI_11B_RX_REG_241)) & 0x00010000 ) >> 16) #define GET_RO_11B_FREQ_OS (((REG32(ADR_WIFI_11B_RX_REG_245)) & 0x000007ff ) >> 0) #define GET_RO_11B_SNR (((REG32(ADR_WIFI_11B_RX_REG_246)) & 0x0000007f ) >> 0) #define GET_RO_11B_RCPI (((REG32(ADR_WIFI_11B_RX_REG_246)) & 0x007f0000 ) >> 16) #define GET_RO_11B_CRC_CNT (((REG32(ADR_WIFI_11B_RX_REG_249)) & 0x0000ffff ) >> 0) #define GET_RO_11B_SFD_CNT (((REG32(ADR_WIFI_11B_RX_REG_249)) & 0xffff0000 ) >> 16) #define GET_RO_11B_PACKET_ERR_CNT (((REG32(ADR_WIFI_11B_RX_REG_250)) & 0x0000ffff ) >> 0) #define GET_RO_11B_PACKET_ERR (((REG32(ADR_WIFI_11B_RX_REG_250)) & 0x00010000 ) >> 16) #define GET_RO_11B_PACKET_CNT (((REG32(ADR_WIFI_11B_RX_REG_251)) & 0x0000ffff ) >> 0) #define GET_RO_11B_CCA_CNT (((REG32(ADR_WIFI_11B_RX_REG_251)) & 0xffff0000 ) >> 16) #define GET_RO_11B_LENGTH_FIELD (((REG32(ADR_WIFI_11B_RX_REG_252)) & 0x0000ffff ) >> 0) #define GET_RO_11B_SFD_FIELD (((REG32(ADR_WIFI_11B_RX_REG_252)) & 0xffff0000 ) >> 16) #define GET_RO_11B_SIGNAL_FIELD (((REG32(ADR_WIFI_11B_RX_REG_253)) & 0x000000ff ) >> 0) #define GET_RO_11B_SERVICE_FIELD (((REG32(ADR_WIFI_11B_RX_REG_253)) & 0x0000ff00 ) >> 8) #define GET_RO_11B_CRC_CORRECT (((REG32(ADR_WIFI_11B_RX_REG_253)) & 0x00010000 ) >> 16) #define GET_RG_RATE_STAT (((REG32(ADR_WIFI_11B_RX_REG_254)) & 0x00070000 ) >> 16) #define GET_RG_PACKET_STAT_EN_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_254)) & 0x00100000 ) >> 20) #define GET_RG_BIT_REVERSE (((REG32(ADR_WIFI_11B_RX_REG_254)) & 0x00200000 ) >> 21) #define GET_RG_SOFT_RST_N_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x00000001 ) >> 0) #define GET_RG_CE_BYPASS_TAP (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x000000f0 ) >> 4) #define GET_RG_EQ_BYPASS_FBW_TAP (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x00000f00 ) >> 8) #define GET_RG_DEBUG_SEL_11B_RX (((REG32(ADR_WIFI_11B_RX_REG_255)) & 0x000f0000 ) >> 16) #define GET_RG_BIST_EN_TX_FFT (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00000001 ) >> 0) #define GET_RG_BIST_MODE_TX_FFT (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00000010 ) >> 4) #define GET_RO_BIST_DONE_TX_FFT_1 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00010000 ) >> 16) #define GET_RO_BIST_FAIL_TX_FFT_1 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00020000 ) >> 17) #define GET_RO_BIST_DONE_TX_FFT_0 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00100000 ) >> 20) #define GET_RO_BIST_FAIL_TX_FFT_0 (((REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) & 0x00200000 ) >> 21) #define GET_RG_BB_RISE_TIME_11GN_TX (((REG32(ADR_WIFI_11GN_TX_BB_RAMP_REG)) & 0x000000ff ) >> 0) #define GET_RG_BB_FALL_TIME_11GN_TX (((REG32(ADR_WIFI_11GN_TX_BB_RAMP_REG)) & 0x0000ff00 ) >> 8) #define GET_RG_TX_CLK_OUTER_EN (((REG32(ADR_WIFI_11GN_TX_CONTROL_REG)) & 0x00000001 ) >> 0) #define GET_RG_SHORT_GI_EN (((REG32(ADR_WIFI_11GN_TX_CONTROL_REG)) & 0x00000010 ) >> 4) #define GET_RG_STF_SCALE_20 (((REG32(ADR_WIFI_11GN_TX_STS_SCALE_REG)) & 0x000003ff ) >> 0) #define GET_RG_STF_SCALE_40 (((REG32(ADR_WIFI_11GN_TX_STS_SCALE_REG)) & 0x03ff0000 ) >> 16) #define GET_RG_FFT_SCALE_104 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG0)) & 0x000003ff ) >> 0) #define GET_RG_FFT_SCALE_114 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG0)) & 0x03ff0000 ) >> 16) #define GET_RG_FFT_SCALE_52 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x000003ff ) >> 0) #define GET_RG_FFT_SCALE_56 (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x003ff000 ) >> 12) #define GET_RG_SCR_INIT_SEED (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x7f000000 ) >> 24) #define GET_RG_SCR_SEED_MANUANL (((REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) & 0x80000000 ) >> 31) #define GET_RO_TX_CNT_R_11GN_TX (((REG32(ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG)) & 0xffffffff ) >> 0) #define GET_RG_DEBUG_SEL_11GN_TX (((REG32(ADR_WIFI_11GN_TX_DEBUG_SEL_REG)) & 0x00000f00 ) >> 8) #define GET_RG_RESERVED_11GN_TX (((REG32(ADR_WIFI_11GN_TX_RESERVED_REG)) & 0xffffffff ) >> 0) #define GET_RG_POS_DES_L_EXT_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_000)) & 0x0000000f ) >> 0) #define GET_RG_PRE_DES_DLY_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_000)) & 0x000000f0 ) >> 4) #define GET_RG_RESERVED_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_001)) & 0xffffffff ) >> 0) #define GET_RG_HT40_TR_LPF_KI (((REG32(ADR_WIFI_11GN_RX_REG_002)) & 0x0000000f ) >> 0) #define GET_RG_HT40_TR_LPF_KP (((REG32(ADR_WIFI_11GN_RX_REG_002)) & 0x000000f0 ) >> 4) #define GET_RG_HT40_SYM_BOUND_CNT (((REG32(ADR_WIFI_11GN_RX_REG_002)) & 0x00007f00 ) >> 8) #define GET_RG_HT20_TR_LPF_KI (((REG32(ADR_WIFI_11GN_RX_REG_003)) & 0x0000000f ) >> 0) #define GET_RG_HT20_TR_LPF_KP (((REG32(ADR_WIFI_11GN_RX_REG_003)) & 0x000000f0 ) >> 4) #define GET_RG_TR_LPF_RATE_GN (((REG32(ADR_WIFI_11GN_RX_REG_003)) & 0x3fffff00 ) >> 8) #define GET_RG_CR_LPF_KI_GN (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x00000007 ) >> 0) #define GET_RG_HT20_SYM_BOUND_CNT (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x00007f00 ) >> 8) #define GET_RG_XSCOR32_RATIO (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x007f0000 ) >> 16) #define GET_RG_ATCOR64_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_004_)) & 0x7f000000 ) >> 24) #define GET_RG_ATCOR16_CNT_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_005)) & 0x00007f00 ) >> 8) #define GET_RG_ATCOR16_CNT_LMT1 (((REG32(ADR_WIFI_11GN_RX_REG_005)) & 0x007f0000 ) >> 16) #define GET_RG_ATCOR16_RATIO_SB (((REG32(ADR_WIFI_11GN_RX_REG_005)) & 0x7f000000 ) >> 24) #define GET_RG_XSCOR64_CNT_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_006_)) & 0x007f0000 ) >> 16) #define GET_RG_XSCOR64_CNT_LMT1 (((REG32(ADR_WIFI_11GN_RX_REG_006_)) & 0x7f000000 ) >> 24) #define GET_RG_HT20_RX_FFT_SCALE (((REG32(ADR_WIFI_11GN_RX_REG_007_)) & 0x000003ff ) >> 0) #define GET_RG_VITERBI_AB_SWAP (((REG32(ADR_WIFI_11GN_RX_REG_007_)) & 0x00010000 ) >> 16) #define GET_RG_ATCOR16_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_007_)) & 0x0f000000 ) >> 24) #define GET_RG_NORMSQUARE_LOW_SNR_7 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0x000000ff ) >> 0) #define GET_RG_NORMSQUARE_LOW_SNR_6 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0x0000ff00 ) >> 8) #define GET_RG_NORMSQUARE_LOW_SNR_5 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0x00ff0000 ) >> 16) #define GET_RG_NORMSQUARE_LOW_SNR_4 (((REG32(ADR_WIFI_11GN_RX_REG_008)) & 0xff000000 ) >> 24) #define GET_RG_NORMSQUARE_LOW_SNR_8 (((REG32(ADR_WIFI_11GN_RX_REG_009)) & 0xff000000 ) >> 24) #define GET_RG_NORMSQUARE_SNR_3 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0x000000ff ) >> 0) #define GET_RG_NORMSQUARE_SNR_2 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0x0000ff00 ) >> 8) #define GET_RG_NORMSQUARE_SNR_1 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0x00ff0000 ) >> 16) #define GET_RG_NORMSQUARE_SNR_0 (((REG32(ADR_WIFI_11GN_RX_REG_010_)) & 0xff000000 ) >> 24) #define GET_RG_NORMSQUARE_SNR_7 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0x000000ff ) >> 0) #define GET_RG_NORMSQUARE_SNR_6 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0x0000ff00 ) >> 8) #define GET_RG_NORMSQUARE_SNR_5 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0x00ff0000 ) >> 16) #define GET_RG_NORMSQUARE_SNR_4 (((REG32(ADR_WIFI_11GN_RX_REG_011)) & 0xff000000 ) >> 24) #define GET_RG_NORMSQUARE_SNR_8 (((REG32(ADR_WIFI_11GN_RX_REG_012)) & 0xff000000 ) >> 24) #define GET_RG_SNR_TH_64QAM (((REG32(ADR_WIFI_11GN_RX_REG_013)) & 0x0000007f ) >> 0) #define GET_RG_SNR_TH_16QAM (((REG32(ADR_WIFI_11GN_RX_REG_013)) & 0x00007f00 ) >> 8) #define GET_RG_ATCOR16_CNT_PLUS_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_014)) & 0x0000007f ) >> 0) #define GET_RG_ATCOR16_CNT_PLUS_LMT1 (((REG32(ADR_WIFI_11GN_RX_REG_014)) & 0x00007f00 ) >> 8) #define GET_RG_SYM_BOUND_METHOD (((REG32(ADR_WIFI_11GN_RX_REG_014)) & 0x00030000 ) >> 16) #define GET_RG_HT40_RX_FFT_SCALE (((REG32(ADR_WIFI_11GN_RX_REG_015)) & 0x000003ff ) >> 0) #define GET_RG_ERASE_SC_NUM3 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x0000007f ) >> 0) #define GET_RG_SC_CTRL3 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00000080 ) >> 7) #define GET_RG_ERASE_SC_NUM2 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00007f00 ) >> 8) #define GET_RG_SC_CTRL2 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00008000 ) >> 15) #define GET_RG_ERASE_SC_NUM1 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x007f0000 ) >> 16) #define GET_RG_SC_CTRL1 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x00800000 ) >> 23) #define GET_RG_ERASE_SC_NUM0 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x7f000000 ) >> 24) #define GET_RG_SC_CTRL0 (((REG32(ADR_WIFI_11GN_RX_REG_016)) & 0x80000000 ) >> 31) #define GET_RG_ERASE_SC_NUM7 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x0000007f ) >> 0) #define GET_RG_SC_CTRL7 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00000080 ) >> 7) #define GET_RG_ERASE_SC_NUM6 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00007f00 ) >> 8) #define GET_RG_SC_CTRL6 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00008000 ) >> 15) #define GET_RG_ERASE_SC_NUM5 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x007f0000 ) >> 16) #define GET_RG_SC_CTRL5 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x00800000 ) >> 23) #define GET_RG_ERASE_SC_NUM4 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x7f000000 ) >> 24) #define GET_RG_SC_CTRL4 (((REG32(ADR_WIFI_11GN_RX_REG_017)) & 0x80000000 ) >> 31) #define GET_RG_BIST_EN_CCFO (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00000001 ) >> 0) #define GET_RG_BIST_MODE_CCFO (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00000010 ) >> 4) #define GET_RO_BIST_DONE_CCFO_1 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00010000 ) >> 16) #define GET_RO_BIST_FAIL_CCFO_1 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00020000 ) >> 17) #define GET_RO_BIST_DONE_CCFO_0 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00100000 ) >> 20) #define GET_RO_BIST_FAIL_CCFO_0 (((REG32(ADR_WIFI_11GN_RX_REG_032)) & 0x00200000 ) >> 21) #define GET_RG_BIST_EN_VTB (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00000001 ) >> 0) #define GET_RG_BIST_MODE_VTB (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00000010 ) >> 4) #define GET_RO_BIST_DONE_VTB_3 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00010000 ) >> 16) #define GET_RO_BIST_FAIL_VTB_3 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00020000 ) >> 17) #define GET_RO_BIST_DONE_VTB_2 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00100000 ) >> 20) #define GET_RO_BIST_FAIL_VTB_2 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x00200000 ) >> 21) #define GET_RO_BIST_DONE_VTB_1 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x01000000 ) >> 24) #define GET_RO_BIST_FAIL_VTB_1 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x02000000 ) >> 25) #define GET_RO_BIST_DONE_VTB_0 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x10000000 ) >> 28) #define GET_RO_BIST_FAIL_VTB_0 (((REG32(ADR_WIFI_11GN_RX_REG_033)) & 0x20000000 ) >> 29) #define GET_RG_PWRON_DLY_TH_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_039)) & 0x000000ff ) >> 0) #define GET_RG_SB_START_CNT (((REG32(ADR_WIFI_11GN_RX_REG_039)) & 0x00007f00 ) >> 8) #define GET_RG_CCA_POW_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_040)) & 0x000000f0 ) >> 4) #define GET_RG_CCA_POW_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_040)) & 0x00000700 ) >> 8) #define GET_RG_CCA_POW_TH (((REG32(ADR_WIFI_11GN_RX_REG_040)) & 0xffff0000 ) >> 16) #define GET_RG_POW16_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_048)) & 0x000000f0 ) >> 4) #define GET_RG_POW16_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_048)) & 0x00000700 ) >> 8) #define GET_RG_POW16_TH_L (((REG32(ADR_WIFI_11GN_RX_REG_048)) & 0xff000000 ) >> 24) #define GET_RG_XSCOR16_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x00000007 ) >> 0) #define GET_RG_XSCOR16_RATIO (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x00007f00 ) >> 8) #define GET_RG_ATCOR16_SHORT_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x00070000 ) >> 16) #define GET_RG_ATCOR16_RATIO_CCD (((REG32(ADR_WIFI_11GN_RX_REG_049)) & 0x7f000000 ) >> 24) #define GET_RG_ATCOR64_ACC_LMT (((REG32(ADR_WIFI_11GN_RX_REG_050)) & 0x0000007f ) >> 0) #define GET_RG_ATCOR16_SHORT_CNT_LMT2 (((REG32(ADR_WIFI_11GN_RX_REG_050)) & 0x00070000 ) >> 16) #define GET_RG_CCFO_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x0000007f ) >> 0) #define GET_RG_BYPASS_COARSE_FREQ (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x00000100 ) >> 8) #define GET_RG_CCFO_GAIN_BY2 (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x00000200 ) >> 9) #define GET_RG_XSCOR64_RATIO_SB (((REG32(ADR_WIFI_11GN_RX_REG_051)) & 0x007f0000 ) >> 16) #define GET_RG_5G_CCFO_CNT_LMT (((REG32(ADR_WIFI_11GN_RX_REG_052)) & 0x0000007f ) >> 0) #define GET_RG_5G_BYPASS_COARSE_FREQ (((REG32(ADR_WIFI_11GN_RX_REG_052)) & 0x00000100 ) >> 8) #define GET_RG_5G_CCFO_GAIN_BY2 (((REG32(ADR_WIFI_11GN_RX_REG_052)) & 0x00000200 ) >> 9) #define GET_RG_ACS_INI_PM_ALL0 (((REG32(ADR_WIFI_11GN_RX_REG_076)) & 0x00000001 ) >> 0) #define GET_RG_VITERBI_TB_BITS (((REG32(ADR_WIFI_11GN_RX_REG_076)) & 0xff000000 ) >> 24) #define GET_RG_CR_CNT_UPDATE_SGI (((REG32(ADR_WIFI_11GN_RX_REG_087)) & 0x000001ff ) >> 0) #define GET_RG_TR_CNT_UPDATE_SGI (((REG32(ADR_WIFI_11GN_RX_REG_087)) & 0x01ff0000 ) >> 16) #define GET_RG_CR_CNT_UPDATE (((REG32(ADR_WIFI_11GN_RX_REG_088)) & 0x000001ff ) >> 0) #define GET_RG_TR_CNT_UPDATE (((REG32(ADR_WIFI_11GN_RX_REG_088)) & 0x01ff0000 ) >> 16) #define GET_RG_CPE_SEL_64QAM (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00010000 ) >> 16) #define GET_RG_CPE_SEL_16QAM (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00020000 ) >> 17) #define GET_RG_CPE_SEL_QPSK (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00040000 ) >> 18) #define GET_RG_CPE_SEL_BPSK (((REG32(ADR_WIFI_11GN_RX_REG_089)) & 0x00080000 ) >> 19) #define GET_RG_BYPASS_CPE_MA (((REG32(ADR_WIFI_11GN_RX_REG_096)) & 0x00000010 ) >> 4) #define GET_RG_CHSMTH_COEF (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x00030000 ) >> 16) #define GET_RG_CHSMTH_EN (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x00040000 ) >> 18) #define GET_RG_CHEST_DD_FACTOR (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x07000000 ) >> 24) #define GET_RG_CH_UPDATE (((REG32(ADR_WIFI_11GN_RX_REG_098)) & 0x80000000 ) >> 31) #define GET_RG_FMT_DET_MM_TH (((REG32(ADR_WIFI_11GN_RX_REG_100)) & 0x000000ff ) >> 0) #define GET_RG_FMT_DET_GF_TH (((REG32(ADR_WIFI_11GN_RX_REG_100)) & 0x0000ff00 ) >> 8) #define GET_RG_DO_NOT_CHECK_L_RATE (((REG32(ADR_WIFI_11GN_RX_REG_100)) & 0x02000000 ) >> 25) #define GET_RG_NEW_PILOT_AVG (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x00000001 ) >> 0) #define GET_RG_NEW_SB (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x00000010 ) >> 4) #define GET_RG_ATCOR64_FREQ_START (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x00007f00 ) >> 8) #define GET_RG_L_LENGTH_MAX (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x0fff0000 ) >> 16) #define GET_RG_ATCOR16_CCA_GAIN (((REG32(ADR_WIFI_11GN_RX_REG_101)) & 0x30000000 ) >> 28) #define GET_RG_PSDU_TIME_OFFSET_GF (((REG32(ADR_WIFI_11GN_RX_REG_102)) & 0x0000ffff ) >> 0) #define GET_RG_PSDU_TIME_OFFSET_MF (((REG32(ADR_WIFI_11GN_RX_REG_102)) & 0xffff0000 ) >> 16) #define GET_RG_PSDU_TIME_OFFSET_LEGACY (((REG32(ADR_WIFI_11GN_RX_REG_103)) & 0x0000ffff ) >> 0) #define GET_RG_INTRUP_RX_11GN_CLEAR (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00000001 ) >> 0) #define GET_RG_INTRUP_RX_11GN_MASK (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00000010 ) >> 4) #define GET_RG_INTRUP_RX_11GN_TRIG (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00000f00 ) >> 8) #define GET_RO_INTRUP_RX_11GN (((REG32(ADR_WIFI_11GN_RX_REG_241)) & 0x00010000 ) >> 16) #define GET_RO_STBC_PACKET_CNT (((REG32(ADR_WIFI_11GN_RX_REG_245)) & 0x0000ffff ) >> 0) #define GET_RO_STBC_PACKET_ERR_CNT (((REG32(ADR_WIFI_11GN_RX_REG_245)) & 0xffff0000 ) >> 16) #define GET_RO_11GN_SNR (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x0000007f ) >> 0) #define GET_RO_11GN_NOISE_PWR (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x00007f00 ) >> 8) #define GET_RO_11GN_RCPI (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x007f0000 ) >> 16) #define GET_RO_11GN_SIGNAL_PWR (((REG32(ADR_WIFI_11GN_RX_REG_246)) & 0x7f000000 ) >> 24) #define GET_RO_11GN_FREQ_OS_LTS (((REG32(ADR_WIFI_11GN_RX_REG_247)) & 0x00007fff ) >> 0) #define GET_RO_11GN_HT_SIGNAL_FIELD_47_24 (((REG32(ADR_WIFI_11GN_RX_REG_248)) & 0x00ffffff ) >> 0) #define GET_RO_11GN_HT_SIGNAL_FIELD_23_0 (((REG32(ADR_WIFI_11GN_RX_REG_249)) & 0x00ffffff ) >> 0) #define GET_RO_11GN_PACKET_ERR_CNT (((REG32(ADR_WIFI_11GN_RX_REG_250)) & 0x0000ffff ) >> 0) #define GET_RO_11GN_SERVICE_FIELD (((REG32(ADR_WIFI_11GN_RX_REG_250)) & 0xffff0000 ) >> 16) #define GET_RO_11GN_PACKET_CNT (((REG32(ADR_WIFI_11GN_RX_REG_251)) & 0x0000ffff ) >> 0) #define GET_RO_11GN_CCA_CNT (((REG32(ADR_WIFI_11GN_RX_REG_251)) & 0xffff0000 ) >> 16) #define GET_RO_11GN_L_SIGNAL_FIELD (((REG32(ADR_WIFI_11GN_RX_REG_252)) & 0x00ffffff ) >> 0) #define GET_RO_AMPDU_PACKET_CNT (((REG32(ADR_WIFI_11GN_RX_REG_253)) & 0x0000ffff ) >> 0) #define GET_RO_AMPDU_PACKET_ERR_CNT (((REG32(ADR_WIFI_11GN_RX_REG_253)) & 0xffff0000 ) >> 16) #define GET_RG_DAGC_CNT_TH (((REG32(ADR_WIFI_11GN_RX_REG_254)) & 0x00000003 ) >> 0) #define GET_RG_RATE_MCS_STAT (((REG32(ADR_WIFI_11GN_RX_REG_254)) & 0x000f0000 ) >> 16) #define GET_RG_PACKET_STAT_EN_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_254)) & 0x00100000 ) >> 20) #define GET_RG_SOFT_RST_N_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000001 ) >> 0) #define GET_RG_RIFS_EN (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000002 ) >> 1) #define GET_RG_STBC_EN (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000004 ) >> 2) #define GET_RG_COR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000008 ) >> 3) #define GET_RG_INI_PHASE (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000030 ) >> 4) #define GET_RG_CCA_PWR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000200 ) >> 9) #define GET_RG_CCA_XSCOR_PWR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000400 ) >> 10) #define GET_RG_CCA_XSCOR_AVGPWR_SEL (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00000800 ) >> 11) #define GET_RG_DEBUG_SEL_11GN_RX (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x0000f000 ) >> 12) #define GET_RG_POST_CLK_EN (((REG32(ADR_WIFI_11GN_RX_REG_255)) & 0x00010000 ) >> 16) #define GET_RG_THL_ED (((REG32(ADR_WIFI_RADAR_REG_00)) & 0x0000003f ) >> 0) #define GET_RG_THH_ED (((REG32(ADR_WIFI_RADAR_REG_00)) & 0x00003f00 ) >> 8) #define GET_RG_THL_RATIO (((REG32(ADR_WIFI_RADAR_REG_00)) & 0x00ff0000 ) >> 16) #define GET_RG_THH_RATIO (((REG32(ADR_WIFI_RADAR_REG_00)) & 0xff000000 ) >> 24) #define GET_RG_PW_MIN (((REG32(ADR_WIFI_RADAR_REG_01)) & 0x00000fff ) >> 0) #define GET_RG_PW_MAX (((REG32(ADR_WIFI_RADAR_REG_01)) & 0x0fff0000 ) >> 16) #define GET_RG_PERIOD_MIN (((REG32(ADR_WIFI_RADAR_REG_02)) & 0x00000fff ) >> 0) #define GET_RG_PERIOD_MAX (((REG32(ADR_WIFI_RADAR_REG_02)) & 0x0fff0000 ) >> 16) #define GET_RG_TIME_PERIOD (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x00000fff ) >> 0) #define GET_RG_PULSE_NUMBER (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x00700000 ) >> 20) #define GET_RG_ALPHA_FINE (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x07000000 ) >> 24) #define GET_RG_ALPHA_COARSE (((REG32(ADR_WIFI_RADAR_REG_03)) & 0x30000000 ) >> 28) #define GET_RG_RADAR_EN (((REG32(ADR_WIFI_RADAR_REG_04)) & 0x00000001 ) >> 0) #define GET_RG_TOLERANCE_PERIOD (((REG32(ADR_WIFI_RADAR_REG_04)) & 0x003f0000 ) >> 16) #define GET_RG_TOLERANCE_PW (((REG32(ADR_WIFI_RADAR_REG_04)) & 0x3f000000 ) >> 24) #define GET_RO_RADAR_DET_NUM (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x00000007 ) >> 0) #define GET_RO_RADAR_DET_OUT (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x00000010 ) >> 4) #define GET_RO_RADAR_VALID (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x00000100 ) >> 8) #define GET_RO_PW (((REG32(ADR_WIFI_RADAR_REG_RO)) & 0x0fff0000 ) >> 16) #define GET_RO_PW_ARRAY_0 (((REG32(ADR_WIFI_RADAR_REG_DB_A0_RO)) & 0x00000fff ) >> 0) #define GET_RO_PW_ARRAY_1 (((REG32(ADR_WIFI_RADAR_REG_DB_A0_RO)) & 0x0fff0000 ) >> 16) #define GET_RO_PW_ARRAY_2 (((REG32(ADR_WIFI_RADAR_REG_DB_A1_RO)) & 0x00000fff ) >> 0) #define GET_RO_PW_ARRAY_3 (((REG32(ADR_WIFI_RADAR_REG_DB_A1_RO)) & 0x0fff0000 ) >> 16) #define GET_RO_PW_ARRAY_4 (((REG32(ADR_WIFI_RADAR_REG_DB_A2_RO)) & 0x00000fff ) >> 0) #define GET_RO_PW_ARRAY_5 (((REG32(ADR_WIFI_RADAR_REG_DB_A2_RO)) & 0x0fff0000 ) >> 16) #define GET_RO_PERIOD_ARRAY_0 (((REG32(ADR_WIFI_RADAR_REG_DB_P0_RO)) & 0x00000fff ) >> 0) #define GET_RO_PERIOD_ARRAY_1 (((REG32(ADR_WIFI_RADAR_REG_DB_P0_RO)) & 0x0fff0000 ) >> 16) #define GET_RO_PERIOD_ARRAY_2 (((REG32(ADR_WIFI_RADAR_REG_DB_P1_RO)) & 0x00000fff ) >> 0) #define GET_RO_PERIOD_ARRAY_3 (((REG32(ADR_WIFI_RADAR_REG_DB_P1_RO)) & 0x0fff0000 ) >> 16) #define GET_RO_PERIOD_ARRAY_4 (((REG32(ADR_WIFI_RADAR_REG_DB_P2_RO)) & 0x00000fff ) >> 0) #define GET_RO_PERIOD_ARRAY_5 (((REG32(ADR_WIFI_RADAR_REG_DB_P2_RO)) & 0x0fff0000 ) >> 16) #define GET_RG_PW_CHIRP_MIN (((REG32(ADR_WIFI_RADAR_CHIRP_REG)) & 0x00000fff ) >> 0) #define GET_RG_PW_CHIRP_MAX (((REG32(ADR_WIFI_RADAR_CHIRP_REG)) & 0x0fff0000 ) >> 16) #define GET_CPU_QUE_POP_ALT (((REG32(ADR_MB_CPU_INT_ALT)) & 0x00000001 ) >> 0) #define GET_CPU_INT_ALT (((REG32(ADR_MB_CPU_INT_ALT)) & 0x00000004 ) >> 2) #define GET_CPU_QUE_POP (((REG32(ADR_MB_CPU_INT)) & 0x00000001 ) >> 0) #define GET_CPU_INT (((REG32(ADR_MB_CPU_INT)) & 0x00000004 ) >> 2) #define GET_CPU_ID_TB0 (((REG32(ADR_CPU_ID_TB0)) & 0xffffffff ) >> 0) #define GET_CPU_ID_TB1 (((REG32(ADR_CPU_ID_TB1)) & 0xffffffff ) >> 0) #define GET_PKTID (((REG32(ADR_CH0_TRIG_1)) & 0x0000007f ) >> 0) #define GET_HWID (((REG32(ADR_CH0_TRIG_1)) & 0x00000780 ) >> 7) #define GET_CH0_INT_ADDR (((REG32(ADR_CH0_TRIG_0)) & 0xffffffff ) >> 0) #define GET_PRIPKTID (((REG32(ADR_CH0_PRI_TRIG)) & 0x0000007f ) >> 0) #define GET_PRIHWID (((REG32(ADR_CH0_PRI_TRIG)) & 0x00000780 ) >> 7) #define GET_CH0_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000001 ) >> 0) #define GET_FF0_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000002 ) >> 1) #define GET_CH2_FULL (((REG32(ADR_MCU_STATUS)) & 0x00000010 ) >> 4) #define GET_FF2_EMPTY (((REG32(ADR_MCU_STATUS)) & 0x00000020 ) >> 5) #define GET_RLS_BUSY (((REG32(ADR_MCU_STATUS)) & 0x00000200 ) >> 9) #define GET_RLS_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000400 ) >> 10) #define GET_RTN_COUNT_CLR (((REG32(ADR_MCU_STATUS)) & 0x00000800 ) >> 11) #define GET_RLS_COUNT (((REG32(ADR_MCU_STATUS)) & 0x00ff0000 ) >> 16) #define GET_RTN_COUNT (((REG32(ADR_MCU_STATUS)) & 0xff000000 ) >> 24) #define GET_FF0_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x0000001f ) >> 0) #define GET_FF1_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000001e0 ) >> 5) #define GET_FF3_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00003800 ) >> 11) #define GET_FF5_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x000e0000 ) >> 17) #define GET_FF6_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x00700000 ) >> 20) #define GET_FF7_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x03800000 ) >> 23) #define GET_FF8_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0x1c000000 ) >> 26) #define GET_FF9_CNT (((REG32(ADR_RD_IN_FFCNT1)) & 0xe0000000 ) >> 29) #define GET_FF10_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000007 ) >> 0) #define GET_FF11_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000038 ) >> 3) #define GET_FF12_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x000001c0 ) >> 6) #define GET_FF13_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00000e00 ) >> 9) #define GET_FF14_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00007000 ) >> 12) #define GET_FF15_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x00038000 ) >> 15) #define GET_FF4_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x007c0000 ) >> 18) #define GET_FF2_CNT (((REG32(ADR_RD_IN_FFCNT2)) & 0x03800000 ) >> 23) #define GET_CH0_FULL_ALT (((REG32(ADR_RD_FFIN_FULL)) & 0x00000001 ) >> 0) #define GET_CH1_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000002 ) >> 1) #define GET_CH2_FULL_ALT (((REG32(ADR_RD_FFIN_FULL)) & 0x00000004 ) >> 2) #define GET_CH3_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000008 ) >> 3) #define GET_CH4_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000010 ) >> 4) #define GET_CH5_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000020 ) >> 5) #define GET_CH6_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000040 ) >> 6) #define GET_CH7_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000080 ) >> 7) #define GET_CH8_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000100 ) >> 8) #define GET_CH9_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000200 ) >> 9) #define GET_CH10_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000400 ) >> 10) #define GET_CH11_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00000800 ) >> 11) #define GET_CH12_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00001000 ) >> 12) #define GET_CH13_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00002000 ) >> 13) #define GET_CH14_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00004000 ) >> 14) #define GET_CH15_FULL (((REG32(ADR_RD_FFIN_FULL)) & 0x00008000 ) >> 15) #define GET_PKTID_ALT (((REG32(ADR_CH2_TRIG_ALT)) & 0x0000007f ) >> 0) #define GET_HWID_ALT (((REG32(ADR_CH2_TRIG_ALT)) & 0x00000780 ) >> 7) #define GET_CH2_INT_ADDR_ALT (((REG32(ADR_CH2_INT_ADDR_ALT)) & 0xffffffff ) >> 0) #define GET_HALT_CH1 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000002 ) >> 1) #define GET_HALT_CH3 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000008 ) >> 3) #define GET_HALT_CH4 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000010 ) >> 4) #define GET_HALT_CH5 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000020 ) >> 5) #define GET_HALT_CH6 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000040 ) >> 6) #define GET_HALT_CH7 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000080 ) >> 7) #define GET_HALT_CH8 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000100 ) >> 8) #define GET_HALT_CH9 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000200 ) >> 9) #define GET_HALT_CH10 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000400 ) >> 10) #define GET_HALT_CH11 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00000800 ) >> 11) #define GET_HALT_CH12 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00001000 ) >> 12) #define GET_HALT_CH13 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00002000 ) >> 13) #define GET_HALT_CH14 (((REG32(ADR_MBOX_HALT_CFG)) & 0x00004000 ) >> 14) #define GET_STOP_MBOX_OUT (((REG32(ADR_MBOX_HALT_CFG)) & 0x00010000 ) >> 16) #define GET_STOP_MBOX_IN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00020000 ) >> 17) #define GET_MB_ERR_AUTO_HALT_EN (((REG32(ADR_MBOX_HALT_CFG)) & 0x00100000 ) >> 20) #define GET_MB_EXCEPT_CLR (((REG32(ADR_MBOX_HALT_CFG)) & 0x00200000 ) >> 21) #define GET_CH1_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000002 ) >> 1) #define GET_CH3_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000008 ) >> 3) #define GET_CH4_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000010 ) >> 4) #define GET_CH5_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000020 ) >> 5) #define GET_CH6_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000040 ) >> 6) #define GET_CH7_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000080 ) >> 7) #define GET_CH8_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000100 ) >> 8) #define GET_CH9_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000200 ) >> 9) #define GET_CH10_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000400 ) >> 10) #define GET_CH11_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00000800 ) >> 11) #define GET_CH12_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00001000 ) >> 12) #define GET_CH13_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00002000 ) >> 13) #define GET_CH14_HALT_STS (((REG32(ADR_MBOX_HALT_STS)) & 0x00004000 ) >> 14) #define GET_STOP_MBOX_OUT_SUCCESS (((REG32(ADR_MBOX_HALT_STS)) & 0x00010000 ) >> 16) #define GET_MB_EXCEPT_CASE (((REG32(ADR_MBOX_HALT_STS)) & 0xff000000 ) >> 24) #define GET_MB_DBG_TIME_STEP (((REG32(ADR_MB_DBG_CFG1)) & 0x0000ffff ) >> 0) #define GET_DBG_TYPE (((REG32(ADR_MB_DBG_CFG1)) & 0x00030000 ) >> 16) #define GET_MB_DBG_CLR (((REG32(ADR_MB_DBG_CFG1)) & 0x00040000 ) >> 18) #define GET_DBG_ALC_LOG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x00080000 ) >> 19) #define GET_MB_DBG_COUNTER_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x01000000 ) >> 24) #define GET_MB_DBG_EN (((REG32(ADR_MB_DBG_CFG1)) & 0x80000000 ) >> 31) #define GET_MB_DBG_RECORD_CNT (((REG32(ADR_MB_DBG_CFG2)) & 0x0000ffff ) >> 0) #define GET_MB_DBG_LENGTH (((REG32(ADR_MB_DBG_CFG2)) & 0xffff0000 ) >> 16) #define GET_MB_DBG_CFG_ADDR (((REG32(ADR_MB_DBG_CFG3)) & 0xffffffff ) >> 0) #define GET_DBG_HWID0_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000001 ) >> 0) #define GET_DBG_HWID1_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000002 ) >> 1) #define GET_DBG_HWID2_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000004 ) >> 2) #define GET_DBG_HWID3_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000008 ) >> 3) #define GET_DBG_HWID4_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000010 ) >> 4) #define GET_DBG_HWID5_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000020 ) >> 5) #define GET_DBG_HWID6_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000040 ) >> 6) #define GET_DBG_HWID7_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000080 ) >> 7) #define GET_DBG_HWID8_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000100 ) >> 8) #define GET_DBG_HWID9_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000200 ) >> 9) #define GET_DBG_HWID10_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000400 ) >> 10) #define GET_DBG_HWID11_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00000800 ) >> 11) #define GET_DBG_HWID12_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00001000 ) >> 12) #define GET_DBG_HWID13_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00002000 ) >> 13) #define GET_DBG_HWID14_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00004000 ) >> 14) #define GET_DBG_HWID15_WR_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00008000 ) >> 15) #define GET_DBG_HWID0_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00010000 ) >> 16) #define GET_DBG_HWID1_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00020000 ) >> 17) #define GET_DBG_HWID2_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00040000 ) >> 18) #define GET_DBG_HWID3_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00080000 ) >> 19) #define GET_DBG_HWID4_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00100000 ) >> 20) #define GET_DBG_HWID5_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00200000 ) >> 21) #define GET_DBG_HWID6_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00400000 ) >> 22) #define GET_DBG_HWID7_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x00800000 ) >> 23) #define GET_DBG_HWID8_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x01000000 ) >> 24) #define GET_DBG_HWID9_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x02000000 ) >> 25) #define GET_DBG_HWID10_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x04000000 ) >> 26) #define GET_DBG_HWID11_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x08000000 ) >> 27) #define GET_DBG_HWID12_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x10000000 ) >> 28) #define GET_DBG_HWID13_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x20000000 ) >> 29) #define GET_DBG_HWID14_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x40000000 ) >> 30) #define GET_DBG_HWID15_RD_EN (((REG32(ADR_MB_DBG_CFG4)) & 0x80000000 ) >> 31) #define GET_MB_OUT_QUEUE_EN (((REG32(ADR_MB_OUT_QUEUE_CFG)) & 0x00000002 ) >> 1) #define GET_OUT_QUEUE_FLUSH_ID (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x0000007f ) >> 0) #define GET_OUT_QUEUE_FLUSH_MODE (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000003 ) >> 0) #define GET_OUT_QUEUE_FLUSH_SEL (((REG32(ADR_MB_OUT_QUEUE_FLUSH)) & 0x00000f00 ) >> 8) #define GET_FFO0_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0000001f ) >> 0) #define GET_FFO1_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000003e0 ) >> 5) #define GET_FFO2_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00003c00 ) >> 10) #define GET_FFO3_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x000f8000 ) >> 15) #define GET_FFO4_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x00300000 ) >> 20) #define GET_FFO5_CNT (((REG32(ADR_RD_FFOUT_CNT1)) & 0x0e000000 ) >> 25) #define GET_FFO6_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x0000000f ) >> 0) #define GET_FFO7_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000003e0 ) >> 5) #define GET_FFO8_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00007c00 ) >> 10) #define GET_FFO9_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x000f8000 ) >> 15) #define GET_FFO10_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x00f00000 ) >> 20) #define GET_FFO11_CNT (((REG32(ADR_RD_FFOUT_CNT2)) & 0x3e000000 ) >> 25) #define GET_FFO12_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000007 ) >> 0) #define GET_FFO13_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00000060 ) >> 5) #define GET_FFO14_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00007c00 ) >> 10) #define GET_FFO15_CNT (((REG32(ADR_RD_FFOUT_CNT3)) & 0x00078000 ) >> 15) #define GET_CH0_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000001 ) >> 0) #define GET_CH1_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000002 ) >> 1) #define GET_CH2_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000004 ) >> 2) #define GET_CH3_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000008 ) >> 3) #define GET_CH4_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000010 ) >> 4) #define GET_CH5_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000020 ) >> 5) #define GET_CH6_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000040 ) >> 6) #define GET_CH7_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000080 ) >> 7) #define GET_CH8_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000100 ) >> 8) #define GET_CH9_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000200 ) >> 9) #define GET_CH10_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000400 ) >> 10) #define GET_CH11_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00000800 ) >> 11) #define GET_CH12_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00001000 ) >> 12) #define GET_CH13_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00002000 ) >> 13) #define GET_CH14_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00004000 ) >> 14) #define GET_CH15_FFO_FULL (((REG32(ADR_RD_FFOUT_FULL)) & 0x00008000 ) >> 15) #define GET_CH0_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000001 ) >> 0) #define GET_CH1_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000002 ) >> 1) #define GET_CH2_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000004 ) >> 2) #define GET_CH3_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000008 ) >> 3) #define GET_CH4_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000010 ) >> 4) #define GET_CH5_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000020 ) >> 5) #define GET_CH6_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000040 ) >> 6) #define GET_CH7_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000080 ) >> 7) #define GET_CH8_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000100 ) >> 8) #define GET_CH9_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000200 ) >> 9) #define GET_CH10_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000400 ) >> 10) #define GET_CH11_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00000800 ) >> 11) #define GET_CH12_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00001000 ) >> 12) #define GET_CH13_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00002000 ) >> 13) #define GET_CH14_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00004000 ) >> 14) #define GET_CH15_LOWTHOLD_INT (((REG32(ADR_MB_THRESHOLD6)) & 0x00008000 ) >> 15) #define GET_MB_LOW_THOLD_EN (((REG32(ADR_MB_THRESHOLD6)) & 0x80000000 ) >> 31) #define GET_CH0_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x0000001f ) >> 0) #define GET_CH1_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x00001f00 ) >> 8) #define GET_CH2_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x001f0000 ) >> 16) #define GET_CH3_LOWTHOLD (((REG32(ADR_MB_THRESHOLD7)) & 0x1f000000 ) >> 24) #define GET_CH4_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x0000001f ) >> 0) #define GET_CH5_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x00001f00 ) >> 8) #define GET_CH6_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x001f0000 ) >> 16) #define GET_CH7_LOWTHOLD (((REG32(ADR_MB_THRESHOLD8)) & 0x1f000000 ) >> 24) #define GET_CH8_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x0000001f ) >> 0) #define GET_CH9_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x00001f00 ) >> 8) #define GET_CH10_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x001f0000 ) >> 16) #define GET_CH11_LOWTHOLD (((REG32(ADR_MB_THRESHOLD9)) & 0x1f000000 ) >> 24) #define GET_CH12_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x0000001f ) >> 0) #define GET_CH13_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x00001f00 ) >> 8) #define GET_CH14_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x001f0000 ) >> 16) #define GET_CH15_LOWTHOLD (((REG32(ADR_MB_THRESHOLD10)) & 0x1f000000 ) >> 24) #define GET_TRASH_TIMEOUT_EN (((REG32(ADR_MB_TRASH_CFG)) & 0x00000001 ) >> 0) #define GET_TRASH_CAN_INT (((REG32(ADR_MB_TRASH_CFG)) & 0x00000002 ) >> 1) #define GET_TRASH_INT_ID (((REG32(ADR_MB_TRASH_CFG)) & 0x000007f0 ) >> 4) #define GET_TRASH_TIMEOUT (((REG32(ADR_MB_TRASH_CFG)) & 0x03ff0000 ) >> 16) #define GET_IN_FIFO_FLUSH_ID (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x000007ff ) >> 0) #define GET_IN_FIFO_FLUSH_MODE (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000003 ) >> 0) #define GET_IN_FIFO_FLUSH_SEL (((REG32(ADR_MB_IN_FF_FLUSH)) & 0x00000f00 ) >> 8) #define GET_CPU_ID_TB2 (((REG32(ADR_CPU_ID_TB2)) & 0xffffffff ) >> 0) #define GET_CPU_ID_TB3 (((REG32(ADR_CPU_ID_TB3)) & 0xffffffff ) >> 0) #define GET_IQ_LOG_EN (((REG32(ADR_PHY_IQ_LOG_CFG0)) & 0x00000001 ) >> 0) #define GET_IQ_LOG_STOP_MODE (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0x00000001 ) >> 0) #define GET_IQ_LOG_TIMER (((REG32(ADR_PHY_IQ_LOG_CFG1)) & 0xffff0000 ) >> 16) #define GET_IQ_LOG_LEN (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0x0000ffff ) >> 0) #define GET_IQ_LOG_ST_ADR (((REG32(ADR_PHY_IQ_LOG_LEN)) & 0xffff0000 ) >> 16) #define GET_IQ_LOG_TAIL_ADR (((REG32(ADR_PHY_IQ_LOG_PTR)) & 0x0000ffff ) >> 0) #define GET_ALC_LENG (((REG32(ADR_WR_ALC)) & 0x0003ffff ) >> 0) #define GET_CH0_DYN_PRI (((REG32(ADR_WR_ALC)) & 0x00300000 ) >> 20) #define GET_MCU_PKTID (((REG32(ADR_GETID)) & 0xffffffff ) >> 0) #define GET_CH0_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000003 ) >> 0) #define GET_CH1_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000030 ) >> 4) #define GET_CH2_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00000300 ) >> 8) #define GET_CH3_STA_PRI (((REG32(ADR_CH_STA_PRI)) & 0x00003000 ) >> 12) #define GET_ID_TB0 (((REG32(ADR_RD_ID0)) & 0xffffffff ) >> 0) #define GET_ID_TB1 (((REG32(ADR_RD_ID1)) & 0xffffffff ) >> 0) #define GET_ID_MNG_HALT (((REG32(ADR_IMD_CFG)) & 0x00000010 ) >> 4) #define GET_ID_MNG_ERR_HALT_EN (((REG32(ADR_IMD_CFG)) & 0x00000020 ) >> 5) #define GET_ID_EXCEPT_FLG_CLR (((REG32(ADR_IMD_CFG)) & 0x00000040 ) >> 6) #define GET_ID_EXCEPT_FLG (((REG32(ADR_IMD_CFG)) & 0x00000080 ) >> 7) #define GET_ID_FULL (((REG32(ADR_IMD_STA)) & 0x00000001 ) >> 0) #define GET_ID_MNG_BUSY (((REG32(ADR_IMD_STA)) & 0x00000002 ) >> 1) #define GET_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000004 ) >> 2) #define GET_CH0_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000010 ) >> 4) #define GET_CH1_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000020 ) >> 5) #define GET_CH2_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000040 ) >> 6) #define GET_CH3_REQ_LOCK (((REG32(ADR_IMD_STA)) & 0x00000080 ) >> 7) #define GET_REQ_LOCK_INT_EN (((REG32(ADR_IMD_STA)) & 0x00000100 ) >> 8) #define GET_REQ_LOCK_INT (((REG32(ADR_IMD_STA)) & 0x00000200 ) >> 9) #define GET_MCU_ALC_READY (((REG32(ADR_ALC_STA)) & 0x00000001 ) >> 0) #define GET_ALC_FAIL (((REG32(ADR_ALC_STA)) & 0x00000002 ) >> 1) #define GET_ALC_BUSY (((REG32(ADR_ALC_STA)) & 0x00000004 ) >> 2) #define GET_CH0_NVLD (((REG32(ADR_ALC_STA)) & 0x00000010 ) >> 4) #define GET_CH1_NVLD (((REG32(ADR_ALC_STA)) & 0x00000020 ) >> 5) #define GET_CH2_NVLD (((REG32(ADR_ALC_STA)) & 0x00000040 ) >> 6) #define GET_CH3_NVLD (((REG32(ADR_ALC_STA)) & 0x00000080 ) >> 7) #define GET_ALC_INT_ID (((REG32(ADR_ALC_STA)) & 0x00007f00 ) >> 8) #define GET_ALC_TIMEOUT (((REG32(ADR_ALC_STA)) & 0x03ff0000 ) >> 16) #define GET_ALC_TIMEOUT_INT_EN (((REG32(ADR_ALC_STA)) & 0x40000000 ) >> 30) #define GET_ALC_TIMEOUT_INT (((REG32(ADR_ALC_STA)) & 0x80000000 ) >> 31) #define GET_TX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x000000ff ) >> 0) #define GET_RX_ID_COUNT (((REG32(ADR_TRX_ID_COUNT)) & 0x0000ff00 ) >> 8) #define GET_TX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000000ff ) >> 0) #define GET_RX_ID_THOLD (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x0000ff00 ) >> 8) #define GET_ID_THOLD_RX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00010000 ) >> 16) #define GET_RX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x000e0000 ) >> 17) #define GET_ID_THOLD_TX_INT (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00100000 ) >> 20) #define GET_TX_INT_CH (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x00e00000 ) >> 21) #define GET_ID_THOLD_INT_EN (((REG32(ADR_TRX_ID_THRESHOLD)) & 0x01000000 ) >> 24) #define GET_TX_ID_TB0 (((REG32(ADR_TX_ID0)) & 0xffffffff ) >> 0) #define GET_TX_ID_TB1 (((REG32(ADR_TX_ID1)) & 0xffffffff ) >> 0) #define GET_RX_ID_TB0 (((REG32(ADR_RX_ID0)) & 0xffffffff ) >> 0) #define GET_RX_ID_TB1 (((REG32(ADR_RX_ID1)) & 0xffffffff ) >> 0) #define GET_DOUBLE_RLS_INT_EN (((REG32(ADR_RTN_STA)) & 0x00000001 ) >> 0) #define GET_ID_DOUBLE_RLS_INT (((REG32(ADR_RTN_STA)) & 0x00000002 ) >> 1) #define GET_DOUBLE_RLS_ID (((REG32(ADR_RTN_STA)) & 0x00007f00 ) >> 8) #define GET_ID_LEN_THOLD_INT_EN (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000001 ) >> 0) #define GET_ALL_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000002 ) >> 1) #define GET_TX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000004 ) >> 2) #define GET_RX_ID_LEN_THOLD_INT (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00000008 ) >> 3) #define GET_ID_TX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x00001ff0 ) >> 4) #define GET_ID_RX_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x003fe000 ) >> 13) #define GET_ID_LEN_THOLD (((REG32(ADR_ID_LEN_THREADSHOLD1)) & 0x7fc00000 ) >> 22) #define GET_ALL_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x000001ff ) >> 0) #define GET_TX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x0003fe00 ) >> 9) #define GET_RX_ID_ALC_LEN (((REG32(ADR_ID_LEN_THREADSHOLD2)) & 0x07fc0000 ) >> 18) #define GET_CH_ARB_EN (((REG32(ADR_CH_ARB_PRI)) & 0x00000001 ) >> 0) #define GET_CH_PRI1 (((REG32(ADR_CH_ARB_PRI)) & 0x00000030 ) >> 4) #define GET_CH_PRI2 (((REG32(ADR_CH_ARB_PRI)) & 0x00000300 ) >> 8) #define GET_CH_PRI3 (((REG32(ADR_CH_ARB_PRI)) & 0x00003000 ) >> 12) #define GET_CH_PRI4 (((REG32(ADR_CH_ARB_PRI)) & 0x00030000 ) >> 16) #define GET_TX_ID_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0000007f ) >> 0) #define GET_TX_PAGE_REMAIN (((REG32(ADR_TX_ID_REMAIN_STATUS)) & 0x0001ff00 ) >> 8) #define GET_ID_PAGE_MAX_SIZE (((REG32(ADR_ID_INFO_STA)) & 0x000001ff ) >> 0) #define GET_TX_PAGE_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x000001ff ) >> 0) #define GET_TX_COUNT_LIMIT (((REG32(ADR_TX_LIMIT_INTR)) & 0x00ff0000 ) >> 16) #define GET_TX_LIMIT_INT (((REG32(ADR_TX_LIMIT_INTR)) & 0x40000000 ) >> 30) #define GET_TX_LIMIT_INT_EN (((REG32(ADR_TX_LIMIT_INTR)) & 0x80000000 ) >> 31) #define GET_TX_PAGE_USE_7_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x000000ff ) >> 0) #define GET_TX_ID_USE_5_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x00003f00 ) >> 8) #define GET_EDCA0_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x0003c000 ) >> 14) #define GET_EDCA1_FFO_CNT_3_0 (((REG32(ADR_TX_ID_ALL_INFO)) & 0x003c0000 ) >> 18) #define GET_EDCA2_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0x07c00000 ) >> 22) #define GET_EDCA3_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO)) & 0xf8000000 ) >> 27) #define GET_ID_TB2 (((REG32(ADR_RD_ID2)) & 0xffffffff ) >> 0) #define GET_ID_TB3 (((REG32(ADR_RD_ID3)) & 0xffffffff ) >> 0) #define GET_TX_ID_TB2 (((REG32(ADR_TX_ID2)) & 0xffffffff ) >> 0) #define GET_TX_ID_TB3 (((REG32(ADR_TX_ID3)) & 0xffffffff ) >> 0) #define GET_RX_ID_TB2 (((REG32(ADR_RX_ID2)) & 0xffffffff ) >> 0) #define GET_RX_ID_TB3 (((REG32(ADR_RX_ID3)) & 0xffffffff ) >> 0) #define GET_TX_PAGE_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x000001ff ) >> 0) #define GET_TX_ID_USE2 (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x0001fe00 ) >> 9) #define GET_EDCA4_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x001e0000 ) >> 17) #define GET_EDCA5_FFO_CNT (((REG32(ADR_TX_ID_ALL_INFO2)) & 0x03e00000 ) >> 21) #define GET_TX_PAGE_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x000001ff ) >> 0) #define GET_TX_ID_USE3 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x0001fe00 ) >> 9) #define GET_EDCA1_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x003e0000 ) >> 17) #define GET_EDCA4_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0x07800000 ) >> 23) #define GET_EDCA5_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_A)) & 0xf8000000 ) >> 27) #define GET_TX_PAGE_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x000001ff ) >> 0) #define GET_TX_ID_USE4 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x0001fe00 ) >> 9) #define GET_EDCA2_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x003e0000 ) >> 17) #define GET_EDCA3_FFO_CNT2 (((REG32(ADR_TX_ID_ALL_INFO_B)) & 0x07c00000 ) >> 22) #define GET_TX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x000001ff ) >> 0) #define GET_RX_ID_IFO_LEN (((REG32(ADR_TX_ID_REMAIN_STATUS2)) & 0x01ff0000 ) >> 16) #define GET_MAX_ALL_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x000000ff ) >> 0) #define GET_MAX_TX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x0000ff00 ) >> 8) #define GET_MAX_RX_ALC_ID_CNT (((REG32(ADR_ALC_ID_INFO)) & 0x00ff0000 ) >> 16) #define GET_MAX_ALL_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x000001ff ) >> 0) #define GET_MAX_TX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x0003fe00 ) >> 9) #define GET_MAX_RX_ID_ALC_LEN (((REG32(ADR_ALC_ID_INF1)) & 0x07fc0000 ) >> 18) #define GET_ALC_ABT_ID (((REG32(ADR_ALC_ABORT)) & 0x0000007f ) >> 0) #define GET_ALC_ABT_STS (((REG32(ADR_ALC_ABORT)) & 0x00000100 ) >> 8) #define GET_ALC_ABT_CLR (((REG32(ADR_ALC_ABORT)) & 0x00000200 ) >> 9) #define GET_ALC_ERR_STS (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000001 ) >> 0) #define GET_RLS_ERR_STS (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000002 ) >> 1) #define GET_ALC_ERR_CLR (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000004 ) >> 2) #define GET_RLS_ERR_CLR (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000008 ) >> 3) #define GET_AL_STATE (((REG32(ADR_ALC_RLS_STATUS)) & 0x00000700 ) >> 8) #define GET_RL_STATE (((REG32(ADR_ALC_RLS_STATUS)) & 0x00007000 ) >> 12) #define GET_ALC_ERR_ID (((REG32(ADR_ALC_RLS_STATUS)) & 0x007f0000 ) >> 16) #define GET_RLS_ERR_ID (((REG32(ADR_ALC_RLS_STATUS)) & 0x7f000000 ) >> 24) #define GET_DMN_NOHIT_STS (((REG32(ADR_DMN_STATUS)) & 0x00000001 ) >> 0) #define GET_DMN_NOHIT_CLR (((REG32(ADR_DMN_STATUS)) & 0x00000002 ) >> 1) #define GET_DMN_WR (((REG32(ADR_DMN_STATUS)) & 0x00000004 ) >> 2) #define GET_DMN_PORT (((REG32(ADR_DMN_STATUS)) & 0x000000f0 ) >> 4) #define GET_DMN_NHIT_ID (((REG32(ADR_DMN_STATUS)) & 0x00007f00 ) >> 8) #define GET_DMN_NHIT_ADDR (((REG32(ADR_DMN_STATUS)) & 0x00ff0000 ) >> 16) #define GET_AVA_TAG (((REG32(ADR_TAG_STATUS)) & 0x000001ff ) >> 0) #define GET_PKTBUF_FULL (((REG32(ADR_TAG_STATUS)) & 0x00010000 ) >> 16) #define GET_PKT_REQ_STATUS (((REG32(ADR_REQ_STATUS)) & 0x0000ffff ) >> 0) #define GET_PG_TAG_31_0 (((REG32(ADR_PAGE_TAG_STATUS_0)) & 0xffffffff ) >> 0) #define GET_PG_TAG_63_32 (((REG32(ADR_PAGE_TAG_STATUS_1)) & 0xffffffff ) >> 0) #define GET_PG_TAG_95_64 (((REG32(ADR_PAGE_TAG_STATUS_2)) & 0xffffffff ) >> 0) #define GET_PG_TAG_127_96 (((REG32(ADR_PAGE_TAG_STATUS_3)) & 0xffffffff ) >> 0) #define GET_PG_TAG_159_128 (((REG32(ADR_PAGE_TAG_STATUS_4)) & 0xffffffff ) >> 0) #define GET_PG_TAG_191_160 (((REG32(ADR_PAGE_TAG_STATUS_5)) & 0xffffffff ) >> 0) #define GET_PG_TAG_223_192 (((REG32(ADR_PAGE_TAG_STATUS_6)) & 0xffffffff ) >> 0) #define GET_PG_TAG_255_224 (((REG32(ADR_PAGE_TAG_STATUS_7)) & 0xffffffff ) >> 0) #define GET_FPGA_TO_GEMINIA_DAC_SIGN_SWAP (((REG32(ADR_FPGA_GEMINIARF_SWITCH)) & 0x00000002 ) >> 1) #define GET_FPGA_TO_GEMINIA_DAC_EDGE_SEL (((REG32(ADR_FPGA_GEMINIARF_SWITCH)) & 0x00000004 ) >> 2) #define GET_FPGA_TO_GEMINIA_ADC_EDGE_SEL (((REG32(ADR_FPGA_GEMINIARF_SWITCH)) & 0x00000008 ) >> 3) // the following is for setting CSR fields // please define platform dependent REG32_R/REG32_W // #define REG32_R(_REG_) (*(volatile u32 *) _REG_) // #define REG32_W(_REG_,_val_) (*(volatile u32 *) _REG_ = _val_) #define SET_REG(_REG_, _VAL_, _SHIFT_, _MASK_) \ ({u32 reg = REG32_R(_REG_); reg =((((_VAL_) << _SHIFT_) & ~_MASK_) | (reg & _MASK_)); REG32_W(_REG_, reg); reg;}) #define SET_FBUS_DMAC_SAR0(_VAL_) SET_REG(ADR_FBUS_SAR0,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_DAR0(_VAL_) SET_REG(ADR_FBUS_DAR0,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_INTR_EN0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,0,0xfffffffe) #define SET_FBUS_DMAC_DST_TR_WIDTH0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,1,0xfffffff1) #define SET_FBUS_DMAC_SRC_TR_WIDTH0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,4,0xffffff8f) #define SET_FBUS_DMAC_DINC0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,7,0xfffffe7f) #define SET_FBUS_DMAC_SINC0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,9,0xfffff9ff) #define SET_FBUS_DMAC_DST_MSIZE0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,11,0xffffc7ff) #define SET_FBUS_DMAC_SRC_MSIZE0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,14,0xfffe3fff) #define SET_FBUS_DMAC_FC_MODE0(_VAL_) SET_REG(ADR_FBUS_CTL0_1,_VAL_,20,0xff8fffff) #define SET_FBUS_DMAC_BLOCK0(_VAL_) SET_REG(ADR_FBUS_CTL0_2,_VAL_,0,0xfffff000) #define SET_FBUS_DMAC_CH0_PRIOR(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,5,0xffffffdf) #define SET_FBUS_DMAC_HS_SEL_DST0(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,10,0xfffffbff) #define SET_FBUS_DMAC_HS_SEL_SRC0(_VAL_) SET_REG(ADR_FBUS_CFG0_1,_VAL_,11,0xfffff7ff) #define SET_FBUS_DMAC_SRC_HS_BUS_SEL0(_VAL_) SET_REG(ADR_FBUS_CFG0_2,_VAL_,7,0xfffffc7f) #define SET_FBUS_DMAC_DST_HS_BUS_SEL0(_VAL_) SET_REG(ADR_FBUS_CFG0_2,_VAL_,11,0xffffc7ff) #define SET_FBUS_DMAC_SAR1(_VAL_) SET_REG(ADR_FBUS_SAR1,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_DAR1(_VAL_) SET_REG(ADR_FBUS_DAR1,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_INTR_EN1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,0,0xfffffffe) #define SET_FBUS_DMAC_DST_TR_WIDTH1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,1,0xfffffff1) #define SET_FBUS_DMAC_SRC_TR_WIDTH1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,4,0xffffff8f) #define SET_FBUS_DMAC_DINC1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,7,0xfffffe7f) #define SET_FBUS_DMAC_SINC1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,9,0xfffff9ff) #define SET_FBUS_DMAC_DST_MSIZE1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,11,0xffffc7ff) #define SET_FBUS_DMAC_SRC_MSIZE1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,14,0xfffe3fff) #define SET_FBUS_DMAC_FC_MODE1(_VAL_) SET_REG(ADR_FBUS_CTL1_1,_VAL_,20,0xff8fffff) #define SET_FBUS_DMAC_BLOCK1(_VAL_) SET_REG(ADR_FBUS_CTL1_2,_VAL_,0,0xfffff000) #define SET_FBUS_DMAC_CH1_PRIOR(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,5,0xffffffdf) #define SET_FBUS_DMAC_HS_SEL_DST1(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,10,0xfffffbff) #define SET_FBUS_DMAC_HS_SEL_SRC1(_VAL_) SET_REG(ADR_FBUS_CFG1_1,_VAL_,11,0xfffff7ff) #define SET_FBUS_DMAC_SRC_HS_BUS_SEL1(_VAL_) SET_REG(ADR_FBUS_CFG1_2,_VAL_,7,0xfffffc7f) #define SET_FBUS_DMAC_DST_HS_BUS_SEL1(_VAL_) SET_REG(ADR_FBUS_CFG1_2,_VAL_,11,0xffffc7ff) #define SET_FBUS_DMAC_CH_RAW_TR(_VAL_) SET_REG(ADR_FBUS_RAWTR,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_CH_ERR_TR(_VAL_) SET_REG(ADR_FBUS_RAWERR,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_CH_STATUSTR_TR(_VAL_) SET_REG(ADR_FBUS_STATUSTR,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_CH_STATUSERR_TR(_VAL_) SET_REG(ADR_FBUS_STATUSERR,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_CH_DEMASK_TR(_VAL_) SET_REG(ADR_FBUS_MASKTR,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_CH_DEMASK_ERR(_VAL_) SET_REG(ADR_FBUS_MASKERR,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_CH0_CLR_TR(_VAL_) SET_REG(ADR_FBUS_CLRTR,_VAL_,0,0xfffffffe) #define SET_FBUS_DMAC_CH1_CLR_TR(_VAL_) SET_REG(ADR_FBUS_CLRTR,_VAL_,1,0xfffffffd) #define SET_FBUS_DMAC_CH0_CLR_ERR(_VAL_) SET_REG(ADR_FBUS_CLRERR,_VAL_,0,0xfffffffe) #define SET_FBUS_DMAC_CH1_CLR_ERR(_VAL_) SET_REG(ADR_FBUS_CLRERR,_VAL_,1,0xfffffffd) #define SET_FBUS_COMBINED_INT_STATUS(_VAL_) SET_REG(ADR_FBUS_COMBINED_INT_STATUS,_VAL_,0,0x00000000) #define SET_FBUS_DMAC_DISEN_SHS_SRC_REQ(_VAL_) SET_REG(ADR_FBUS_SHS_SRC_REQ_CFG,_VAL_,0,0xffff0000) #define SET_FBUS_DMAC_DISEN_SHS_DST_REQ(_VAL_) SET_REG(ADR_FBUS_SHS_DST_REQ_CFG,_VAL_,0,0xffff0000) #define SET_FBUS_DMAC_DISEN_SHS_SRC_SREQ(_VAL_) SET_REG(ADR_FBUS_SHS_SRC_SREQ_CFG,_VAL_,0,0xffff0000) #define SET_FBUS_DMAC_DISEN_SHS_DST_SREQ(_VAL_) SET_REG(ADR_FBUS_SHS_DST_SREQ_CFG,_VAL_,0,0xffff0000) #define SET_FBUS_DMAC_EN(_VAL_) SET_REG(ADR_FBUS_DMA_EN,_VAL_,0,0xfffffffe) #define SET_FBUS_DMAC_CH_EN(_VAL_) SET_REG(ADR_FBUS_CH_EN,_VAL_,0,0xffff0000) #define SET_FBUS_CHANNEL_NO(_VAL_) SET_REG(ADR_FBUS_DMAC_INFO,_VAL_,8,0xfffff8ff) #define SET_SBUS_DMAC_SAR0(_VAL_) SET_REG(ADR_SBUS_SAR0,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_DAR0(_VAL_) SET_REG(ADR_SBUS_DAR0,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_INTR_EN0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,0,0xfffffffe) #define SET_SBUS_DMAC_DST_TR_WIDTH0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,1,0xfffffff1) #define SET_SBUS_DMAC_SRC_TR_WIDTH0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,4,0xffffff8f) #define SET_SBUS_DMAC_DINC0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,7,0xfffffe7f) #define SET_SBUS_DMAC_SINC0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,9,0xfffff9ff) #define SET_SBUS_DMAC_DST_MSIZE0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,11,0xffffc7ff) #define SET_SBUS_DMAC_SRC_MSIZE0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,14,0xfffe3fff) #define SET_SBUS_DMAC_FC_MODE0(_VAL_) SET_REG(ADR_SBUS_CTL0_1,_VAL_,20,0xff8fffff) #define SET_SBUS_DMAC_BLOCK0(_VAL_) SET_REG(ADR_SBUS_CTL0_2,_VAL_,0,0xfffff000) #define SET_SBUS_DMAC_CH0_PRIOR(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,5,0xffffffdf) #define SET_SBUS_DMAC_HS_SEL_DST0(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,10,0xfffffbff) #define SET_SBUS_DMAC_HS_SEL_SRC0(_VAL_) SET_REG(ADR_SBUS_CFG0_1,_VAL_,11,0xfffff7ff) #define SET_SBUS_DMAC_SRC_HS_BUS_SEL0(_VAL_) SET_REG(ADR_SBUS_CFG0_2,_VAL_,7,0xfffffc7f) #define SET_SBUS_DMAC_DST_HS_BUS_SEL0(_VAL_) SET_REG(ADR_SBUS_CFG0_2,_VAL_,11,0xffffc7ff) #define SET_SBUS_DMAC_SAR1(_VAL_) SET_REG(ADR_SBUS_SAR1,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_DAR1(_VAL_) SET_REG(ADR_SBUS_DAR1,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_INTR_EN1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,0,0xfffffffe) #define SET_SBUS_DMAC_DST_TR_WIDTH1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,1,0xfffffff1) #define SET_SBUS_DMAC_SRC_TR_WIDTH1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,4,0xffffff8f) #define SET_SBUS_DMAC_DINC1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,7,0xfffffe7f) #define SET_SBUS_DMAC_SINC1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,9,0xfffff9ff) #define SET_SBUS_DMAC_DST_MSIZE1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,11,0xffffc7ff) #define SET_SBUS_DMAC_SRC_MSIZE1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,14,0xfffe3fff) #define SET_SBUS_DMAC_FC_MODE1(_VAL_) SET_REG(ADR_SBUS_CTL1_1,_VAL_,20,0xff8fffff) #define SET_SBUS_DMAC_BLOCK1(_VAL_) SET_REG(ADR_SBUS_CTL1_2,_VAL_,0,0xfffff000) #define SET_SBUS_DMAC_CH1_PRIOR(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,5,0xffffffdf) #define SET_SBUS_DMAC_HS_SEL_DST1(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,10,0xfffffbff) #define SET_SBUS_DMAC_HS_SEL_SRC1(_VAL_) SET_REG(ADR_SBUS_CFG1_1,_VAL_,11,0xfffff7ff) #define SET_SBUS_DMAC_SRC_HS_BUS_SEL1(_VAL_) SET_REG(ADR_SBUS_CFG1_2,_VAL_,7,0xfffffc7f) #define SET_SBUS_DMAC_DST_HS_BUS_SEL1(_VAL_) SET_REG(ADR_SBUS_CFG1_2,_VAL_,11,0xffffc7ff) #define SET_SBUS_DMAC_CH_RAW_TR(_VAL_) SET_REG(ADR_SBUS_RAWTR,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_CH_ERR_TR(_VAL_) SET_REG(ADR_SBUS_RAWERR,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_CH_STATUSTR_TR(_VAL_) SET_REG(ADR_SBUS_STATUSTR,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_CH_STATUSERR_TR(_VAL_) SET_REG(ADR_SBUS_STATUSERR,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_CH_DEMASK_TR(_VAL_) SET_REG(ADR_SBUS_MASKTR,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_CH_DEMASK_ERR(_VAL_) SET_REG(ADR_SBUS_MASKERR,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_CH0_CLR_TR(_VAL_) SET_REG(ADR_SBUS_CLRTR,_VAL_,0,0xfffffffe) #define SET_SBUS_DMAC_CH1_CLR_TR(_VAL_) SET_REG(ADR_SBUS_CLRTR,_VAL_,1,0xfffffffd) #define SET_SBUS_DMAC_CH0_CLR_ERR(_VAL_) SET_REG(ADR_SBUS_CLRERR,_VAL_,0,0xfffffffe) #define SET_SBUS_DMAC_CH1_CLR_ERR(_VAL_) SET_REG(ADR_SBUS_CLRERR,_VAL_,1,0xfffffffd) #define SET_SBUS_COMBINED_INT_STATUS(_VAL_) SET_REG(ADR_SBUS_COMBINED_INT_STATUS,_VAL_,0,0x00000000) #define SET_SBUS_DMAC_DISEN_SHS_SRC_REQ(_VAL_) SET_REG(ADR_SBUS_SHS_SRC_REQ_CFG,_VAL_,0,0xffff0000) #define SET_SBUS_DMAC_DISEN_SHS_DST_REQ(_VAL_) SET_REG(ADR_SBUS_SHS_DST_REQ_CFG,_VAL_,0,0xffff0000) #define SET_SBUS_DMAC_DISEN_SHS_SRC_SREQ(_VAL_) SET_REG(ADR_SBUS_SHS_SRC_SREQ_CFG,_VAL_,0,0xffff0000) #define SET_SBUS_DMAC_DISEN_SHS_DST_SREQ(_VAL_) SET_REG(ADR_SBUS_SHS_DST_SREQ_CFG,_VAL_,0,0xffff0000) #define SET_SBUS_DMAC_EN(_VAL_) SET_REG(ADR_SBUS_DMA_EN,_VAL_,0,0xfffffffe) #define SET_SBUS_DMAC_CH_EN(_VAL_) SET_REG(ADR_SBUS_CH_EN,_VAL_,0,0xffff0000) #define SET_SBUS_CHANNEL_NO(_VAL_) SET_REG(ADR_SBUS_DMAC_INFO,_VAL_,8,0xfffff8ff) #define SET_I2S_ENABLE(_VAL_) SET_REG(ADR_I2S_EN,_VAL_,0,0xfffffffe) #define SET_I2S_RX_ENABLE(_VAL_) SET_REG(ADR_I2S_RX_EN,_VAL_,0,0xfffffffe) #define SET_I2S_TX_ENABLE(_VAL_) SET_REG(ADR_I2S_TX_EN,_VAL_,0,0xfffffffe) #define SET_I2S_SCLK_SOURCE_ENABLE(_VAL_) SET_REG(ADR_I2S_SCLK_SCR_EN,_VAL_,0,0xfffffffe) #define SET_I2S_SCLK_GATE(_VAL_) SET_REG(ADR_I2S_WS_DEF,_VAL_,0,0xfffffff8) #define SET_I2S_WS_LENGTH(_VAL_) SET_REG(ADR_I2S_WS_DEF,_VAL_,3,0xffffffe7) #define SET_I2S_RST_RXFIFO(_VAL_) SET_REG(ADR_RESET_RX_FIFO,_VAL_,0,0xfffffffe) #define SET_I2S_RST_TXFIFO(_VAL_) SET_REG(ADR_RESET_TX_FIFO,_VAL_,0,0xfffffffe) #define SET_I2S_L_TRX_DATA(_VAL_) SET_REG(ADR_L_TRX_DATA,_VAL_,0,0x00000000) #define SET_I2S_R_TRX_DATA(_VAL_) SET_REG(ADR_R_TRX_DATA,_VAL_,0,0x00000000) #define SET_I2S_RX_CH_ENABLE(_VAL_) SET_REG(ADR_I2S_RX_CH_EN,_VAL_,0,0xfffffffe) #define SET_I2S_TX_CH_ENABLE(_VAL_) SET_REG(ADR_I2S_TX_CH_EN,_VAL_,0,0xfffffffe) #define SET_I2S_RX_WD_RES(_VAL_) SET_REG(ADR_I2S_RX_WORD_RES,_VAL_,0,0xfffffff8) #define SET_I2S_TX_WD_RES(_VAL_) SET_REG(ADR_I2S_TX_WORD_RES,_VAL_,0,0xfffffff8) #define SET_I2S_INTR_RXDA(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,0,0xfffffffe) #define SET_I2S_INTR_RXFO(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,1,0xfffffffd) #define SET_I2S_INTR_RXFE(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,4,0xffffffef) #define SET_I2S_INTR_TXFO(_VAL_) SET_REG(ADR_I2S_INTR,_VAL_,5,0xffffffdf) #define SET_I2S_INTR_RXFA_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,0,0xfffffffe) #define SET_I2S_INTR_RXFO_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,1,0xfffffffd) #define SET_I2S_INTR_TXFE_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,4,0xffffffef) #define SET_I2S_INTR_TXFO_MASK(_VAL_) SET_REG(ADR_I2S_INTR_MASK,_VAL_,5,0xffffffdf) #define SET_I2S_RXFO(_VAL_) SET_REG(ADR_I2S_RXFO,_VAL_,0,0xfffffffe) #define SET_I2S_TXFO(_VAL_) SET_REG(ADR_I2S_TXFO,_VAL_,0,0xfffffffe) #define SET_I2S_RX_FIFO_TH(_VAL_) SET_REG(ADR_I2S_RX_FIFO_TH,_VAL_,0,0xfffffff8) #define SET_I2S_TX_FIFO_TH(_VAL_) SET_REG(ADR_I2S_TX_FIFO_TH,_VAL_,0,0xfffffff8) #define SET_I2S_RX_FIFO_FLUSH(_VAL_) SET_REG(ADR_I2S_RX_FIFO_FLUSH,_VAL_,0,0xfffffffe) #define SET_I2S_TX_FIFO_FLUSH(_VAL_) SET_REG(ADR_I2S_TX_FIFO_FLUSH,_VAL_,0,0xfffffffe) #define SET_I2S_RX_DMA(_VAL_) SET_REG(ADR_I2S_RX_DMA,_VAL_,0,0x00000000) #define SET_I2S_TX_DMA(_VAL_) SET_REG(ADR_I2S_TX_DMA,_VAL_,0,0x00000000) #define SET_I2CMST_ENABLE_MASTER(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,0,0xfffffffe) #define SET_I2CMST_SPEED(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,1,0xfffffff9) #define SET_I2CMST_RESTART_EN(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,5,0xffffffdf) #define SET_I2CMST_DISABLE_SLAVE(_VAL_) SET_REG(ADR_I2CMST_CFG0,_VAL_,6,0xffffffbf) #define SET_I2CMST_TAR(_VAL_) SET_REG(ADR_I2CMST_TAR,_VAL_,0,0xfffffc00) #define SET_I2CMST_TRX_DATA(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,0,0xffffff00) #define SET_I2CMST_TRX_CMDW(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,8,0xfffffeff) #define SET_I2CMST_TRX_STOPW(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,9,0xfffffdff) #define SET_I2CMST_TRX_RESTARTW(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,10,0xfffffbff) #define SET_I2CMST_RX_1STBRDYR(_VAL_) SET_REG(ADR_I2CMST_TRX_CMD_DATA,_VAL_,11,0xfffff7ff) #define SET_I2CMST_SCLK_H_WIDTH(_VAL_) SET_REG(ADR_I2CMST_SCLK_H_WIDTH,_VAL_,0,0xffff0000) #define SET_I2CMST_SCLK_L_WIDTH(_VAL_) SET_REG(ADR_I2CMST_SCLK_L_WIDTH,_VAL_,0,0xffff0000) #define SET_I2CMST_RXU_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,0,0xfffffffe) #define SET_I2CMST_RXO_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,1,0xfffffffd) #define SET_I2CMST_RXF_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,2,0xfffffffb) #define SET_I2CMST_TXO_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,3,0xfffffff7) #define SET_I2CMST_TXE_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,4,0xffffffef) #define SET_I2CMST_RXDONE_INT(_VAL_) SET_REG(ADR_I2CMST_INT,_VAL_,7,0xffffff7f) #define SET_I2CMST_RXU_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,0,0xfffffffe) #define SET_I2CMST_RXO_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,1,0xfffffffd) #define SET_I2CMST_RXF_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,2,0xfffffffb) #define SET_I2CMST_TXO_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,3,0xfffffff7) #define SET_I2CMST_TXE_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,4,0xffffffef) #define SET_I2CMST_RXDONE_INT_MASK(_VAL_) SET_REG(ADR_I2CMST_INT_MASK,_VAL_,7,0xffffff7f) #define SET_I2CMST_RXU_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,0,0xfffffffe) #define SET_I2CMST_RXO_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,1,0xfffffffd) #define SET_I2CMST_RXF_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,2,0xfffffffb) #define SET_I2CMST_TXO_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,3,0xfffffff7) #define SET_I2CMST_TXE_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,4,0xffffffef) #define SET_I2CMST_RXDONE_INT_STAR(_VAL_) SET_REG(ADR_I2CMST_INT_STA,_VAL_,7,0xffffff7f) #define SET_I2CMST_RX_FIFO_TH(_VAL_) SET_REG(ADR_I2CMST_RX_FIFO_TH,_VAL_,0,0xffff0000) #define SET_I2CMST_TX_FIFO_TH(_VAL_) SET_REG(ADR_I2CMST_TX_FIFO_TH,_VAL_,0,0xffff0000) #define SET_I2CMST_EN(_VAL_) SET_REG(ADR_I2CMST_ENABLE,_VAL_,0,0xfffffffe) #define SET_SPIMST_DATA_LEN(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,0,0xfffffff0) #define SET_SPIMST_CPHA(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,6,0xffffffbf) #define SET_SPIMST_CPOL(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,7,0xffffff7f) #define SET_TRX_MODE(_VAL_) SET_REG(ADR_SPIMST_CFG0,_VAL_,8,0xfffffcff) #define SET_DATA_FRAMES(_VAL_) SET_REG(ADR_SPIMST_CFG1,_VAL_,0,0xffff0000) #define SET_SPIMST_ENABLE(_VAL_) SET_REG(ADR_SPIMST_EN,_VAL_,0,0xfffffffe) #define SET_SPIMST_CEN_ENABLE(_VAL_) SET_REG(ADR_SPIMST_CEN,_VAL_,0,0xfffffffe) #define SET_SPIMST_SCLK_RATE(_VAL_) SET_REG(ADR_SPIMST_SCLK_RATE,_VAL_,0,0xffff0000) #define SET_SPIMST_TXFIFO_TH(_VAL_) SET_REG(ADR_SPIMST_TXFIFO_TH,_VAL_,0,0xfffffff0) #define SET_SPIMST_RXFIFO_TH(_VAL_) SET_REG(ADR_SPIMST_RXFIFO_TH,_VAL_,0,0xfffffff0) #define SET_TRXBUSYFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,0,0xfffffffe) #define SET_TXNOTFULLFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,1,0xfffffffd) #define SET_TXEMPTYFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,2,0xfffffffb) #define SET_RXNOTEMPTYFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,3,0xfffffff7) #define SET_RXFULLFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,4,0xffffffef) #define SET_TXERRORFLAG(_VAL_) SET_REG(ADR_SPIMST_STATUS,_VAL_,5,0xffffffdf) #define SET_SPIMST_TXE_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,0,0xfffffffe) #define SET_SPIMST_TXO_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,1,0xfffffffd) #define SET_SPIMST_RXU_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,2,0xfffffffb) #define SET_SPIMST_RXO_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,3,0xfffffff7) #define SET_SPIMST_RXF_INT_UNMASK(_VAL_) SET_REG(ADR_SPIMST_INT_MASK,_VAL_,4,0xffffffef) #define SET_SPIMST_TXE_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,0,0xfffffffe) #define SET_SPIMST_TXO_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,1,0xfffffffd) #define SET_SPIMST_RXU_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,2,0xfffffffb) #define SET_SPIMST_RXO_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,3,0xfffffff7) #define SET_SPIMST_RXF_INT(_VAL_) SET_REG(ADR_SPIMST_INT,_VAL_,4,0xffffffef) #define SET_SPIMST_TRX_DATA(_VAL_) SET_REG(ADR_SPIMST_TRX_DATA,_VAL_,0,0x00000000) #define SET_SPIMST_RX_SAMPLE_DLY(_VAL_) SET_REG(ADR_SPIMST_RX_SAMPLE_DLY,_VAL_,0,0xffffff00) #define SET_ACR_INPRESEL(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,0,0xfffffffe) #define SET_ACR_QUERYACK(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,1,0xfffffffd) #define SET_ACR_RX_0_IRQ_ENABLE(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,3,0xfffffff7) #define SET_ACR_DMAENABLE(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,4,0xffffffcf) #define SET_ACR_DATATOKEN(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,6,0xffffff3f) #define SET_ACR_TXBUFSEL(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,8,0xfffff0ff) #define SET_ACR_SGDMAENABLE(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,12,0xffffcfff) #define SET_ACR_LPM_CLK_STOP(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,14,0xffffbfff) #define SET_ACR_REQERROR(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,15,0xffff7fff) #define SET_ACR_REQLENGTH(_VAL_) SET_REG(ADR_APPLICATION_CONTROL_REG,_VAL_,16,0xf800ffff) #define SET_MDAR_MEMADDR(_VAL_) SET_REG(ADR_MEMORY_DESTINATION_ADDRESS_REG,_VAL_,0,0x00000000) #define SET_UDCR_MCE(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,0,0xfffffffe) #define SET_UDCR_MTMS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,1,0xfffffff1) #define SET_UDCR_LTE(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,4,0xffffffef) #define SET_UDCR_SOFTCONN(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,5,0xffffffdf) #define SET_UDCR_SOFTDIS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,6,0xffffffbf) #define SET_UDCR_SPI(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,8,0xfffffeff) #define SET_UDCR_RWS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,9,0xfffffdff) #define SET_UDCR_HNPS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,10,0xfffffbff) #define SET_UDCR_LPMS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,11,0xfffff7ff) #define SET_UDCR_GET_STS_CTRL(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,13,0xffffdfff) #define SET_UDCR_SET_INTF_CTRL(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,14,0xffffbfff) #define SET_UDCR_SET_CONF_CTRL(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,15,0xffff7fff) #define SET_UDCR_SYNCFRAME(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,16,0xfffeffff) #define SET_UDCR_UTD(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,17,0xfffdffff) #define SET_UDCR_DSI(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,18,0xfffbffff) #define SET_UDCR_AAHNPS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,19,0xfff7ffff) #define SET_UDCR_TM_HNPR_DIS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,20,0xffefffff) #define SET_UDCR_TM_OSRPR_DIS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,21,0xffdfffff) #define SET_UDCR_USBTESTMODE(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,24,0xf8ffffff) #define SET_UDCR_UTME(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,27,0xf7ffffff) #define SET_UDCR_UTMS(_VAL_) SET_REG(ADR_USB_AND_DEVICE_CONTROL_REG,_VAL_,28,0xefffffff) #define SET_HHR_HANDSHAKE(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,0,0xfffffffc) #define SET_HHR_ENDPOINT0_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,16,0xfffeffff) #define SET_HHR_ENDPOINT1_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,17,0xfffdffff) #define SET_HHR_ENDPOINT2_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,18,0xfffbffff) #define SET_HHR_ENDPOINT3_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,19,0xfff7ffff) #define SET_HHR_ENDPOINT4_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,20,0xffefffff) #define SET_HHR_ENDPOINT5_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,21,0xffdfffff) #define SET_HHR_ENDPOINT6_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,22,0xffbfffff) #define SET_HHR_ENDPOINT7_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,23,0xff7fffff) #define SET_HHR_ENDPOINT8_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,24,0xfeffffff) #define SET_HHR_ENDPOINT9_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,25,0xfdffffff) #define SET_HHR_ENDPOINT10_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,26,0xfbffffff) #define SET_HHR_ENDPOINT11_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,27,0xf7ffffff) #define SET_HHR_ENDPOINT12_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,28,0xefffffff) #define SET_HHR_ENDPOINT13_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,29,0xdfffffff) #define SET_HHR_ENDPOINT14_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,30,0xbfffffff) #define SET_HHR_ENDPOINT15_HALT(_VAL_) SET_REG(ADR_HANDSHAKE_AND_HALT_BIT_REG,_VAL_,31,0x7fffffff) #define SET_STR0_BMREQUSETTYPE(_VAL_) SET_REG(ADR_SETUP_TRANSACTION_REG_0,_VAL_,0,0xffffff00) #define SET_STR0_BREQUEST(_VAL_) SET_REG(ADR_SETUP_TRANSACTION_REG_0,_VAL_,8,0xffff00ff) #define SET_STR0_WVALUE(_VAL_) SET_REG(ADR_SETUP_TRANSACTION_REG_0,_VAL_,16,0x0000ffff) #define SET_STR1_WINDEX(_VAL_) SET_REG(ADR_SETUP_TRANSACTION_REG_1,_VAL_,0,0xffff0000) #define SET_STR1_WLENGTH(_VAL_) SET_REG(ADR_SETUP_TRANSACTION_REG_1,_VAL_,16,0x0000ffff) #define SET_TBCR0_BUFFEROFFSET(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_0,_VAL_,0,0xfffffc00) #define SET_TBCR0_PREINQUEUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_0,_VAL_,12,0xffff8fff) #define SET_TBCR0_BUFFERRESIDUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_0,_VAL_,16,0xf000ffff) #define SET_TBCR1_BUFFEROFFSET(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_1,_VAL_,0,0xfffffc00) #define SET_TBCR1_PREINQUEUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_1,_VAL_,12,0xffff8fff) #define SET_TBCR1_BUFFERRESIDUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_1,_VAL_,16,0xf000ffff) #define SET_TBCR2_BUFFEROFFSET(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_2,_VAL_,0,0xfffffc00) #define SET_TBCR2_PREINQUEUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_2,_VAL_,12,0xffff8fff) #define SET_TBCR2_BUFFERRESIDUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_2,_VAL_,16,0xf000ffff) #define SET_TBCR3_BUFFEROFFSET(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_3,_VAL_,0,0xfffffc00) #define SET_TBCR3_PREINQUEUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_3,_VAL_,12,0xffff8fff) #define SET_TBCR3_BUFFERRESIDUE(_VAL_) SET_REG(ADR_TXBUFFER_CONTROL_REG_3,_VAL_,16,0xf000ffff) #define SET_IER_CONNECT(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,0,0xfffffffe) #define SET_IER_DISCONNECT(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,1,0xfffffffd) #define SET_IER_RESET(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,2,0xfffffffb) #define SET_IER_SUSPEND(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,3,0xfffffff7) #define SET_IER_RESUME(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,4,0xffffffef) #define SET_IER_SOF(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,5,0xffffffdf) #define SET_IER_DMA_DONE(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,8,0xfffffeff) #define SET_IER_DMA_ERROR(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,9,0xfffffdff) #define SET_IER_CONTROL_ENDPOINT_SETUP_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,16,0xfffeffff) #define SET_IER_CONTROL_ENDPOINT_OUT_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,17,0xfffdffff) #define SET_IER_CONTROL_ENDPOINT_IN_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,18,0xfffbffff) #define SET_IER_CONTROL_ENDPOINT_QUERY_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,19,0xfff7ffff) #define SET_IER_PEP1_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,24,0xfeffffff) #define SET_IER_PEP2_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,25,0xfdffffff) #define SET_IER_PEP3_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,26,0xfbffffff) #define SET_IER_PEP4_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,27,0xf7ffffff) #define SET_IER_PEP5_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,28,0xefffffff) #define SET_IER_PEP6_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,29,0xdfffffff) #define SET_IER_PEP7_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,30,0xbfffffff) #define SET_IER_PEP8_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_ENABLE_REG,_VAL_,31,0x7fffffff) #define SET_IDR_CONNECT(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,0,0xfffffffe) #define SET_IDR_DISCONNECT(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,1,0xfffffffd) #define SET_IDR_RESET(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,2,0xfffffffb) #define SET_IDR_SUSPEND(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,3,0xfffffff7) #define SET_IDR_RESUME(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,4,0xffffffef) #define SET_IDR_SOF(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,5,0xffffffdf) #define SET_IDR_DMA_DONE(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,8,0xfffffeff) #define SET_IDR_DMA_ERROR(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,9,0xfffffdff) #define SET_IDR_CONTROL_ENDPOINT_SETUP_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,16,0xfffeffff) #define SET_IDR_CONTROL_ENDPOINT_OUT_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,17,0xfffdffff) #define SET_IDR_CONTROL_ENDPOINT_IN_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,18,0xfffbffff) #define SET_IDR_CONTROL_ENDPOINT_QUERY_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,19,0xfff7ffff) #define SET_IDR_PEP1_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,24,0xfeffffff) #define SET_IDR_PEP2_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,25,0xfdffffff) #define SET_IDR_PEP3_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,26,0xfbffffff) #define SET_IDR_PEP4_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,27,0xf7ffffff) #define SET_IDR_PEP5_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,28,0xefffffff) #define SET_IDR_PEP6_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,29,0xdfffffff) #define SET_IDR_PEP7_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,30,0xbfffffff) #define SET_IDR_PEP8_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_DISABLE_REG,_VAL_,31,0x7fffffff) #define SET_ISR_CONNECT(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,0,0xfffffffe) #define SET_ISR_DISCONNECT(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,1,0xfffffffd) #define SET_ISR_RESET(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,2,0xfffffffb) #define SET_ISR_SUSPEND(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,3,0xfffffff7) #define SET_ISR_RESUME(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,4,0xffffffef) #define SET_ISR_SOF(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,5,0xffffffdf) #define SET_ISR_DMA_DONE(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,8,0xfffffeff) #define SET_ISR_DMA_ERROR(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,9,0xfffffdff) #define SET_ISR_CONTROL_ENDPOINT_SETUP_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,16,0xfffeffff) #define SET_ISR_CONTROL_ENDPOINT_OUT_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,17,0xfffdffff) #define SET_ISR_CONTROL_ENDPOINT_IN_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,18,0xfffbffff) #define SET_ISR_CONTROL_ENDPOINT_QUERY_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,19,0xfff7ffff) #define SET_ISR_PEP1_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,24,0xfeffffff) #define SET_ISR_PEP2_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,25,0xfdffffff) #define SET_ISR_PEP3_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,26,0xfbffffff) #define SET_ISR_PEP4_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,27,0xf7ffffff) #define SET_ISR_PEP5_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,28,0xefffffff) #define SET_ISR_PEP6_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,29,0xdfffffff) #define SET_ISR_PEP7_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,30,0xbfffffff) #define SET_ISR_PEP8_TRANSACTION(_VAL_) SET_REG(ADR_INTERRUPT_STATUS_REG,_VAL_,31,0x7fffffff) #define SET_PIR0_CURRENTACTIVEALT0(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,0,0xfffffff0) #define SET_PIR0_LOGICALINTERFACENUM0(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,4,0xffffff0f) #define SET_PIR0_CONFIGURATIONNUM0(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,8,0xfffff0ff) #define SET_PIR0_MAXALTNUM0(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,12,0xffff0fff) #define SET_PIR0_CURRENTACTIVEALT1(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,16,0xfff0ffff) #define SET_PIR0_LOGICALINTERFACENUM1(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,20,0xff0fffff) #define SET_PIR0_CONFIGURATIONNUM1(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,24,0xf0ffffff) #define SET_PIR0_MAXALTNUM1(_VAL_) SET_REG(ADR_PHYSICAL_INTERFACE_REG_0,_VAL_,28,0x0fffffff) #define SET_EDR0_EP_TYPE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,0,0xfffffff8) #define SET_EDR0_EP_DIR(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,3,0xfffffff7) #define SET_EDR0_EP_NO(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,4,0xffffff0f) #define SET_EDR0_EP_ALTER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,8,0xfffff0ff) #define SET_EDR0_EP_PHYINTERFACE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,12,0xffff0fff) #define SET_EDR0_EP_MAXSIZE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,16,0xf800ffff) #define SET_EDR0_EP_NAK(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,27,0xf7ffffff) #define SET_EDR0_EP_INBUFFER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_0,_VAL_,28,0x0fffffff) #define SET_EDR1_EP_TYPE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,0,0xfffffff8) #define SET_EDR1_EP_DIR(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,3,0xfffffff7) #define SET_EDR1_EP_NO(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,4,0xffffff0f) #define SET_EDR1_EP_ALTER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,8,0xfffff0ff) #define SET_EDR1_EP_PHYINTERFACE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,12,0xffff0fff) #define SET_EDR1_EP_MAXSIZE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,16,0xf800ffff) #define SET_EDR1_EP_NAK(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,27,0xf7ffffff) #define SET_EDR1_EP_INBUFFER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_1,_VAL_,28,0x0fffffff) #define SET_EDR2_EP_TYPE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,0,0xfffffff8) #define SET_EDR2_EP_DIR(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,3,0xfffffff7) #define SET_EDR2_EP_NO(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,4,0xffffff0f) #define SET_EDR2_EP_ALTER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,8,0xfffff0ff) #define SET_EDR2_EP_PHYINTERFACE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,12,0xffff0fff) #define SET_EDR2_EP_MAXSIZE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,16,0xf800ffff) #define SET_EDR2_EP_NAK(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,27,0xf7ffffff) #define SET_EDR2_EP_INBUFFER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_2,_VAL_,28,0x0fffffff) #define SET_EDR3_EP_TYPE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,0,0xfffffff8) #define SET_EDR3_EP_DIR(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,3,0xfffffff7) #define SET_EDR3_EP_NO(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,4,0xffffff0f) #define SET_EDR3_EP_ALTER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,8,0xfffff0ff) #define SET_EDR3_EP_PHYINTERFACE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,12,0xffff0fff) #define SET_EDR3_EP_MAXSIZE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,16,0xf800ffff) #define SET_EDR3_EP_NAK(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,27,0xf7ffffff) #define SET_EDR3_EP_INBUFFER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_3,_VAL_,28,0x0fffffff) #define SET_EDR4_EP_TYPE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,0,0xfffffff8) #define SET_EDR4_EP_DIR(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,3,0xfffffff7) #define SET_EDR4_EP_NO(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,4,0xffffff0f) #define SET_EDR4_EP_ALTER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,8,0xfffff0ff) #define SET_EDR4_EP_PHYINTERFACE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,12,0xffff0fff) #define SET_EDR4_EP_MAXSIZE(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,16,0xf800ffff) #define SET_EDR4_EP_NAK(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,27,0xf7ffffff) #define SET_EDR4_EP_INBUFFER(_VAL_) SET_REG(ADR_ENDPOINT_DESCRIPTOR_REG_4,_VAL_,28,0x0fffffff) #define SET_TIMER_COUNT_VALUE(_VAL_) SET_REG(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_0,_VAL_,0,0xffff0000) #define SET_TIMER_RELOAD_VALUE(_VAL_) SET_REG(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1,_VAL_,0,0xffff0000) #define SET_CORECLKIN_POWER_SAVING_MODE(_VAL_) SET_REG(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1,_VAL_,16,0xfffeffff) #define SET_TIMER_PRE_SCALE_SELECTION(_VAL_) SET_REG(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1,_VAL_,17,0xfff1ffff) #define SET_EP4_RX_AGGREGATION_ENABLE(_VAL_) SET_REG(ADR_USB_EP4_AGGREGATION_REG,_VAL_,0,0xfffffffe) #define SET_EP4_RX_AGGREGATION_MAX_SIZE(_VAL_) SET_REG(ADR_USB_EP4_AGGREGATION_REG,_VAL_,8,0xfe0000ff) #define SET_EP_ENABLE_1(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,0,0xfffffffe) #define SET_EP_ENABLE_2(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,1,0xfffffffd) #define SET_EP_ENABLE_3(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,2,0xfffffffb) #define SET_EP_ENABLE_4(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,3,0xfffffff7) #define SET_EP_ENABLE_5(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,4,0xffffffef) #define SET_EP_ENABLE_6(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,5,0xffffffdf) #define SET_EP_ENABLE_7(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,6,0xffffffbf) #define SET_EP_ENABLE_8(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,7,0xffffff7f) #define SET_BULK_OUT_H_POR(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,8,0xfffffeff) #define SET_HCI_CONCURRENT_EN(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,9,0xfffffdff) #define SET_EP3_NAK_EN(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_0,_VAL_,10,0xfffffbff) #define SET_EP2_DATA0(_VAL_) SET_REG(ADR_USB_ACC_EP2_DATA_REG_0,_VAL_,0,0x00000000) #define SET_EP2_DATA1(_VAL_) SET_REG(ADR_USB_ACC_EP2_DATA_REG_1,_VAL_,0,0x00000000) #define SET_ACC_SUSPEND(_VAL_) SET_REG(ADR_USB_ACC_CTRL_REG_1,_VAL_,0,0xfffffffe) #define SET_ACC_CTRL_CS(_VAL_) SET_REG(ADR_USB_ACC_STATUS_REG,_VAL_,0,0xfffffff0) #define SET_CMD_REG0(_VAL_) SET_REG(ADR_EP1_DATA_REG_0,_VAL_,0,0x00000000) #define SET_CMD_REG1(_VAL_) SET_REG(ADR_EP1_DATA_REG_1,_VAL_,0,0x00000000) #define SET_CMD_REG2(_VAL_) SET_REG(ADR_EP1_DATA_REG_2,_VAL_,0,0x00000000) #define SET_LPM_ALIVE(_VAL_) SET_REG(ADR_USB_CONTROLLER_LOW_POWER_STATUS_REG,_VAL_,0,0xfffffffe) #define SET_UTMI_SUSPENDM(_VAL_) SET_REG(ADR_USB_CONTROLLER_LOW_POWER_STATUS_REG,_VAL_,1,0xfffffffd) #define SET_ID_DIG(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_0,_VAL_,0,0xfffffffe) #define SET_DEV_WAKEUP(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_0,_VAL_,1,0xfffffffd) #define SET_XTSEL(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_1,_VAL_,0,0xfffffffc) #define SET_XCFG_LOCK_RANGE_MIN(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2,_VAL_,0,0xfffffff8) #define SET_XCFG_LOCK_RANGE_MAX(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2,_VAL_,3,0xffffffc7) #define SET_XCFG_FINE_TUNE_NUM(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2,_VAL_,6,0xfffffe3f) #define SET_XCFG_COARSE_TUNE_NUM(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2,_VAL_,9,0xfffff1ff) #define SET_XCFGO(_VAL_) SET_REG(ADR_USB_CONTROLLER_CTRL_STATUS_REG_3,_VAL_,0,0xffff0000) #define SET_OUTCLKSEL(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,0,0xfffffffe) #define SET_UTMI_RESET(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,1,0xfffffffd) #define SET_PLL_EN(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,2,0xfffffffb) #define SET_UTMI_DATABUS16_8(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,3,0xfffffff7) #define SET_DEBUG_SEL(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,4,0xffffff0f) #define SET_VCONTROL_REG(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,8,0xfffff0ff) #define SET_VCONTROL_LD(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,12,0xffffefff) #define SET_HS_BIST_MODE(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,13,0xffffdfff) #define SET_OSCOUTEN(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,14,0xffffbfff) #define SET_LS_EN(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_0,_VAL_,15,0xffff7fff) #define SET_XCFGI_L(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_1,_VAL_,0,0x00000000) #define SET_XCFGI_M(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_2,_VAL_,0,0x00000000) #define SET_XCFGI_H(_VAL_) SET_REG(ADR_USB_PHY_CTRL_STATUS_REG_3,_VAL_,0,0xffffffe0) #define SET_BCWR_ID_PULLUP(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,0,0xfffffffe) #define SET_BCWR_A_VBUS_REQ(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,1,0xfffffffd) #define SET_BCWR_A_SRP_DET_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,2,0xfffffffb) #define SET_BCWR_B_CONN_DET(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,3,0xfffffff7) #define SET_BCWR_ID_DET_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,4,0xffffffef) #define SET_BCWR_A_HNP_EN(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,5,0xffffffdf) #define SET_BCWR_A_HNP_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,6,0xffffffbf) #define SET_BCWR_A_IDLE_REQ(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,7,0xffffff7f) #define SET_BCWR_B_DSCHA_VBUS(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,8,0xfffffeff) #define SET_BCWR_B_CHRG_DP(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,9,0xfffffdff) #define SET_BCWR_B_CHRG_VBUS(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,10,0xfffffbff) #define SET_BCWR_B_SESS_VLD_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,11,0xfffff7ff) #define SET_BCWR_B_HNP_REQ(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,12,0xffffefff) #define SET_BCWR_B_HNP_EN(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,13,0xffffdfff) #define SET_BCWR_B_HNP_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,14,0xffffbfff) #define SET_BCWR_TEST_MODE(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,16,0xffe0ffff) #define SET_BCWR_DP_TIMER(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,24,0xfcffffff) #define SET_BCWR_VBUS_TIMER(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,26,0xf3ffffff) #define SET_BCWR_B_CONN_LDB_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,28,0xefffffff) #define SET_BCWR_B_CONN_SDB_CHK(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,29,0xdfffffff) #define SET_BCWR_EHC_EN(_VAL_) SET_REG(ADR_OTG_LINK_WRITE_REG,_VAL_,30,0xbfffffff) #define SET_MCU_ENABLE(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,0,0xfffffffe) #define SET_MAC_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,1,0xfffffffd) #define SET_USB_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,2,0xfffffffb) #define SET_SDIO_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,3,0xfffffff7) #define SET_SPI_SLV_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,4,0xffffffef) #define SET_UART_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,5,0xffffffdf) #define SET_WDT_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,7,0xffffff7f) #define SET_BTCX_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,10,0xfffffbff) #define SET_US0TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,12,0xffffefff) #define SET_US1TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,13,0xffffdfff) #define SET_US2TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,14,0xffffbfff) #define SET_US3TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,15,0xffff7fff) #define SET_MS0TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,16,0xfffeffff) #define SET_MS1TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,17,0xfffdffff) #define SET_MS2TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,18,0xfffbffff) #define SET_MS3TMR_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,19,0xfff7ffff) #define SET_PLF_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,20,0xffefffff) #define SET_ALL_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,21,0xffdfffff) #define SET_DAT_UART_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,22,0xffbfffff) #define SET_I2C_MST_SW_RST(_VAL_) SET_REG(ADR_BRG_SW_RST,_VAL_,23,0xff7fffff) #define SET_RG_REBOOT(_VAL_) SET_REG(ADR_BOOT,_VAL_,0,0xfffffffe) #define SET_TRAP_IMG_FLS(_VAL_) SET_REG(ADR_BOOT,_VAL_,16,0xfffeffff) #define SET_TRAP_REBOOT(_VAL_) SET_REG(ADR_BOOT,_VAL_,17,0xfffdffff) #define SET_TRAP_BOOT_FLS(_VAL_) SET_REG(ADR_BOOT,_VAL_,18,0xfffbffff) #define SET_CHIP_ID_31_0(_VAL_) SET_REG(ADR_CHIP_ID_0,_VAL_,0,0x00000000) #define SET_CHIP_ID_63_32(_VAL_) SET_REG(ADR_CHIP_ID_1,_VAL_,0,0x00000000) #define SET_CHIP_ID_95_64(_VAL_) SET_REG(ADR_CHIP_ID_2,_VAL_,0,0x00000000) #define SET_CHIP_ID_127_96(_VAL_) SET_REG(ADR_CHIP_ID_3,_VAL_,0,0x00000000) #define SET_CLK_DIGI_SEL(_VAL_) SET_REG(ADR_CLOCK_SELECTION,_VAL_,0,0xfffffff0) #define SET_CLK_USB_PHY30M_SEL(_VAL_) SET_REG(ADR_CLOCK_SELECTION,_VAL_,4,0xffffffef) #define SET_SYS_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,0,0xfffffffe) #define SET_MAC_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,1,0xfffffffd) #define SET_FLASH_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,2,0xfffffffb) #define SET_SDIO_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,3,0xfffffff7) #define SET_SPI_SLV_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,4,0xffffffef) #define SET_UART_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,5,0xffffffdf) #define SET_DMA_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,6,0xffffffbf) #define SET_WDT_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,7,0xffffff7f) #define SET_I2C_SLV_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,8,0xfffffeff) #define SET_INT_CTL_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,9,0xfffffdff) #define SET_BTCX_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,10,0xfffffbff) #define SET_EFS_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,11,0xfffff7ff) #define SET_US0TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,12,0xffffefff) #define SET_US1TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,13,0xffffdfff) #define SET_US2TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,14,0xffffbfff) #define SET_US3TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,15,0xffff7fff) #define SET_MS0TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,16,0xfffeffff) #define SET_MS1TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,17,0xfffdffff) #define SET_MS2TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,18,0xfffbffff) #define SET_MS3TMR_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,19,0xfff7ffff) #define SET_SPI_MST2CBRA_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,20,0xffefffff) #define SET_AHB2PKT_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,21,0xffdfffff) #define SET_PWM_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,22,0xffbfffff) #define SET_I2C_MST_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,23,0xff7fffff) #define SET_RESET_N_CPUN10(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,24,0xfeffffff) #define SET_USB_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,25,0xfdffffff) #define SET_CLK_EN_USB_PHY30M(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,26,0xfbffffff) #define SET_CLK_EN_USB_CTRLUTMI(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,27,0xf7ffffff) #define SET_PHY_IQ_LOG_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,28,0xefffffff) #define SET_SPIMAS_CLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,29,0xdfffffff) #define SET_I2S_PCLK_EN(_VAL_) SET_REG(ADR_PLATFORM_CLOCK_ENABLE,_VAL_,30,0xbfffffff) #define SET_CLK_EN_PHYRF40M(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,0,0xfffffffe) #define SET_CLK_EN_PHYRF80M(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,1,0xfffffffd) #define SET_CLK_EN_160M_PHY(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,2,0xfffffffb) #define SET_BTCX_CSR_CLK_EN(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,10,0xfffffbff) #define SET_CLK_EN_MBIST(_VAL_) SET_REG(ADR_SYS_CSR_CLOCK_ENABLE,_VAL_,11,0xfffff7ff) #define SET_R_BOOTSTRAP_SAMPLE(_VAL_) SET_REG(ADR_BOOTSTRAP_SAMPLE,_VAL_,0,0xfffffff0) #define SET_N10_CORE_CURRENT_PC(_VAL_) SET_REG(ADR_N10_DBG1,_VAL_,0,0x00000000) #define SET_N10_STANDBY_REQ(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,27,0xf7ffffff) #define SET_N10_CORE_STANDBY_MODE(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,28,0xefffffff) #define SET_N10_CORE_DEBUG_MODE(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,29,0xdfffffff) #define SET_N10_STANDBY(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,30,0xbfffffff) #define SET_N10_WAKEUP_OK(_VAL_) SET_REG(ADR_N10_DBG2,_VAL_,31,0x7fffffff) #define SET_SYS_CLOCK_STATE(_VAL_) SET_REG(ADR_ROPMUSTATE,_VAL_,0,0xfffffff8) #define SET_ROM_READ_PROT(_VAL_) SET_REG(ADR_ROM_READ_PROT,_VAL_,0,0xfffffffe) #define SET_GPIO_STOP_SEL(_VAL_) SET_REG(ADR_GPIO_IQ_LOG_STOP,_VAL_,0,0xff800000) #define SET_GPIO_STOP_POL(_VAL_) SET_REG(ADR_GPIO_IQ_LOG_STOP,_VAL_,30,0xbfffffff) #define SET_GPIO_STOP_EN(_VAL_) SET_REG(ADR_GPIO_IQ_LOG_STOP,_VAL_,31,0x7fffffff) #define SET_TB_ADR_SEL(_VAL_) SET_REG(ADR_TB_ADR_SEL,_VAL_,0,0xffff0000) #define SET_TB_CS(_VAL_) SET_REG(ADR_TB_ADR_SEL,_VAL_,31,0x7fffffff) #define SET_TB_RDATA(_VAL_) SET_REG(ADR_TB_RDATA,_VAL_,0,0x00000000) #define SET_UART_W2B_EN(_VAL_) SET_REG(ADR_UART_W2B,_VAL_,0,0xfffffffe) #define SET_SYSCTRL_CMD(_VAL_) SET_REG(ADR_SYSCTRL_COMMAND,_VAL_,0,0x00000000) #define SET_CLK_FBUS_SEL(_VAL_) SET_REG(ADR_FBUS_CLK_SEL,_VAL_,0,0xfffffff0) #define SET_SYS_XOSC_ON(_VAL_) SET_REG(ADR_SYSCTRL_STATUS,_VAL_,0,0xfffffffe) #define SET_SYS_DPLL_ON(_VAL_) SET_REG(ADR_SYSCTRL_STATUS,_VAL_,1,0xfffffffd) #define SET_FSM_SYSCTRL(_VAL_) SET_REG(ADR_SYSCTRL_STATUS,_VAL_,8,0xffffe0ff) #define SET_I2SMAS_CLK_DIV(_VAL_) SET_REG(ADR_I2SMAS_CFG,_VAL_,0,0xffffc000) #define SET_I2S_MCLK_DIV(_VAL_) SET_REG(ADR_I2SMAS_CFG,_VAL_,16,0xfffcffff) #define SET_I2S_MASTER(_VAL_) SET_REG(ADR_I2SMAS_CFG,_VAL_,31,0x7fffffff) #define SET_HBUSREQ_LOCK(_VAL_) SET_REG(ADR_HBUSREQ_LOCK,_VAL_,0,0xffffe000) #define SET_HBURST_LOCK(_VAL_) SET_REG(ADR_HBURST_LOCK,_VAL_,0,0xffffe000) #define SET_FENCE_HIT_ADR(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,0,0xffe00000) #define SET_EDLM_SRAM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,27,0xf7ffffff) #define SET_EILM_ROM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,28,0xefffffff) #define SET_EILM_SRAM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,29,0xdfffffff) #define SET_FBUS_SRAM_ERRCK_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,30,0xbfffffff) #define SET_FENCE_HIT_EN(_VAL_) SET_REG(ADR_FENCE_CTRL,_VAL_,31,0x7fffffff) #define SET_EDLM_SRAM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,0,0xfffffffe) #define SET_EILM_ROM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,1,0xfffffffd) #define SET_EILM_SRAM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,2,0xfffffffb) #define SET_FBUS_SRAM_ERR_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,3,0xfffffff7) #define SET_FENCE_HIT_INT(_VAL_) SET_REG(ADR_FENCE_STATUS,_VAL_,4,0xffffffef) #define SET_TOP_SW_PWR_ON1_OUTPUT_PWR_ON1_1_0_0(_VAL_) SET_REG(ADR_POWER_SW_INFO,_VAL_,0,0xfffffffe) #define SET_TOP_SW_PWR_ON2_OUTPUT_PWR_ON2_1_0_0(_VAL_) SET_REG(ADR_POWER_SW_INFO,_VAL_,1,0xfffffffd) #define SET_TOP_SW_PWR_ON3_OUTPUT_PWR_ON3_1_0_0(_VAL_) SET_REG(ADR_POWER_SW_INFO,_VAL_,2,0xfffffffb) #define SET_VIAROM_EMA(_VAL_) SET_REG(ADR_VIAROM_EMA,_VAL_,0,0xfffffff8) #define SET_TEST_MODE0(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,0,0xfffffffe) #define SET_TEST_MODE1(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,1,0xfffffffd) #define SET_TEST_MODE2(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,2,0xfffffffb) #define SET_TEST_MODE3(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,3,0xfffffff7) #define SET_TEST_MODE4(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,4,0xffffffef) #define SET_TEST_MODE_ALL(_VAL_) SET_REG(ADR_TEST_MODE,_VAL_,5,0xffffffdf) #define SET_CLK_EN_CPUN10(_VAL_) SET_REG(ADR_MANUAL_RESET_N,_VAL_,1,0xfffffffd) #define SET_N10_WARM_RESET_N(_VAL_) SET_REG(ADR_MANUAL_RESET_N,_VAL_,2,0xfffffffb) #define SET_FW_EVENT(_VAL_) SET_REG(ADR_DEBUG_FIRMWARE_EVENT_FLAG,_VAL_,0,0x00000000) #define SET_HOST_EVENT(_VAL_) SET_REG(ADR_DEBUG_HOST_EVENT_FLAG,_VAL_,0,0x00000000) #define SET_CHIP_INFO_ID_31_0(_VAL_) SET_REG(ADR_CHIP_INFO_ID_0,_VAL_,0,0x00000000) #define SET_CHIP_INFO_ID_63_32(_VAL_) SET_REG(ADR_CHIP_INFO_ID_1,_VAL_,0,0x00000000) #define SET_CHIP_VER(_VAL_) SET_REG(ADR_CHIP_TYPE_VER,_VAL_,0,0xff000000) #define SET_CHIP_TYPE(_VAL_) SET_REG(ADR_CHIP_TYPE_VER,_VAL_,24,0x00ffffff) #define SET_CHIP_DATE_YYYYMMDD(_VAL_) SET_REG(ADR_CHIP_DATE_YYYYMMDD,_VAL_,0,0x00000000) #define SET_CHIP_DATE_00HHMMSS(_VAL_) SET_REG(ADR_CHIP_DATE_00HHMMSS,_VAL_,0,0xff000000) #define SET_CHIP_GITSHA_31_0(_VAL_) SET_REG(ADR_CHIP_GITSHA_0,_VAL_,0,0x00000000) #define SET_CHIP_GITSHA_63_32(_VAL_) SET_REG(ADR_CHIP_GITSHA_1,_VAL_,0,0x00000000) #define SET_CHIP_GITSHA_95_64(_VAL_) SET_REG(ADR_CHIP_GITSHA_2,_VAL_,0,0x00000000) #define SET_CHIP_GITSHA_127_96(_VAL_) SET_REG(ADR_CHIP_GITSHA_3,_VAL_,0,0x00000000) #define SET_CHIP_GITSHA_159_128(_VAL_) SET_REG(ADR_CHIP_GITSHA_4,_VAL_,0,0x00000000) #define SET_N10CFG_DEFAULT_IVB(_VAL_) SET_REG(ADR_N10CFG_DEF_IVB,_VAL_,0,0xffff0000) #define SET_SYS_N10_IVB_VAL(_VAL_) SET_REG(ADR_N10CFG_SETTING,_VAL_,16,0x0000ffff) #define SET_USB20_HOST_SELRW(_VAL_) SET_REG(ADR_USB20_HOST_SEL,_VAL_,0,0xfffffffe) #define SET_CHIP_INFO_FPGA_TAG(_VAL_) SET_REG(ADR_CHIP_INFO_FPGATAG,_VAL_,0,0x00000000) #define SET_SYS_PMU_MODE_TRAN_INT(_VAL_) SET_REG(ADR_PMU_MODE_TRAN_INT,_VAL_,0,0xfffffffe) #define SET_DBG_WRITE_TO_FINISH_SIM(_VAL_) SET_REG(ADR_DEBUG_SIM_FINISH,_VAL_,0,0xfffffffe) #define SET_DATA_SPI_WAKEUP(_VAL_) SET_REG(ADR_ALWAYS_ON_CFG00,_VAL_,0,0xfffffffe) #define SET_WAKE_SOON_WITH_SCK(_VAL_) SET_REG(ADR_SDIO_RESET_WAKE_CFG,_VAL_,0,0xfffffffe) #define SET_ALLOW_SD_SPI_RESET(_VAL_) SET_REG(ADR_SDIO_RESET_WAKE_CFG,_VAL_,1,0xfffffffd) #define SET_WDT_MCU_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,0,0xfffffffe) #define SET_WDT_SYS_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,1,0xfffffffd) #define SET_SDIO_CMD52_06H_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,2,0xfffffffb) #define SET_DATA_SPI_RESET(_VAL_) SET_REG(ADR_BOOT_INFO,_VAL_,3,0xfffffff7) #define SET_UART_NRTS(_VAL_) SET_REG(ADR_SPARE_UART_INFO,_VAL_,0,0xfffffffe) #define SET_UART_NCTS(_VAL_) SET_REG(ADR_SPARE_UART_INFO,_VAL_,1,0xfffffffd) #define SET_NORMAL_PWR_ON1(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,0,0xfffffffe) #define SET_NORMAL_PWR_ON2(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,1,0xfffffffd) #define SET_NORMAL_PWR_ON3(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,2,0xfffffffb) #define SET_SUSPEND_PWR_ON1(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,4,0xffffffef) #define SET_SUSPEND_PWR_ON2(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,5,0xffffffdf) #define SET_SUSPEND_PWR_ON3(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,6,0xffffffbf) #define SET_NORMAL_ISO_ON1(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,8,0xfffffeff) #define SET_NORMAL_ISO_ON2(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,9,0xfffffdff) #define SET_NORMAL_ISO_ON3(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,10,0xfffffbff) #define SET_TOP_ON1_RST_N(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,12,0xffffefff) #define SET_TOP_ON2_RST_N(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,13,0xffffdfff) #define SET_TOP_ON3_RST_N(_VAL_) SET_REG(ADR_POWER_ON_OFF_CTRL,_VAL_,14,0xffffbfff) #define SET_HOST_WAKE_WIFI(_VAL_) SET_REG(ADR_HOST_WAKE_WIFI_CTRL,_VAL_,0,0xff800000) #define SET_HOST_WAKE_WIFI_POL(_VAL_) SET_REG(ADR_HOST_WAKE_WIFI_CTRL,_VAL_,31,0x7fffffff) #define SET_PRESCALER_US(_VAL_) SET_REG(ADR_PRESCALER_USTIMER,_VAL_,0,0xfffffe00) #define SET_RTC_TIMER_WAKE_PMU_EN(_VAL_) SET_REG(ADR_WAKE_PMU_ENABLE,_VAL_,0,0xfffffffe) #define SET_USB_WAKE_PMU_EN(_VAL_) SET_REG(ADR_WAKE_PMU_ENABLE,_VAL_,1,0xfffffffd) #define SET_ILM160KB_EN(_VAL_) SET_REG(ADR_SRAMCFG_SETTING,_VAL_,1,0xfffffffd) #define SET_PATCH00_EN(_VAL_) SET_REG(ADR_ROM_PATCH00_0,_VAL_,0,0xfffffffe) #define SET_PATCH00_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH00_0,_VAL_,2,0xfffe0003) #define SET_PATCH00_DATA(_VAL_) SET_REG(ADR_ROM_PATCH00_1,_VAL_,0,0x00000000) #define SET_PATCH01_EN(_VAL_) SET_REG(ADR_ROM_PATCH01_0,_VAL_,0,0xfffffffe) #define SET_PATCH01_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH01_0,_VAL_,2,0xfffe0003) #define SET_PATCH01_DATA(_VAL_) SET_REG(ADR_ROM_PATCH01_1,_VAL_,0,0x00000000) #define SET_TU0_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TU0_TM_MODE(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TU0_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TU0_TM_INT_MASK(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TU0_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TU0_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TU1_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TU1_TM_MODE(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TU1_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TU1_TM_INT_MASK(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TU1_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TU1_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TU2_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TU2_TM_MODE(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TU2_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TU2_TM_INT_MASK(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TU2_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TU2_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TU3_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TU3_TM_MODE(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TU3_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TU3_TM_INT_MASK(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TU3_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TU3_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TM0_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TM0_TM_MODE(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TM0_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TM0_TM_INT_MASK(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TM0_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TM0_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM0_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TM1_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TM1_TM_MODE(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TM1_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TM1_TM_INT_MASK(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TM1_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TM1_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM1_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TM2_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TM2_TM_MODE(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TM2_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TM2_TM_INT_MASK(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TM2_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TM2_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM2_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00) #define SET_TM3_TM_INIT_VALUE(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,0,0xffff0000) #define SET_TM3_TM_MODE(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,16,0xfffeffff) #define SET_TM3_TM_INT_STS_DONE(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,17,0xfffdffff) #define SET_TM3_TM_INT_MASK(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER,_VAL_,18,0xfffbffff) #define SET_TM3_TM_CUR_VALUE(_VAL_) SET_REG(ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE,_VAL_,0,0xffff0000) #define SET_TM3_PRESCALER_USTIMER_LOCAL(_VAL_) SET_REG(ADR_TM3_MILLISECOND_TIMER_PRESCALE,_VAL_,0,0xfffffe00) #define SET_MCU_WDT_TIME_CNT(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,0,0xffff0000) #define SET_MCU_WDT_INT_CNT_OFS(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,16,0xff00ffff) #define SET_MCU_WDT_STATUS(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,30,0xbfffffff) #define SET_MCU_WDOG_ENA(_VAL_) SET_REG(ADR_MCU_WDOG_REG,_VAL_,31,0x7fffffff) #define SET_SYS_WDT_TIME_CNT(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,0,0xffff0000) #define SET_SYS_WDT_INT_CNT_OFS(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,16,0xff00ffff) #define SET_SYS_WDT_STATUS(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,30,0xbfffffff) #define SET_SYS_WDOG_ENA(_VAL_) SET_REG(ADR_SYS_WDOG_REG,_VAL_,31,0x7fffffff) #define SET_PWM_POST_SCALER_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,0,0xffffff00) #define SET_PWM_SETTING_UPDATE_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,28,0xefffffff) #define SET_PWM_ALWAYSON_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,29,0xdfffffff) #define SET_PWM_INVERT_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,30,0xbfffffff) #define SET_PWM_ENABLE_0(_VAL_) SET_REG(ADR_PWM_0_CTRL,_VAL_,31,0x7fffffff) #define SET_PWM_INI_VALUE_PERIOD_0(_VAL_) SET_REG(ADR_PWM_0_SET,_VAL_,0,0xffff0000) #define SET_PWM_INI_VALUE_P_0(_VAL_) SET_REG(ADR_PWM_0_SET,_VAL_,16,0x0000ffff) #define SET_PWM_POST_SCALER_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,0,0xffffff00) #define SET_PWM_SETTING_UPDATE_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,28,0xefffffff) #define SET_PWM_ALWAYSON_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,29,0xdfffffff) #define SET_PWM_INVERT_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,30,0xbfffffff) #define SET_PWM_ENABLE_1(_VAL_) SET_REG(ADR_PWM_1_CTRL,_VAL_,31,0x7fffffff) #define SET_PWM_INI_VALUE_PERIOD_1(_VAL_) SET_REG(ADR_PWM_1_SET,_VAL_,0,0xffff0000) #define SET_PWM_INI_VALUE_P_1(_VAL_) SET_REG(ADR_PWM_1_SET,_VAL_,16,0x0000ffff) #define SET_PWM_POST_SCALER_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,0,0xffffff00) #define SET_PWM_SETTING_UPDATE_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,28,0xefffffff) #define SET_PWM_ALWAYSON_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,29,0xdfffffff) #define SET_PWM_INVERT_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,30,0xbfffffff) #define SET_PWM_ENABLE_2(_VAL_) SET_REG(ADR_PWM_2_CTRL,_VAL_,31,0x7fffffff) #define SET_PWM_INI_VALUE_PERIOD_2(_VAL_) SET_REG(ADR_PWM_2_SET,_VAL_,0,0xffff0000) #define SET_PWM_INI_VALUE_P_2(_VAL_) SET_REG(ADR_PWM_2_SET,_VAL_,16,0x0000ffff) #define SET_PWM_POST_SCALER_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,0,0xffffff00) #define SET_PWM_SETTING_UPDATE_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,28,0xefffffff) #define SET_PWM_ALWAYSON_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,29,0xdfffffff) #define SET_PWM_INVERT_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,30,0xbfffffff) #define SET_PWM_ENABLE_3(_VAL_) SET_REG(ADR_PWM_3_CTRL,_VAL_,31,0x7fffffff) #define SET_PWM_INI_VALUE_PERIOD_3(_VAL_) SET_REG(ADR_PWM_3_SET,_VAL_,0,0xffff0000) #define SET_PWM_INI_VALUE_P_3(_VAL_) SET_REG(ADR_PWM_3_SET,_VAL_,16,0x0000ffff) #define SET_PWM_POST_SCALER_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,0,0xffffff00) #define SET_PWM_SETTING_UPDATE_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,28,0xefffffff) #define SET_PWM_ALWAYSON_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,29,0xdfffffff) #define SET_PWM_INVERT_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,30,0xbfffffff) #define SET_PWM_ENABLE_4(_VAL_) SET_REG(ADR_PWM_4_CTRL,_VAL_,31,0x7fffffff) #define SET_PWM_INI_VALUE_PERIOD_4(_VAL_) SET_REG(ADR_PWM_4_SET,_VAL_,0,0xffff0000) #define SET_PWM_INI_VALUE_P_4(_VAL_) SET_REG(ADR_PWM_4_SET,_VAL_,16,0x0000ffff) #define SET_MANUAL_IO(_VAL_) SET_REG(ADR_MANUAL_IO,_VAL_,0,0xff800000) #define SET_MANUAL_PU(_VAL_) SET_REG(ADR_MANUAL_PU,_VAL_,0,0xff800000) #define SET_MANUAL_PD(_VAL_) SET_REG(ADR_MANUAL_PD,_VAL_,0,0xff800000) #define SET_MANUAL_DS(_VAL_) SET_REG(ADR_MANUAL_DS,_VAL_,0,0xff800000) #define SET_IO_PO(_VAL_) SET_REG(ADR_IO_PO,_VAL_,0,0xff800000) #define SET_IO_PI(_VAL_) SET_REG(ADR_IO_PI,_VAL_,0,0xff800000) #define SET_IO_PIE(_VAL_) SET_REG(ADR_IO_PIE,_VAL_,0,0xff800000) #define SET_IO_POEN(_VAL_) SET_REG(ADR_IO_POEN,_VAL_,0,0xff800000) #define SET_IO_PUE(_VAL_) SET_REG(ADR_IO_PUE,_VAL_,0,0xff800000) #define SET_IO_PDE(_VAL_) SET_REG(ADR_IO_PDE,_VAL_,0,0xff800000) #define SET_IO_DS(_VAL_) SET_REG(ADR_IO_DS,_VAL_,0,0xff800000) #define SET_SEL_I2STRX_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,0,0xfffffffe) #define SET_SEL_I2STRX_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,1,0xfffffffd) #define SET_SEL_SPI_SLV(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,2,0xfffffffb) #define SET_SEL_SPI_MST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,3,0xfffffff7) #define SET_SEL_I2C_SLV(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,4,0xffffffef) #define SET_SEL_I2C_MST_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,5,0xffffffdf) #define SET_SEL_I2C_MST_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,6,0xffffffbf) #define SET_SEL_UART0_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,7,0xffffff7f) #define SET_SEL_UART0_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,8,0xfffffeff) #define SET_SEL_BTCX(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,9,0xfffffdff) #define SET_SEL_FLASH(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,10,0xfffffbff) #define SET_SEL_RF(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,11,0xfffff7ff) #define SET_SEL_PWM(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,12,0xfffe0fff) #define SET_SEL_DEBUG_I(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,17,0xfffdffff) #define SET_SEL_DEBUG_II(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,18,0xfffbffff) #define SET_SEL_MEM_BIST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,19,0xfff7ffff) #define SET_SEL_USB_BIST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,20,0xffefffff) #define SET_SEL_USB_TEST(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,21,0xffdfffff) #define SET_SEL_USB_IDDQ(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,22,0xffbfffff) #define SET_I2S_RAW_DATA(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,30,0xbfffffff) #define SET_SPI_RAW_DATA(_VAL_) SET_REG(ADR_IO_FUNC_SEL,_VAL_,31,0x7fffffff) #define SET_SEL_GPO_INT(_VAL_) SET_REG(ADR_INT_THRU_GPIO,_VAL_,0,0xff800000) #define SET_ROM_START_INDEX(_VAL_) SET_REG(ADR_BIST_CTRL,_VAL_,0,0xfffffff0) #define SET_ROM_END_INDEX(_VAL_) SET_REG(ADR_BIST_CTRL,_VAL_,4,0xffffff0f) #define SET_ROMCRC32_GOLDEN(_VAL_) SET_REG(ADR_BIST_CTRL1,_VAL_,0,0x00000000) #define SET_ROMCRC32_RESULT(_VAL_) SET_REG(ADR_BIST_CTRL2,_VAL_,0,0x00000000) #define SET_I2CS_ADDR_DC(_VAL_) SET_REG(ADR_I2CS_ID_ADDR,_VAL_,0,0xfffffffe) #define SET_I2CS_ADDR(_VAL_) SET_REG(ADR_I2CS_ID_ADDR,_VAL_,1,0xffffff01) #define SET_I2CS_INT(_VAL_) SET_REG(ADR_I2CS_STATUS,_VAL_,0,0xffffffe0) #define SET_I2CS_IDLE(_VAL_) SET_REG(ADR_I2CS_STATUS,_VAL_,10,0xfffffbff) #define SET_I2CS_TIME_OUT_CNT(_VAL_) SET_REG(ADR_I2CS_TIME_CNT,_VAL_,0,0xffff0000) #define SET_I2CS_STATE(_VAL_) SET_REG(ADR_I2CS_STATE,_VAL_,0,0xffffff00) #define SET_I2CS_DATA_CONFIG(_VAL_) SET_REG(ADR_I2CS_CTRL,_VAL_,0,0xfffffffe) #define SET_I2CS_HOLD_BUS_EN(_VAL_) SET_REG(ADR_I2CS_CTRL,_VAL_,1,0xfffffffd) #define SET_IO_PORT_REG(_VAL_) SET_REG(ADR_IO_PORT_REG,_VAL_,0,0xfffe0000) #define SET_MASK_RX_INT(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,0,0xfffffffe) #define SET_EDCA4_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,1,0xfffffffd) #define SET_MASK_SOC_SYSTEM_INT(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,2,0xfffffffb) #define SET_EDCA0_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,3,0xfffffff7) #define SET_EDCA1_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,4,0xffffffef) #define SET_EDCA2_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,5,0xffffffdf) #define SET_EDCA3_LOW_THR_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,6,0xffffffbf) #define SET_TX_LIMIT_INT_MASK(_VAL_) SET_REG(ADR_INT_MASK_REG,_VAL_,7,0xffffff7f) #define SET_RX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,0,0xfffffffe) #define SET_EDCA4_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,1,0xfffffffd) #define SET_SOC_SYSTEM_INT_STATUS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,2,0xfffffffb) #define SET_EDCA0_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,3,0xfffffff7) #define SET_EDCA1_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,4,0xffffffef) #define SET_EDCA2_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,5,0xffffffdf) #define SET_EDCA3_LOW_THR_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,6,0xffffffbf) #define SET_TX_LIMIT_INT_STS(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,7,0xffffff7f) #define SET_HOST_TRIGGERED_RX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,8,0xfffffeff) #define SET_HOST_TRIGGERED_TX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,9,0xfffffdff) #define SET_SOC_TRIGGER_RX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,10,0xfffffbff) #define SET_SOC_TRIGGER_TX_INT(_VAL_) SET_REG(ADR_INT_STATUS_REG,_VAL_,11,0xfffff7ff) #define SET_RDY_FOR_TX_RX(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,0,0xfffffffe) #define SET_RDY_FOR_FW_DOWNLOAD(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,1,0xfffffffd) #define SET_ILLEGAL_CMD_RESP_OPTION(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,2,0xfffffffb) #define SET_SDIO_TRX_DATA_SEQUENCE(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,3,0xfffffff7) #define SET_GPIO_INT_TRIGGER_OPTION(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,4,0xffffffef) #define SET_TRIGGER_FUNCTION_SETTING(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,5,0xffffff9f) #define SET_CMD52_ABORT_RESPONSE(_VAL_) SET_REG(ADR_FN1_STATUS_REG,_VAL_,7,0xffffff7f) #define SET_CARD_RCA_REG(_VAL_) SET_REG(ADR_CARD_RCA_REG,_VAL_,0,0xffff0000) #define SET_SDIO_BYTE_MODE_BATCH_SIZE_REG(_VAL_) SET_REG(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG,_VAL_,0,0xffffff00) #define SET_SDIO_CARD_STATUS_REG(_VAL_) SET_REG(ADR_SDIO_CARD_STATUS_REG,_VAL_,0,0x00000000) #define SET_R5_RESPONSE_FLAG(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,0,0xffffff00) #define SET_MCU_TO_SDIO_INFO_MASK(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,16,0xfffeffff) #define SET_INT_THROUGH_PIN(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,17,0xfffdffff) #define SET_DIRECT_INT_MUX_MODE(_VAL_) SET_REG(ADR_R5_RESP_FLAG_OUT_TIMING,_VAL_,18,0xfffbffff) #define SET_SD_CMD_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,0,0xfffffff8) #define SET_SD_CMD_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,4,0xffffff8f) #define SET_SD_DAT_3_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,8,0xfffff8ff) #define SET_SD_DAT_3_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,12,0xffff8fff) #define SET_SD_DAT_2_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,16,0xfff8ffff) #define SET_SD_DAT_2_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,20,0xff8fffff) #define SET_SD_DAT_1_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,24,0xf8ffffff) #define SET_SD_DAT_1_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_0,_VAL_,28,0x8fffffff) #define SET_SD_DAT_0_IN_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_1,_VAL_,0,0xfffffff8) #define SET_SD_DAT_0_OUT_DLY_SEL(_VAL_) SET_REG(ADR_SDIO_DELAY_CHAIN_1,_VAL_,4,0xffffff8f) #define SET_FN1_DMA_START_ADDR_REG(_VAL_) SET_REG(ADR_FN1_DMA_START_ADDR_REG,_VAL_,0,0x00000000) #define SET_SDIO_TO_MCU_INFO(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,0,0xffffff00) #define SET_SDIO_PARTIAL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,8,0xfffffeff) #define SET_SDIO_ALL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,9,0xfffffdff) #define SET_PERI_MAC_ALL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,10,0xfffffbff) #define SET_MAC_ALL_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,11,0xfffff7ff) #define SET_AHB_BRIDGE_RESET(_VAL_) SET_REG(ADR_FN1_INT_CTRL_RESET,_VAL_,12,0xffffefff) #define SET_MCU_TO_SDIO_INFO(_VAL_) SET_REG(ADR_MCU_NOTIFY_HOST_EVENT,_VAL_,0,0xffffff00) #define SET_RAW_IDLE(_VAL_) SET_REG(ADR_MCU_NOTIFY_HOST_EVENT,_VAL_,8,0xfffffeff) #define SET_PEDGE_MODE(_VAL_) SET_REG(ADR_MCU_NOTIFY_HOST_EVENT,_VAL_,9,0xfffffdff) #define SET_RAW_CLEAR(_VAL_) SET_REG(ADR_MCU_NOTIFY_HOST_EVENT,_VAL_,10,0xfffffbff) #define SET_RAW_STATE(_VAL_) SET_REG(ADR_MCU_NOTIFY_HOST_EVENT,_VAL_,11,0xffffe7ff) #define SET_FN1_DMA_RD_START_ADDR_REG(_VAL_) SET_REG(ADR_FN1_DMA_RD_START_ADDR_REG,_VAL_,0,0x00000000) #define SET_CCCR_00H_REG(_VAL_) SET_REG(ADR_CCCR_00H_REG,_VAL_,0,0xffffff00) #define SET_CCCR_02H_REG(_VAL_) SET_REG(ADR_CCCR_00H_REG,_VAL_,16,0xff00ffff) #define SET_CCCR_03H_REG(_VAL_) SET_REG(ADR_CCCR_00H_REG,_VAL_,24,0x00ffffff) #define SET_CCCR_04H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,0,0xffffff00) #define SET_CCCR_05H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,8,0xffff00ff) #define SET_CCCR_06H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,16,0xfff0ffff) #define SET_CCCR_07H_REG(_VAL_) SET_REG(ADR_CCCR_04H_REG,_VAL_,24,0x00ffffff) #define SET_SUPPORT_DIRECT_COMMAND_SDIO(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,0,0xfffffffe) #define SET_SUPPORT_MULTIPLE_BLOCK_TRANSFER(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,1,0xfffffffd) #define SET_SUPPORT_READ_WAIT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,2,0xfffffffb) #define SET_SUPPORT_BUS_CONTROL(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,3,0xfffffff7) #define SET_SUPPORT_BLOCK_GAP_INTERRUPT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,4,0xffffffef) #define SET_ENABLE_BLOCK_GAP_INTERRUPT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,5,0xffffffdf) #define SET_LOW_SPEED_CARD(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,6,0xffffffbf) #define SET_LOW_SPEED_CARD_4BIT(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,7,0xffffff7f) #define SET_COMMON_CIS_PONTER(_VAL_) SET_REG(ADR_CCCR_08H_REG,_VAL_,8,0xfe0000ff) #define SET_SD_SSDR50(_VAL_) SET_REG(ADR_CCCR_14H_REG,_VAL_,24,0xfeffffff) #define SET_SD_SSDR104(_VAL_) SET_REG(ADR_CCCR_14H_REG,_VAL_,25,0xfdffffff) #define SET_SUPPORT_HIGH_SPEED(_VAL_) SET_REG(ADR_CCCR_13H_REG,_VAL_,24,0xfeffffff) #define SET_BSS(_VAL_) SET_REG(ADR_CCCR_13H_REG,_VAL_,25,0xf1ffffff) #define SET_FBR_100H_REG(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,0,0xfffffff0) #define SET_CSASUPPORT(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,6,0xffffffbf) #define SET_ENABLECSA(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,7,0xffffff7f) #define SET_FBR_101H_REG(_VAL_) SET_REG(ADR_FBR_100H_REG,_VAL_,8,0xffff00ff) #define SET_FBR_109H_REG(_VAL_) SET_REG(ADR_FBR_109H_REG,_VAL_,8,0xfe0000ff) #define SET_F0_CIS_CONTENT_REG_31_0(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_0,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_63_32(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_1,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_95_64(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_2,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_127_96(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_3,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_159_128(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_4,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_191_160(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_5,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_223_192(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_6,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_255_224(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_7,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_287_256(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_8,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_319_288(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_9,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_351_320(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_10,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_383_352(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_11,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_415_384(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_12,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_447_416(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_13,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_479_448(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_14,_VAL_,0,0x00000000) #define SET_F0_CIS_CONTENT_REG_511_480(_VAL_) SET_REG(ADR_F0_CIS_CONTENT_REG_15,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_31_0(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_0,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_63_32(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_1,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_95_64(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_2,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_127_96(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_3,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_159_128(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_4,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_191_160(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_5,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_223_192(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_6,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_255_224(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_7,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_287_256(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_8,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_319_288(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_9,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_351_320(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_10,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_383_352(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_11,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_415_384(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_12,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_447_416(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_13,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_479_448(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_14,_VAL_,0,0x00000000) #define SET_F1_CIS_CONTENT_REG_511_480(_VAL_) SET_REG(ADR_F1_CIS_CONTENT_REG_15,_VAL_,0,0x00000000) #define SET_SPARE_MEM(_VAL_) SET_REG(ADR_SPI_MODE,_VAL_,0,0xffffff00) #define SET_TX_SEG(_VAL_) SET_REG(ADR_TX_SEG,_VAL_,0,0x00000000) #define SET_CLK_WIDTH(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM1,_VAL_,0,0xffff0000) #define SET_CSN_INTER(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM1,_VAL_,16,0x0000ffff) #define SET_BACK_DLY(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM2,_VAL_,0,0xffff0000) #define SET_FRONT_DLY(_VAL_) SET_REG(ADR_SPI_TO_PHY_PARAM2,_VAL_,16,0x0000ffff) #define SET_TWI_START_TRIG(_VAL_) SET_REG(ADR_TWIM_EN,_VAL_,0,0xfffffffe) #define SET_TWI_STOP_TRIG(_VAL_) SET_REG(ADR_TWIM_EN,_VAL_,1,0xfffffffd) #define SET_TWI_TRANS_CONTINUE(_VAL_) SET_REG(ADR_TWIM_EN,_VAL_,2,0xfffffffb) #define SET_TWI_DEV_A_10B(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,0,0xfffffffe) #define SET_TWI_MODE(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,1,0xfffffffd) #define SET_SCL(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,16,0xfffeffff) #define SET_SDA(_VAL_) SET_REG(ADR_TWIM_STATUS_SETTING,_VAL_,17,0xfffdffff) #define SET_TWI_INT_TXD_STALL_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,0,0xfffffffe) #define SET_TWI_INT_RXD_STALL_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,1,0xfffffffd) #define SET_TWI_INT_TRANS_FINISH_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,2,0xfffffffb) #define SET_TWI_INT_MISMATCH_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,3,0xfffffff7) #define SET_TWI_INT_TRANS_FAIL_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,4,0xffffffef) #define SET_TWI_INT_HOLD_BUS_EN(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_EN,_VAL_,5,0xffffffdf) #define SET_TWI_INT_TXD_STALL(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,0,0xfffffffe) #define SET_TWI_INT_RXD_STALL(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,1,0xfffffffd) #define SET_TWI_INT_TRANS_FINISH(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,2,0xfffffffb) #define SET_TWI_INT_MISMATCH(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,3,0xfffffff7) #define SET_TWI_INT_TRANS_FAIL(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,4,0xffffffef) #define SET_TWI_INT_HOLD_BUS(_VAL_) SET_REG(ADR_TWIM_INTERRUPT,_VAL_,5,0xffffffdf) #define SET_TWI_INT_TXD_STALL_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,0,0xfffffffe) #define SET_TWI_INT_RXD_STALL_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,1,0xfffffffd) #define SET_TWI_INT_TRANS_FINISH_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,2,0xfffffffb) #define SET_TWI_INT_MISMATCH_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,3,0xfffffff7) #define SET_TWI_INT_TRANS_FAIL_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,4,0xffffffef) #define SET_TWI_INT_HOLD_BUS_ST(_VAL_) SET_REG(ADR_TWIM_INTERRUPT_STATUS,_VAL_,5,0xffffffdf) #define SET_TWI_STATUS_RECORD_0(_VAL_) SET_REG(ADR_TWIM_STATUS_RECORD_0,_VAL_,0,0x00000000) #define SET_TWI_STATUS_RECORD_1(_VAL_) SET_REG(ADR_TWIM_STATUS_RECORD_1,_VAL_,0,0x00000000) #define SET_TWI_RX(_VAL_) SET_REG(ADR_TWIM_DEV_A,_VAL_,0,0xfffffffe) #define SET_TWI_DEV_A10B(_VAL_) SET_REG(ADR_TWIM_DEV_A,_VAL_,1,0xfffff801) #define SET_TWI_TXD_DATA(_VAL_) SET_REG(ADR_TWIM_TXD_DATA,_VAL_,0,0xffffff00) #define SET_TWI_RXD_DATA(_VAL_) SET_REG(ADR_TWIM_RXD_DATA,_VAL_,0,0xffffff00) #define SET_TWI_PSCL(_VAL_) SET_REG(ADR_TWIM_PSCL,_VAL_,0,0xfffffc00) #define SET_TWI_STA_STO_PSCL(_VAL_) SET_REG(ADR_TWIM_PSCL,_VAL_,16,0xfc00ffff) #define SET_TWI_TRANS_PSDA(_VAL_) SET_REG(ADR_TWIM_TRANS_PSDA,_VAL_,0,0xfffffc00) #define SET_TWI_DELAY_ACK(_VAL_) SET_REG(ADR_TWIM_DELAY_ACK,_VAL_,0,0xfffffc00) #define SET_I2CM_INT_WDONE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,0,0xfffffffe) #define SET_I2CM_INT_RDONE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,1,0xfffffffd) #define SET_I2CM_IDLE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,2,0xfffffffb) #define SET_I2CM_INT_MISMATCH(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,3,0xfffffff7) #define SET_I2CM_PSCL(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,4,0xffffc00f) #define SET_I2CM_MANUAL_MODE(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,16,0xfffeffff) #define SET_I2CM_INT_WDATA_NEED(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,17,0xfffdffff) #define SET_I2CM_INT_RDATA_NEED(_VAL_) SET_REG(ADR_I2CM_EN,_VAL_,18,0xfffbffff) #define SET_I2CM_DEV_A(_VAL_) SET_REG(ADR_I2CM_DEV_A,_VAL_,0,0xfffffc00) #define SET_I2CM_DEV_A10B(_VAL_) SET_REG(ADR_I2CM_DEV_A,_VAL_,14,0xffffbfff) #define SET_I2CM_RX(_VAL_) SET_REG(ADR_I2CM_DEV_A,_VAL_,15,0xffff7fff) #define SET_I2CM_LEN(_VAL_) SET_REG(ADR_I2CM_LEN,_VAL_,0,0xffff0000) #define SET_I2CM_T_LEFT(_VAL_) SET_REG(ADR_I2CM_LEN,_VAL_,16,0xfff8ffff) #define SET_I2CM_R_GET(_VAL_) SET_REG(ADR_I2CM_LEN,_VAL_,24,0xf8ffffff) #define SET_I2CM_WDAT(_VAL_) SET_REG(ADR_I2CM_WDAT,_VAL_,0,0x00000000) #define SET_I2CM_RDAT(_VAL_) SET_REG(ADR_I2CM_RDAT,_VAL_,0,0x00000000) #define SET_I2CM_SR_LEN(_VAL_) SET_REG(ADR_I2CM_EN_2,_VAL_,0,0xffff0000) #define SET_I2CM_SR_RX(_VAL_) SET_REG(ADR_I2CM_EN_2,_VAL_,16,0xfffeffff) #define SET_I2CM_REPEAT_START(_VAL_) SET_REG(ADR_I2CM_EN_2,_VAL_,17,0xfffdffff) #define SET_I2CM_STA_STO_PSCL(_VAL_) SET_REG(ADR_I2CM_START_STOP_PERIOD,_VAL_,0,0xfffffc00) #define SET_UART_DATA(_VAL_) SET_REG(ADR_UART_DATA,_VAL_,0,0xffffff00) #define SET_DATA_RDY_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,0,0xfffffffe) #define SET_THR_EMPTY_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,1,0xfffffffd) #define SET_RX_LINESTS_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,2,0xfffffffb) #define SET_MDM_STS_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,3,0xfffffff7) #define SET_TX_THRH_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,4,0xffffffef) #define SET_TX_THRL_IE(_VAL_) SET_REG(ADR_UART_IER,_VAL_,5,0xffffffdf) #define SET_FIFO_EN(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,0,0xfffffffe) #define SET_RXFIFO_RST(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,1,0xfffffffd) #define SET_TXFIFO_RST(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,2,0xfffffffb) #define SET_DMA_MODE(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,3,0xfffffff7) #define SET_EN_AUTO_RTS(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,4,0xffffffef) #define SET_EN_AUTO_CTS(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,5,0xffffffdf) #define SET_RXFIFO_TRGLVL(_VAL_) SET_REG(ADR_UART_FCR,_VAL_,6,0xffffff3f) #define SET_WORD_LEN(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,0,0xfffffffc) #define SET_STOP_BIT(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,2,0xfffffffb) #define SET_PARITY_EN(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,3,0xfffffff7) #define SET_EVEN_PARITY(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,4,0xffffffef) #define SET_FORCE_PARITY(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,5,0xffffffdf) #define SET_SET_BREAK(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,6,0xffffffbf) #define SET_DLAB(_VAL_) SET_REG(ADR_UART_LCR,_VAL_,7,0xffffff7f) #define SET_DTR(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,0,0xfffffffe) #define SET_RTS(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,1,0xfffffffd) #define SET_OUT_1(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,2,0xfffffffb) #define SET_OUT_2(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,3,0xfffffff7) #define SET_LOOP_BACK(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,4,0xffffffef) #define SET_DE_RTS(_VAL_) SET_REG(ADR_UART_MCR,_VAL_,5,0xffffffdf) #define SET_DATA_RDY(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,0,0xfffffffe) #define SET_OVERRUN_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,1,0xfffffffd) #define SET_PARITY_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,2,0xfffffffb) #define SET_FRAMING_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,3,0xfffffff7) #define SET_BREAK_INT(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,4,0xffffffef) #define SET_THR_EMPTY(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,5,0xffffffdf) #define SET_TX_EMPTY(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,6,0xffffffbf) #define SET_FIFODATA_ERR(_VAL_) SET_REG(ADR_UART_LSR,_VAL_,7,0xffffff7f) #define SET_DELTA_CTS(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,0,0xfffffffe) #define SET_DELTA_DSR(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,1,0xfffffffd) #define SET_TRAILEDGE_RI(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,2,0xfffffffb) #define SET_DELTA_CD(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,3,0xfffffff7) #define SET_CTS(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,4,0xffffffef) #define SET_DSR(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,5,0xffffffdf) #define SET_RI(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,6,0xffffffbf) #define SET_CD(_VAL_) SET_REG(ADR_UART_MSR,_VAL_,7,0xffffff7f) #define SET_BRDC_DIV(_VAL_) SET_REG(ADR_UART_SPR,_VAL_,0,0xffff0000) #define SET_RTHR_L(_VAL_) SET_REG(ADR_UART_RTHR,_VAL_,0,0xfffffff0) #define SET_RTHR_H(_VAL_) SET_REG(ADR_UART_RTHR,_VAL_,4,0xffffff0f) #define SET_INT_IDCODE(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,0,0xfffffff0) #define SET_RX_IDLE(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,4,0xffffffef) #define SET_TX_IDLE(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,5,0xffffffdf) #define SET_FIFOS_ENABLED(_VAL_) SET_REG(ADR_UART_ISR,_VAL_,6,0xffffff3f) #define SET_TTHR_L(_VAL_) SET_REG(ADR_UART_TTHR,_VAL_,0,0xfffffff0) #define SET_TTHR_H(_VAL_) SET_REG(ADR_UART_TTHR,_VAL_,4,0xffffff0f) #define SET_RX_RECIEVED(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,0,0xfffffffe) #define SET_RX_FIFO_TO(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,1,0xfffffffd) #define SET_TX_L(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,2,0xfffffffb) #define SET_TX_H(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,3,0xfffffff7) #define SET_TX_EMPTY2(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,4,0xffffffef) #define SET_OVERRUN(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,5,0xffffffdf) #define SET_FRAMING(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,6,0xffffffbf) #define SET_BREAK(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,7,0xffffff7f) #define SET_PARITY(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,8,0xfffffeff) #define SET_MODEN_INT(_VAL_) SET_REG(ADR_UART_INT_MAP,_VAL_,9,0xfffffdff) #define SET_ROP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,0,0xfffffff0) #define SET_RIP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,4,0xffffff0f) #define SET_TOP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,8,0xfffff0ff) #define SET_TIP_A(_VAL_) SET_REG(ADR_UART_POINTER,_VAL_,12,0xffff0fff) #define SET_HSUART_RXD(_VAL_) SET_REG(ADR_HSUART_TRX_CHAR,_VAL_,0,0xffffff00) #define SET_HSUART_ENABRXBUFF(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,0,0xfffffffe) #define SET_HSUART_ENABTXBUFF(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,1,0xfffffffd) #define SET_HSUART_ENABLNSTAT(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,2,0xfffffffb) #define SET_HSUART_ENABMDSTAT(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,3,0xfffffff7) #define SET_HSUART_ENABCTXTHR(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,4,0xffffffef) #define SET_HSUART_ENABDMARXEND(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,6,0xffffffbf) #define SET_HSUART_ENABDMATXEND(_VAL_) SET_REG(ADR_HSUART_INTRRUPT_ENABLE,_VAL_,7,0xffffff7f) #define SET_HSUART_FIFOE(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,0,0xfffffffe) #define SET_HSUART_RX_FIFO_RST(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,1,0xfffffffd) #define SET_HSUART_TX_FIFO_RST(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,2,0xfffffffb) #define SET_HSUART_DMA(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,3,0xfffffff7) #define SET_HSUART_RX_TRIG_LV(_VAL_) SET_REG(ADR_HSUART_FIFO_CTRL,_VAL_,6,0xffffff3f) #define SET_HSUART_WLS(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,0,0xfffffffc) #define SET_HSUART_STB(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,2,0xfffffffb) #define SET_HSUART_PEN(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,3,0xfffffff7) #define SET_HSUART_SP_EPS(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,4,0xffffffcf) #define SET_HSUART_SB(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,6,0xffffffbf) #define SET_HSUART_DLAB(_VAL_) SET_REG(ADR_HSUART_LINE_CTRL,_VAL_,7,0xffffff7f) #define SET_HSUART_DTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,0,0xfffffffe) #define SET_HSUART_RTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,1,0xfffffffd) #define SET_HSUART_OUT1(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,2,0xfffffffb) #define SET_HSUART_OUT2(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,3,0xfffffff7) #define SET_HSUART_LOOP1(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,4,0xffffffef) #define SET_HSUART_ARTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,6,0xffffffbf) #define SET_HSUART_ACTS(_VAL_) SET_REG(ADR_HSUART_MODEM_CTRL,_VAL_,7,0xffffff7f) #define SET_HSUART_DR(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,0,0xfffffffe) #define SET_HSUART_OE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,1,0xfffffffd) #define SET_HSUART_PE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,2,0xfffffffb) #define SET_HSUART_FE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,3,0xfffffff7) #define SET_HSUART_BI(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,4,0xffffffef) #define SET_HSUART_THRE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,5,0xffffffdf) #define SET_HSUART_TSRE(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,6,0xffffffbf) #define SET_HSUART_ERF(_VAL_) SET_REG(ADR_HSUART_LINE_STATUS,_VAL_,7,0xffffff7f) #define SET_HSUART_DCTS(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,0,0xfffffffe) #define SET_HSUART_DDSR(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,1,0xfffffffd) #define SET_HSUART_TERI(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,2,0xfffffffb) #define SET_HSUART_DDCD(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,3,0xfffffff7) #define SET_HSUART_CTS(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,4,0xffffffef) #define SET_HSUART_DSR(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,5,0xffffffdf) #define SET_HSUART_RI(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,6,0xffffffbf) #define SET_HSUART_DCR(_VAL_) SET_REG(ADR_HSUART_MODEM_STATUS,_VAL_,7,0xffffff7f) #define SET_HSUART_SCR(_VAL_) SET_REG(ADR_HSUART_SCRATCH_BOARD,_VAL_,0,0xffffff00) #define SET_HSUART_RTS_AUTO_TH_L(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,0,0xffffffe0) #define SET_HSUART_RTS_AUTO_TH_H(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,8,0xffffe0ff) #define SET_HSUART_TX_THR_L(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,16,0xffe0ffff) #define SET_HSUART_TX_THR_H(_VAL_) SET_REG(ADR_HSUART_FIFO_THRESHOLD,_VAL_,24,0xe0ffffff) #define SET_HSUART_IIR(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,0,0xfffffff0) #define SET_HSUART_TXDMA_DONE(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,5,0xffffffdf) #define SET_HSUART_IFOFOE0(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,6,0xffffffbf) #define SET_HSUART_IFIFOE1(_VAL_) SET_REG(ADR_HSUART_INTERRUPT_STATUS,_VAL_,7,0xffffff7f) #define SET_HSUART_DIV(_VAL_) SET_REG(ADR_HSUART_DIV_FRAC,_VAL_,0,0xffff0000) #define SET_HSUART_FRAC(_VAL_) SET_REG(ADR_HSUART_DIV_FRAC,_VAL_,16,0xff00ffff) #define SET_HSUART_INT(_VAL_) SET_REG(ADR_HSUART_EXPANSION_INTERRUPT_STATUS,_VAL_,0,0xffff0000) #define SET_HSUART_DMA_RX_STR_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_RX_STR_ADDR,_VAL_,0,0x00000000) #define SET_HSUART_DMA_RX_END_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_RX_END_ADDR,_VAL_,0,0x00000000) #define SET_HSUART_DMA_RX_WPT(_VAL_) SET_REG(ADR_HSUART_DMA_RX_WPT,_VAL_,0,0x00000000) #define SET_HSUART_DMA_RX_RPT(_VAL_) SET_REG(ADR_HSUART_DMA_RX_RPT,_VAL_,0,0x00000000) #define SET_HSUART_DMA_TX_STR_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_TX_STR_ADDR,_VAL_,0,0x00000000) #define SET_HSUART_DMA_TX_END_ADDR(_VAL_) SET_REG(ADR_HSUART_DMA_TX_END_ADDR,_VAL_,0,0x00000000) #define SET_HSUART_DMA_TX_WPT(_VAL_) SET_REG(ADR_HSUART_DMA_TX_WPT,_VAL_,0,0x00000000) #define SET_HSUART_DMA_TX_RPT(_VAL_) SET_REG(ADR_HSUART_DMA_TX_RPT,_VAL_,0,0x00000000) #define SET_MANUAL_T_ADDR(_VAL_) SET_REG(ADR_MANUAL_MODE_TX_ADDR,_VAL_,0,0x00000000) #define SET_MANUAL_R_ADDR(_VAL_) SET_REG(ADR_MANUAL_MODE_RX_ADDR,_VAL_,0,0x00000000) #define SET_FLASH_FRONT_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,0,0xfffffff0) #define SET_FLASH_BACK_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,4,0xffffff0f) #define SET_CSN_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,8,0xfffff0ff) #define SET_INDICATOR(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,12,0xfff00fff) #define SET_DUMY_DLY(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,20,0xff0fffff) #define SET_MEM_SEL(_VAL_) SET_REG(ADR_SPI_PARAM,_VAL_,24,0xfeffffff) #define SET_SPI_BUSY(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,0,0xfffffffe) #define SET_SPI_FLASH_MODE(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,1,0xfffffff9) #define SET_MANUAL_MODE_BUSY(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,3,0xfffffff7) #define SET_PREFETCH_EN(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,4,0xffffffef) #define SET_WRAP_EN(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,5,0xffffffdf) #define SET_CONTINUE_R_EN(_VAL_) SET_REG(ADR_SPI_PARAM2,_VAL_,6,0xffffffbf) #define SET_MANUAL_T_LEN(_VAL_) SET_REG(ADR_SPI_TX_LEN,_VAL_,0,0xffff0000) #define SET_MANUAL_R_LEN(_VAL_) SET_REG(ADR_SPI_RX_LEN,_VAL_,0,0xffff0000) #define SET_BIT1_WR_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,0,0xffffff00) #define SET_BIT1_RD_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,8,0xffff00ff) #define SET_BIT2_RD_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,16,0xff00ffff) #define SET_BIT4_RD_CMD(_VAL_) SET_REG(ADR_CMD_SET,_VAL_,24,0x00ffffff) #define SET_BIT4_WR_CMD(_VAL_) SET_REG(ADR_CMD_SET_1,_VAL_,0,0xffffff00) #define SET_FLS_CLK_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,0,0xfffffff8) #define SET_FLS_CLK_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,4,0xffffff8f) #define SET_FLS_MOSI_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,8,0xfffff8ff) #define SET_FLS_MOSI_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,12,0xffff8fff) #define SET_FLS_MISO_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,16,0xfff8ffff) #define SET_FLS_MISO_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,20,0xff8fffff) #define SET_FLS_WP_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,24,0xf8ffffff) #define SET_FLS_WP_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO0_DLY,_VAL_,28,0x8fffffff) #define SET_FLS_NC_IN_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO1_DLY,_VAL_,0,0xfffffff8) #define SET_FLS_NC_OUT_DLY_SEL(_VAL_) SET_REG(ADR_FLASH_IO1_DLY,_VAL_,4,0xffffff8f) #define SET_SPI_F_MISO_CLK_SEL(_VAL_) SET_REG(ADR_FLASH_IO1_DLY,_VAL_,8,0xfffffeff) #define SET_INS_START_ADDR(_VAL_) SET_REG(ADR_INS_SPACE_START_ADDR,_VAL_,0,0xff000000) #define SET_INS_END_ADDR(_VAL_) SET_REG(ADR_INS_SPACE_END_ADDR,_VAL_,0,0xff000000) #define SET_INS_BUF_CLR(_VAL_) SET_REG(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR,_VAL_,0,0xfffffffe) #define SET_RW_BUF_CLR(_VAL_) SET_REG(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR,_VAL_,1,0xfffffffd) #define SET_ERR_FLAG_CLR(_VAL_) SET_REG(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR,_VAL_,2,0xfffffffb) #define SET_DMA_ADR_SRC(_VAL_) SET_REG(ADR_DMA_ADR_SRC,_VAL_,0,0x00000000) #define SET_DMA_ADR_DST(_VAL_) SET_REG(ADR_DMA_ADR_DST,_VAL_,0,0x00000000) #define SET_DMA_SRC_SIZE(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,0,0xfffffff8) #define SET_DMA_SRC_INC(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,3,0xfffffff7) #define SET_DMA_DST_SIZE(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,4,0xffffff8f) #define SET_DMA_DST_INC(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,7,0xffffff7f) #define SET_DMA_FAST_FILL(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,8,0xfffffeff) #define SET_DMA_SDIO_KICK(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,12,0xffffefff) #define SET_DMA_BADR_EN(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,13,0xffffdfff) #define SET_DMA_LEN(_VAL_) SET_REG(ADR_DMA_CTRL,_VAL_,16,0x0000ffff) #define SET_DMA_INT_MASK(_VAL_) SET_REG(ADR_DMA_INT,_VAL_,0,0xfffffffe) #define SET_DMA_STS(_VAL_) SET_REG(ADR_DMA_INT,_VAL_,8,0xfffffeff) #define SET_DMA_FINISH(_VAL_) SET_REG(ADR_DMA_INT,_VAL_,31,0x7fffffff) #define SET_DMA_CONST(_VAL_) SET_REG(ADR_DMA_FILL_CONST,_VAL_,0,0x00000000) #define SET_D2_DMA_ADR_SRC(_VAL_) SET_REG(ADR_D2_DMA_ADR_SRC,_VAL_,0,0x00000000) #define SET_D2_DMA_ADR_DST(_VAL_) SET_REG(ADR_D2_DMA_ADR_DST,_VAL_,0,0x00000000) #define SET_D2_DMA_SRC_SIZE(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,0,0xfffffff8) #define SET_D2_DMA_SRC_INC(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,3,0xfffffff7) #define SET_D2_DMA_DST_SIZE(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,4,0xffffff8f) #define SET_D2_DMA_DST_INC(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,7,0xffffff7f) #define SET_D2_DMA_FAST_FILL(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,8,0xfffffeff) #define SET_D2_DMA_SDIO_KICK(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,12,0xffffefff) #define SET_D2_DMA_BADR_EN(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,13,0xffffdfff) #define SET_D2_DMA_LEN(_VAL_) SET_REG(ADR_D2_DMA_CTRL,_VAL_,16,0x0000ffff) #define SET_D2_DMA_INT_MASK(_VAL_) SET_REG(ADR_D2_DMA_INT,_VAL_,0,0xfffffffe) #define SET_D2_DMA_STS(_VAL_) SET_REG(ADR_D2_DMA_INT,_VAL_,8,0xfffffeff) #define SET_D2_DMA_FINISH(_VAL_) SET_REG(ADR_D2_DMA_INT,_VAL_,31,0x7fffffff) #define SET_D2_DMA_CONST(_VAL_) SET_REG(ADR_D2_DMA_FILL_CONST,_VAL_,0,0x00000000) #define SET_MASK_TYPHOST_INT_MAP_02(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP_02,_VAL_,0,0x00000000) #define SET_RAW_TYPHOST_INT_MAP_02(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP_02,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPHOST_INT_MAP_02(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP_02,_VAL_,0,0x00000000) #define SET_MASK_TYPHOST_INT_MAP_15(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP_15,_VAL_,0,0x00000000) #define SET_RAW_TYPHOST_INT_MAP_15(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP_15,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPHOST_INT_MAP_15(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP_15,_VAL_,0,0x00000000) #define SET_MASK_TYPHOST_INT_MAP_31(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP_31,_VAL_,0,0x00000000) #define SET_RAW_TYPHOST_INT_MAP_31(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP_31,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPHOST_INT_MAP_31(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP_31,_VAL_,0,0x00000000) #define SET_MASK_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_MASK_TYPHOST_INT_MAP,_VAL_,0,0x00000000) #define SET_RAW_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_RAW_TYPHOST_INT_MAP,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_POSTMASK_TYPHOST_INT_MAP,_VAL_,0,0x00000000) #define SET_SUMMARY_TYPHOST_INT_MAP(_VAL_) SET_REG(ADR_SUMMARY_TYPHOST_INT_MAP,_VAL_,0,0xfffffffe) #define SET_MASK_TYPMCU_INT_MAP_02(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP_02,_VAL_,0,0x00000000) #define SET_RAW_TYPMCU_INT_MAP_02(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP_02,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPMCU_INT_MAP_02(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP_02,_VAL_,0,0x00000000) #define SET_MASK_TYPMCU_INT_MAP_15(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP_15,_VAL_,0,0x00000000) #define SET_RAW_TYPMCU_INT_MAP_15(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP_15,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPMCU_INT_MAP_15(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP_15,_VAL_,0,0x00000000) #define SET_MASK_TYPMCU_INT_MAP_31(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP_31,_VAL_,0,0x00000000) #define SET_RAW_TYPMCU_INT_MAP_31(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP_31,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPMCU_INT_MAP_31(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP_31,_VAL_,0,0x00000000) #define SET_MASK_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_MASK_TYPMCU_INT_MAP,_VAL_,0,0x00000000) #define SET_RAW_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_RAW_TYPMCU_INT_MAP,_VAL_,0,0x00000000) #define SET_POSTMASK_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_POSTMASK_TYPMCU_INT_MAP,_VAL_,0,0x00000000) #define SET_SUMMARY_TYPMCU_INT_MAP(_VAL_) SET_REG(ADR_SUMMARY_TYPMCU_INT_MAP,_VAL_,0,0xfffffffe) #define SET_INT_GPI_SUB_00(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,0,0xfffffff0) #define SET_INT_GPI_SUB_01(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,4,0xffffff0f) #define SET_INT_GPI_SUB_02(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,8,0xfffff0ff) #define SET_INT_GPI_SUB_03(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,12,0xffff0fff) #define SET_INT_GPI_SUB_04(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,16,0xfff0ffff) #define SET_INT_GPI_SUB_05(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,20,0xff0fffff) #define SET_INT_GPI_SUB_06(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,24,0xf0ffffff) #define SET_INT_GPI_SUB_07(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_00_TO_07,_VAL_,28,0x0fffffff) #define SET_INT_GPI_SUB_08(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,0,0xfffffff0) #define SET_INT_GPI_SUB_09(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,4,0xffffff0f) #define SET_INT_GPI_SUB_10(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,8,0xfffff0ff) #define SET_INT_GPI_SUB_11(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,12,0xffff0fff) #define SET_INT_GPI_SUB_12(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,16,0xfff0ffff) #define SET_INT_GPI_SUB_13(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,20,0xff0fffff) #define SET_INT_GPI_SUB_14(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,24,0xf0ffffff) #define SET_INT_GPI_SUB_15(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_08_TO_15,_VAL_,28,0x0fffffff) #define SET_INT_GPI_SUB_16(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,0,0xfffffff0) #define SET_INT_GPI_SUB_17(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,4,0xffffff0f) #define SET_INT_GPI_SUB_18(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,8,0xfffff0ff) #define SET_INT_GPI_SUB_19(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,12,0xffff0fff) #define SET_INT_GPI_SUB_20(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,16,0xfff0ffff) #define SET_INT_GPI_SUB_21(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,20,0xff0fffff) #define SET_INT_GPI_SUB_22(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_BANK_16_TO_22,_VAL_,24,0xf0ffffff) #define SET_INT_GPI_MODE_00(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,0,0xfffffff8) #define SET_INT_GPI_MODE_01(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,4,0xffffff8f) #define SET_INT_GPI_MODE_02(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,8,0xfffff8ff) #define SET_INT_GPI_MODE_03(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,12,0xffff8fff) #define SET_INT_GPI_MODE_04(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,16,0xfff8ffff) #define SET_INT_GPI_MODE_05(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,20,0xff8fffff) #define SET_INT_GPI_MODE_06(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,24,0xf8ffffff) #define SET_INT_GPI_MODE_07(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_00_TO_07,_VAL_,28,0x8fffffff) #define SET_INT_GPI_MODE_08(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,0,0xfffffff8) #define SET_INT_GPI_MODE_09(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,4,0xffffff8f) #define SET_INT_GPI_MODE_10(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,8,0xfffff8ff) #define SET_INT_GPI_MODE_11(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,12,0xffff8fff) #define SET_INT_GPI_MODE_12(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,16,0xfff8ffff) #define SET_INT_GPI_MODE_13(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,20,0xff8fffff) #define SET_INT_GPI_MODE_14(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,24,0xf8ffffff) #define SET_INT_GPI_MODE_15(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_08_TO_15,_VAL_,28,0x8fffffff) #define SET_INT_GPI_MODE_16(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,0,0xfffffff8) #define SET_INT_GPI_MODE_17(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,4,0xffffff8f) #define SET_INT_GPI_MODE_18(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,8,0xfffff8ff) #define SET_INT_GPI_MODE_19(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,12,0xffff8fff) #define SET_INT_GPI_MODE_20(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,16,0xfff8ffff) #define SET_INT_GPI_MODE_21(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,20,0xff8fffff) #define SET_INT_GPI_MODE_22(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,24,0xf8ffffff) #define SET_GPO_INT_POL(_VAL_) SET_REG(ADR_GPIO_INTERRUPT_MODE_16_TO_22,_VAL_,31,0x7fffffff) #define SET_INT_IPC_RAW(_VAL_) SET_REG(ADR_IPC_INTERRUPT,_VAL_,0,0x00000000) #define SET_INT_WIFI_PHY(_VAL_) SET_REG(ADR_CLR_INT_STS2,_VAL_,23,0xff7fffff) #define SET_INT_UART_DBG_RX_TOUT(_VAL_) SET_REG(ADR_CLR_INT_STS2,_VAL_,26,0xfbffffff) #define SET_INT_UART_DATA_RX_TOUT(_VAL_) SET_REG(ADR_CLR_INT_STS2,_VAL_,30,0xbfffffff) #define SET_INT_ALC_TIMEOUT(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,8,0xfffffeff) #define SET_INT_REQ_LOCK(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,9,0xfffffdff) #define SET_INT_TX_LIMIT(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,10,0xfffffbff) #define SET_INT_ID_THOLD_RX(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,11,0xfffff7ff) #define SET_INT_ID_THOLD_TX(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,12,0xffffefff) #define SET_INT_ID_DOUBLE_RLS(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,13,0xffffdfff) #define SET_INT_RX_ID_LEN_THOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,14,0xffffbfff) #define SET_INT_TX_ID_LEN_THOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,15,0xffff7fff) #define SET_INT_ALL_ID_LEN_THOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,16,0xfffeffff) #define SET_INT_TRASH_CAN(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,17,0xfffdffff) #define SET_INT_MB_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,18,0xfffbffff) #define SET_INT_EDCA0_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,20,0xffefffff) #define SET_INT_EDCA1_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,21,0xffdfffff) #define SET_INT_EDCA2_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,22,0xffbfffff) #define SET_INT_EDCA3_LOWTHOLD(_VAL_) SET_REG(ADR_CLR_INT_STS1,_VAL_,23,0xff7fffff) #define SET_INT_SDIO_WAKE(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,2,0xfffffffb) #define SET_INT_SPI_M_DONE(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,3,0xfffffff7) #define SET_INT_FLASH_DMA_DONE(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,6,0xffffffbf) #define SET_INT_FBUSDMAC_INT_COMBINED(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,9,0xfffffdff) #define SET_INT_DMAC_INT_COMBINED(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,10,0xfffffbff) #define SET_INT_I2S(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,16,0xfffeffff) #define SET_INT_CPU_ALT(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,18,0xfffbffff) #define SET_INT_CPU(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,19,0xfff7ffff) #define SET_INT_US_TIMER_0(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,20,0xffefffff) #define SET_INT_US_TIMER_1(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,21,0xffdfffff) #define SET_INT_US_TIMER_2(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,22,0xffbfffff) #define SET_INT_US_TIMER_3(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,23,0xff7fffff) #define SET_INT_MS_TIMER_0(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,24,0xfeffffff) #define SET_INT_MS_TIMER_1(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,25,0xfdffffff) #define SET_INT_MS_TIMER_2(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,26,0xfbffffff) #define SET_INT_MS_TIMER_3(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,27,0xf7ffffff) #define SET_INT_I2CMST(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,28,0xefffffff) #define SET_INT_HCI(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,29,0xdfffffff) #define SET_INT_CO_DMA(_VAL_) SET_REG(ADR_CLR_INT_STS0,_VAL_,30,0xbfffffff) #define SET_PATCH02_EN(_VAL_) SET_REG(ADR_ROM_PATCH02_0,_VAL_,0,0xfffffffe) #define SET_PATCH02_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH02_0,_VAL_,2,0xfffe0003) #define SET_PATCH02_DATA(_VAL_) SET_REG(ADR_ROM_PATCH02_1,_VAL_,0,0x00000000) #define SET_PATCH03_EN(_VAL_) SET_REG(ADR_ROM_PATCH03_0,_VAL_,0,0xfffffffe) #define SET_PATCH03_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH03_0,_VAL_,2,0xfffe0003) #define SET_PATCH03_DATA(_VAL_) SET_REG(ADR_ROM_PATCH03_1,_VAL_,0,0x00000000) #define SET_PATCH04_EN(_VAL_) SET_REG(ADR_ROM_PATCH04_0,_VAL_,0,0xfffffffe) #define SET_PATCH04_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH04_0,_VAL_,2,0xfffe0003) #define SET_PATCH04_DATA(_VAL_) SET_REG(ADR_ROM_PATCH04_1,_VAL_,0,0x00000000) #define SET_PATCH05_EN(_VAL_) SET_REG(ADR_ROM_PATCH05_0,_VAL_,0,0xfffffffe) #define SET_PATCH05_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH05_0,_VAL_,2,0xfffe0003) #define SET_PATCH05_DATA(_VAL_) SET_REG(ADR_ROM_PATCH05_1,_VAL_,0,0x00000000) #define SET_PATCH06_EN(_VAL_) SET_REG(ADR_ROM_PATCH06_0,_VAL_,0,0xfffffffe) #define SET_PATCH06_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH06_0,_VAL_,2,0xfffe0003) #define SET_PATCH06_DATA(_VAL_) SET_REG(ADR_ROM_PATCH06_1,_VAL_,0,0x00000000) #define SET_PATCH07_EN(_VAL_) SET_REG(ADR_ROM_PATCH07_0,_VAL_,0,0xfffffffe) #define SET_PATCH07_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH07_0,_VAL_,2,0xfffe0003) #define SET_PATCH07_DATA(_VAL_) SET_REG(ADR_ROM_PATCH07_1,_VAL_,0,0x00000000) #define SET_PATCH08_EN(_VAL_) SET_REG(ADR_ROM_PATCH08_0,_VAL_,0,0xfffffffe) #define SET_PATCH08_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH08_0,_VAL_,2,0xfffe0003) #define SET_PATCH08_DATA(_VAL_) SET_REG(ADR_ROM_PATCH08_1,_VAL_,0,0x00000000) #define SET_PATCH09_EN(_VAL_) SET_REG(ADR_ROM_PATCH09_0,_VAL_,0,0xfffffffe) #define SET_PATCH09_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH09_0,_VAL_,2,0xfffe0003) #define SET_PATCH09_DATA(_VAL_) SET_REG(ADR_ROM_PATCH09_1,_VAL_,0,0x00000000) #define SET_PATCH10_EN(_VAL_) SET_REG(ADR_ROM_PATCH10_0,_VAL_,0,0xfffffffe) #define SET_PATCH10_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH10_0,_VAL_,2,0xfffe0003) #define SET_PATCH10_DATA(_VAL_) SET_REG(ADR_ROM_PATCH10_1,_VAL_,0,0x00000000) #define SET_PATCH11_EN(_VAL_) SET_REG(ADR_ROM_PATCH11_0,_VAL_,0,0xfffffffe) #define SET_PATCH11_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH11_0,_VAL_,2,0xfffe0003) #define SET_PATCH11_DATA(_VAL_) SET_REG(ADR_ROM_PATCH11_1,_VAL_,0,0x00000000) #define SET_PATCH12_EN(_VAL_) SET_REG(ADR_ROM_PATCH12_0,_VAL_,0,0xfffffffe) #define SET_PATCH12_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH12_0,_VAL_,2,0xfffe0003) #define SET_PATCH12_DATA(_VAL_) SET_REG(ADR_ROM_PATCH12_1,_VAL_,0,0x00000000) #define SET_PATCH13_EN(_VAL_) SET_REG(ADR_ROM_PATCH13_0,_VAL_,0,0xfffffffe) #define SET_PATCH13_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH13_0,_VAL_,2,0xfffe0003) #define SET_PATCH13_DATA(_VAL_) SET_REG(ADR_ROM_PATCH13_1,_VAL_,0,0x00000000) #define SET_PATCH14_EN(_VAL_) SET_REG(ADR_ROM_PATCH14_0,_VAL_,0,0xfffffffe) #define SET_PATCH14_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH14_0,_VAL_,2,0xfffe0003) #define SET_PATCH14_DATA(_VAL_) SET_REG(ADR_ROM_PATCH14_1,_VAL_,0,0x00000000) #define SET_PATCH15_EN(_VAL_) SET_REG(ADR_ROM_PATCH15_0,_VAL_,0,0xfffffffe) #define SET_PATCH15_ADDR(_VAL_) SET_REG(ADR_ROM_PATCH15_0,_VAL_,2,0xfffe0003) #define SET_PATCH15_DATA(_VAL_) SET_REG(ADR_ROM_PATCH15_1,_VAL_,0,0x00000000) #define SET_INT_BROWNOUT_LOWBATTERY(_VAL_) SET_REG(ADR_BROWNOUT_INT,_VAL_,0,0xfffffffe) #define SET_LOWBATTERY_SAMPLE_MIN_COUNT(_VAL_) SET_REG(ADR_BROWNOUT_SETUP,_VAL_,0,0xfffffff0) #define SET_TX_ON_DEMAND_ENA(_VAL_) SET_REG(ADR_CONTROL,_VAL_,1,0xfffffffd) #define SET_RX_2_HOST(_VAL_) SET_REG(ADR_CONTROL,_VAL_,2,0xfffffffb) #define SET_AUTO_SEQNO(_VAL_) SET_REG(ADR_CONTROL,_VAL_,3,0xfffffff7) #define SET_BYPASS_TX_PARSER_ENCAP(_VAL_) SET_REG(ADR_CONTROL,_VAL_,4,0xffffffef) #define SET_HDR_STRIP(_VAL_) SET_REG(ADR_CONTROL,_VAL_,5,0xffffffdf) #define SET_ERP_PROTECT(_VAL_) SET_REG(ADR_CONTROL,_VAL_,6,0xffffff3f) #define SET_PRO_VER(_VAL_) SET_REG(ADR_CONTROL,_VAL_,8,0xfffffcff) #define SET_TXQ_ID0(_VAL_) SET_REG(ADR_CONTROL,_VAL_,12,0xffff8fff) #define SET_TXQ_ID1(_VAL_) SET_REG(ADR_CONTROL,_VAL_,16,0xfff8ffff) #define SET_TX_ETHER_TRAP_EN(_VAL_) SET_REG(ADR_CONTROL,_VAL_,20,0xffefffff) #define SET_RX_ETHER_TRAP_EN(_VAL_) SET_REG(ADR_CONTROL,_VAL_,21,0xffdfffff) #define SET_RX_NULL_TRAP_EN(_VAL_) SET_REG(ADR_CONTROL,_VAL_,22,0xffbfffff) #define SET_TRX_DEBUG_CNT_ENA(_VAL_) SET_REG(ADR_CONTROL,_VAL_,28,0xefffffff) #define SET_HCI_TX_AGG_EN(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,0,0xfffffffe) #define SET_HCI_RX_EN(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,1,0xfffffffd) #define SET_HCI_RX_FORM_1(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,30,0xbfffffff) #define SET_HCI_RX_FORM_0(_VAL_) SET_REG(ADR_HCI_TRX_MODE,_VAL_,31,0x7fffffff) #define SET_TX_FLOW_CTRL(_VAL_) SET_REG(ADR_TX_FLOW_0,_VAL_,0,0xffff0000) #define SET_TX_FLOW_MGMT(_VAL_) SET_REG(ADR_TX_FLOW_0,_VAL_,16,0x0000ffff) #define SET_TX_FLOW_DATA(_VAL_) SET_REG(ADR_TX_FLOW_1,_VAL_,0,0x00000000) #define SET_SD_RX_LEN(_VAL_) SET_REG(ADR_REMAINING_RX_PACKET_LENGTH,_VAL_,0,0xffff0000) #define SET_RX_ACCU_LEN(_VAL_) SET_REG(ADR_RX_PACKET_LENGTH_STATUS,_VAL_,0,0xffff0000) #define SET_HCI_RX_LEN(_VAL_) SET_REG(ADR_RX_PACKET_LENGTH_STATUS,_VAL_,16,0x0000ffff) #define SET_DOT11RTSTHRESHOLD(_VAL_) SET_REG(ADR_THRESHOLD,_VAL_,16,0x0000ffff) #define SET_TX_ERR_RECOVER(_VAL_) SET_REG(ADR_TX_ERROR_RECEOVERY,_VAL_,0,0xfffffffe) #define SET_TX_ERR_FIRST_4B_EN(_VAL_) SET_REG(ADR_TX_ERROR_RECEOVERY,_VAL_,1,0xfffffffd) #define SET_RX_INT_TIMEOUT(_VAL_) SET_REG(ADR_TX_ERROR_RECEOVERY,_VAL_,16,0x0000ffff) #define SET_TXF_ID(_VAL_) SET_REG(ADR_TXFID_INCREASE,_VAL_,0,0xffffffc0) #define SET_SEQ_CTRL(_VAL_) SET_REG(ADR_GLOBAL_SEQUENCE,_VAL_,0,0xffff0000) #define SET_DBG_ADDR_EN(_VAL_) SET_REG(ADR_HCI_REG_0X2C,_VAL_,0,0xfffffffe) #define SET_DBG_ADDR_FENCE(_VAL_) SET_REG(ADR_HCI_REG_0X2C,_VAL_,8,0xffff00ff) #define SET_TX_PBOFFSET(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,0,0xffffff00) #define SET_TX_INFO_SIZE(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,8,0xffff00ff) #define SET_RX_INFO_SIZE(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,16,0xff00ffff) #define SET_RX_LAST_PHY_SIZE(_VAL_) SET_REG(ADR_HCI_TX_RX_INFO_SIZE,_VAL_,24,0x00ffffff) #define SET_TX_INFO_CLEAR_SIZE(_VAL_) SET_REG(ADR_HCI_TX_INFO_CLEAR,_VAL_,0,0xffffffc0) #define SET_TX_INFO_CLEAR_ENABLE(_VAL_) SET_REG(ADR_HCI_TX_INFO_CLEAR,_VAL_,8,0xfffffeff) #define SET_RX_PER_RD_LEN(_VAL_) SET_REG(ADR_HCI_TO_PKTBUF_SETTING,_VAL_,0,0xffffffc0) #define SET_BACKUP_PG_CNT(_VAL_) SET_REG(ADR_HCI_TO_PKTBUF_SETTING,_VAL_,8,0xfffff0ff) #define SET_MANUAL_HCI_ALLOC_EN(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC,_VAL_,0,0xfffffffe) #define SET_MANUAL_HCI_ALLOC_SIZE(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_ACTION,_VAL_,0,0xffff0000) #define SET_MANUAL_ALLOC_ID(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,0,0xffffff80) #define SET_HAS_MANUAL_BUF(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,7,0xffffff7f) #define SET_DOUBLE_ALLOC_ERR(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,8,0xfffffeff) #define SET_NO_ALLOC_ERR(_VAL_) SET_REG(ADR_HCI_MANUAL_ALLOC_STATUS,_VAL_,9,0xfffffdff) #define SET_TXTRAP_ETHTYPE1(_VAL_) SET_REG(ADR_TX_ETHER_TYPE_1,_VAL_,0,0xffff0000) #define SET_TXTRAP_ETHTYPE0(_VAL_) SET_REG(ADR_TX_ETHER_TYPE_1,_VAL_,16,0x0000ffff) #define SET_RXTRAP_ETHTYPE1(_VAL_) SET_REG(ADR_RX_ETHER_TYPE_1,_VAL_,0,0xffff0000) #define SET_RXTRAP_ETHTYPE0(_VAL_) SET_REG(ADR_RX_ETHER_TYPE_1,_VAL_,16,0x0000ffff) #define SET_TX_PKT_SEND_LEN(_VAL_) SET_REG(ADR_TX_PACKET_LENGTH,_VAL_,0,0xffff0000) #define SET_TX_SDIO_PKT_LEN(_VAL_) SET_REG(ADR_TX_PACKET_LENGTH,_VAL_,16,0x0000ffff) #define SET_TX_PKT_SEND_ID(_VAL_) SET_REG(ADR_TX_PACKET_ID,_VAL_,0,0xffffff80) #define SET_HCI_PENDING_RX_MPDU_CNT(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,0,0xffffffe0) #define SET_HCI_RX_HALT(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,8,0xfffffeff) #define SET_HIF_LOOP_BACK(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,9,0xfffffdff) #define SET_USB_BULK_IN_LEN_INIT(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,30,0xbfffffff) #define SET_HCI_RX_MPDU_DEQUE(_VAL_) SET_REG(ADR_RX_RESCUE_HELPER,_VAL_,31,0x7fffffff) #define SET_HCI_BULK_IN_HOST_SIZE(_VAL_) SET_REG(ADR_HCI_FORCE_PRE_BULK_IN,_VAL_,0,0xfffe0000) #define SET_HCI_BULK_IN_TIME_OUT(_VAL_) SET_REG(ADR_HCI_BULK_IN_TIME_OUT_VALUE,_VAL_,0,0x00000000) #define SET_HCI_MONITOR_REG0(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_0,_VAL_,0,0x00000000) #define SET_HCI_MONITOR_REG2(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_2,_VAL_,0,0x00000000) #define SET_HCI_MONITOR_REG3(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_3,_VAL_,0,0x00000000) #define SET_HCI_MONITOR_REG4(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_4,_VAL_,0,0x00000000) #define SET_HCI_MONITOR_REG5(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_5,_VAL_,0,0x00000000) #define SET_SDIO_TX_INVALID_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_6,_VAL_,0,0x00000000) #define SET_HCI_MB_MAX_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_7,_VAL_,0,0xffffff00) #define SET_HCI_PROC_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_7,_VAL_,8,0xffff00ff) #define SET_SDIO_TRANS_CNT(_VAL_) SET_REG(ADR_HCI_STATE_DEBUG_MODE_7,_VAL_,16,0xff00ffff) #define SET_TX_ON_DEMAND_LENGTH(_VAL_) SET_REG(ADR_HCI_TX_ON_DEMAND_LENGTH,_VAL_,0,0x00000000) #define SET_HCI_TX_ALLOC_CNT(_VAL_) SET_REG(ADR_HCI_TX_ALLOC_SUCCESS_COUNT,_VAL_,0,0x00000000) #define SET_HCI_TX_ALLOC_TIME(_VAL_) SET_REG(ADR_HCI_TX_ALLOC_SPENDING_TIME,_VAL_,0,0x00000000) #define SET_RX_PKT_TRAP_COUNTER(_VAL_) SET_REG(ADR_RX_TRAP_COUNT,_VAL_,0,0x00000000) #define SET_TX_PKT_TRAP_COUNTER(_VAL_) SET_REG(ADR_TX_TRAP_COUNT,_VAL_,0,0x00000000) #define SET_RX_PKT_DROP_COUNTER(_VAL_) SET_REG(ADR_RX_DROP_COUNT,_VAL_,0,0x00000000) #define SET_TX_PKT_DROP_COUNTER(_VAL_) SET_REG(ADR_TX_DROP_COUNT,_VAL_,0,0x00000000) #define SET_HOST_EVENT_COUNTER(_VAL_) SET_REG(ADR_RX_HOST_EVENT_COUNT,_VAL_,0,0x00000000) #define SET_HOST_CMD_COUNTER(_VAL_) SET_REG(ADR_TX_HOST_COMMAND_COUNT,_VAL_,0,0x00000000) #define SET_RX_PKT_COUNTER(_VAL_) SET_REG(ADR_RX_PACKET_COUNTER,_VAL_,0,0x00000000) #define SET_TX_PKT_COUNTER(_VAL_) SET_REG(ADR_TX_PACKET_COUNTER,_VAL_,0,0x00000000) #define SET_HOST_RX_FAIL_COUNTER(_VAL_) SET_REG(ADR_SDIO_RX_FAIL_COUNT,_VAL_,0,0x00000000) #define SET_HOST_TX_FAIL_COUNTER(_VAL_) SET_REG(ADR_SDIO_TX_FAIL_COUNT,_VAL_,0,0x00000000) #define SET_CORRECT_RATE_REP_LEN(_VAL_) SET_REG(ADR_CORRECT_RATE_REPORT_LENGTH,_VAL_,0,0xfffffffe) #define SET_TX_PKT_SEND_TO_RX(_VAL_) SET_REG(ADR_TX_PACKET_SEND_TO_RX_DIRECTLY,_VAL_,0,0xfffffffe) #define SET_PEERPS_REJECT_ENABLE(_VAL_) SET_REG(ADR_POWER_SAVING_PEER_REJECT_FUNCTION,_VAL_,0,0xfffffffe) #define SET_TRANS_FULL_PKT_AMPDU1P2(_VAL_) SET_REG(ADR_POWER_SAVING_PEER_REJECT_FUNCTION,_VAL_,4,0xffffffef) #define SET_TX_RX_TRAP_HW_ID_SELECT_ENABLE(_VAL_) SET_REG(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION,_VAL_,0,0xfffffffe) #define SET_TX_TRAP_HW_ID(_VAL_) SET_REG(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION,_VAL_,4,0xffffff0f) #define SET_RX_TRAP_HW_ID(_VAL_) SET_REG(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION,_VAL_,8,0xfffff0ff) #define SET_RX_DEBUG_HCI_EXP_0(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_CTRL,_VAL_,0,0xfffffffe) #define SET_RX_DEBUG_HCI_EXP_0_RND_MODE(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_CTRL,_VAL_,4,0xffffffcf) #define SET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MIN(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_LEN,_VAL_,0,0xffff0000) #define SET_RX_DEBUG_HCI_EXP_0_LENGHT_LIMIT_MAX(_VAL_) SET_REG(ADR_RX_HCI_EXP_0_LEN,_VAL_,16,0x0000ffff) #define SET_RX_AGG_CNT(_VAL_) SET_REG(ADR_FORCE_RX_AGGREGATION_MODE,_VAL_,0,0xfffffff0) #define SET_RX_AGG_METHOD_3(_VAL_) SET_REG(ADR_FORCE_RX_AGGREGATION_MODE,_VAL_,7,0xffffff7f) #define SET_RX_AGG_TIMER_RELOAD_VALUE(_VAL_) SET_REG(ADR_FORCE_RX_AGGREGATION_MODE,_VAL_,16,0x0000ffff) #define SET_CS_START_ADDR(_VAL_) SET_REG(ADR_CS_START_ADDR,_VAL_,0,0xffff0000) #define SET_CS_PKT_ID(_VAL_) SET_REG(ADR_CS_START_ADDR,_VAL_,16,0xff80ffff) #define SET_ADD_LEN(_VAL_) SET_REG(ADR_CS_ADD_LEN,_VAL_,0,0xffff0000) #define SET_CS_ADDER_EN(_VAL_) SET_REG(ADR_CS_CMD,_VAL_,0,0xfffffffe) #define SET_PSEUDO(_VAL_) SET_REG(ADR_CS_CMD,_VAL_,1,0xfffffffd) #define SET_CALCULATE(_VAL_) SET_REG(ADR_CS_INI_BUF,_VAL_,0,0x00000000) #define SET_L4_LEN(_VAL_) SET_REG(ADR_CS_PSEUDO_BUF,_VAL_,0,0xffff0000) #define SET_L4_PROTOL(_VAL_) SET_REG(ADR_CS_PSEUDO_BUF,_VAL_,16,0xff00ffff) #define SET_CHECK_SUM(_VAL_) SET_REG(ADR_CS_CHECK_SUM,_VAL_,0,0xffff0000) #define SET_RAND_EN(_VAL_) SET_REG(ADR_RAND_EN,_VAL_,0,0xfffffffe) #define SET_RAND_NUM(_VAL_) SET_REG(ADR_RAND_NUM,_VAL_,0,0x00000000) #define SET_MUL_OP1(_VAL_) SET_REG(ADR_MUL_OP1,_VAL_,0,0x00000000) #define SET_MUL_OP2(_VAL_) SET_REG(ADR_MUL_OP2,_VAL_,0,0x00000000) #define SET_MUL_ANS0(_VAL_) SET_REG(ADR_MUL_ANS0,_VAL_,0,0x00000000) #define SET_MUL_ANS1(_VAL_) SET_REG(ADR_MUL_ANS1,_VAL_,0,0x00000000) #define SET_RD_ADDR(_VAL_) SET_REG(ADR_DMA_RDATA,_VAL_,0,0xffff0000) #define SET_RD_ID(_VAL_) SET_REG(ADR_DMA_RDATA,_VAL_,16,0xff80ffff) #define SET_WR_ADDR(_VAL_) SET_REG(ADR_DMA_WDATA,_VAL_,0,0xffff0000) #define SET_WR_ID(_VAL_) SET_REG(ADR_DMA_WDATA,_VAL_,16,0xff80ffff) #define SET_LEN(_VAL_) SET_REG(ADR_DMA_LEN,_VAL_,0,0xffff0000) #define SET_CLR(_VAL_) SET_REG(ADR_DMA_CLR,_VAL_,0,0xfffffffe) #define SET_PHY_MODE(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,0,0xfffffffc) #define SET_SHRT_PREAM(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,2,0xfffffffb) #define SET_SHRT_GI(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,3,0xfffffff7) #define SET_DATA_RATE(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,4,0xfffff80f) #define SET_MCS(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,12,0xffff8fff) #define SET_FRAME_LEN(_VAL_) SET_REG(ADR_NAV_DATA,_VAL_,16,0x0000ffff) #define SET_DURATION(_VAL_) SET_REG(ADR_CO_NAV,_VAL_,0,0xffff0000) #define SET_SHA_DST_ADDR(_VAL_) SET_REG(ADR_SHA_DST_ADDR,_VAL_,0,0x00000000) #define SET_SHA_SRC_ADDR(_VAL_) SET_REG(ADR_SHA_SRC_ADDR,_VAL_,0,0x00000000) #define SET_SHA_BUSY(_VAL_) SET_REG(ADR_SHA_SETTING,_VAL_,0,0xfffffffe) #define SET_SHA_ENDIAN(_VAL_) SET_REG(ADR_SHA_SETTING,_VAL_,1,0xfffffffd) #define SET_EFS_CLKFREQ(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,0,0xfffff000) #define SET_EFS_VDDQ_EN_LOW_ACTIVE(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,16,0xfffeffff) #define SET_EFS_CLKFREQ_RD(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,20,0xf00fffff) #define SET_EFS_PRE_RD(_VAL_) SET_REG(ADR_EFUSE_CLK_FREQ,_VAL_,28,0x0fffffff) #define SET_EFS_LDO_ON(_VAL_) SET_REG(ADR_EFUSE_LDO_TIME,_VAL_,0,0xffff0000) #define SET_EFS_LDO_OFF(_VAL_) SET_REG(ADR_EFUSE_LDO_TIME,_VAL_,16,0x0000ffff) #define SET_EFS_RD_FLAG(_VAL_) SET_REG(ADR_EFUSE_STATUS,_VAL_,0,0xfffffffe) #define SET_EFS_PROGRESS_DONE(_VAL_) SET_REG(ADR_EFUSE_STATUS2,_VAL_,0,0xfffffffe) #define SET_EFS_WR_KICK(_VAL_) SET_REG(ADR_EFUSE_WR_KICK,_VAL_,0,0xfffffffe) #define SET_EFS_RD_KICK(_VAL_) SET_REG(ADR_EFUSE_RD_KICK,_VAL_,0,0xfffffffe) #define SET_EFS_VDDQ_EN(_VAL_) SET_REG(ADR_EFUSE_VDDQ_EN,_VAL_,0,0xfffffffe) #define SET_EFS_BYTE_0(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_1(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_2(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_3(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_0,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_4(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_5(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_6(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_7(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_1,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_8(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_9(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_10(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_11(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_2,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_12(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_13(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_14(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_15(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_3,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_16(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_17(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_18(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_19(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_4,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_20(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_21(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_22(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_23(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_5,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_24(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_25(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_26(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_27(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_6,_VAL_,24,0x00ffffff) #define SET_EFS_BYTE_28(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,0,0xffffff00) #define SET_EFS_BYTE_29(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,8,0xffff00ff) #define SET_EFS_BYTE_30(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,16,0xff00ffff) #define SET_EFS_BYTE_31(_VAL_) SET_REG(ADR_EFUSE_WDATA_0_7,_VAL_,24,0x00ffffff) #define SET_SPI_M_FRONT_DLY(_VAL_) SET_REG(ADR_SPI_DELAY,_VAL_,0,0xffff0000) #define SET_SPI_M_BACK_DLY(_VAL_) SET_REG(ADR_SPI_DELAY,_VAL_,16,0x0000ffff) #define SET_SPI_CLK_DIV(_VAL_) SET_REG(ADR_SPI_CLK_DIV,_VAL_,0,0xffff0000) #define SET_SPI_MASTER_BUSY(_VAL_) SET_REG(ADR_SPI_BUSY,_VAL_,0,0xfffffffe) #define SET_SPI_CLR(_VAL_) SET_REG(ADR_SPI_CLR,_VAL_,0,0xfffffffe) #define SET_CPOL(_VAL_) SET_REG(ADR_SPI_MAS_MODE,_VAL_,0,0xfffffffe) #define SET_CPHA(_VAL_) SET_REG(ADR_SPI_MAS_MODE,_VAL_,1,0xfffffffd) #define SET_CSPOL(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,0,0xfffffffe) #define SET_INV_DATA(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,1,0xfffffffd) #define SET_FAST_CLK(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,2,0xfffffffb) #define SET_AUTO_CSN(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,3,0xfffffff7) #define SET_THREE_WIRE(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,4,0xfffffc0f) #define SET_ENDIAN(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,10,0xfffffbff) #define SET_EARLY_SAMPLE(_VAL_) SET_REG(ADR_SPI_M_CFG,_VAL_,11,0xfffff7ff) #define SET_SPI_CSN(_VAL_) SET_REG(ADR_SPI_CFG,_VAL_,0,0xfffffffe) #define SET_CMD_LEN_SPIMAS(_VAL_) SET_REG(ADR_SPI_MAS_COMMAND_LEN,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_TB0_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB0_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_TB0_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB0_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_MASK0_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK0_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_MASK0_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK0_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_CTRL_0(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL0,_VAL_,0,0xfffffffc) #define SET_MRX_MCAST_TB1_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB1_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_TB1_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB1_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_MASK1_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK1_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_MASK1_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK1_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_CTRL_1(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL1,_VAL_,0,0xfffffffc) #define SET_MRX_MCAST_TB2_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB2_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_TB2_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB2_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_MASK2_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK2_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_MASK2_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK2_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_CTRL_2(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL2,_VAL_,0,0xfffffffc) #define SET_MRX_MCAST_TB3_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_TB3_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_TB3_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_TB3_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_MASK3_31_0(_VAL_) SET_REG(ADR_MRX_MCAST_MK3_0,_VAL_,0,0x00000000) #define SET_MRX_MCAST_MASK3_47_32(_VAL_) SET_REG(ADR_MRX_MCAST_MK3_1,_VAL_,0,0xffff0000) #define SET_MRX_MCAST_CTRL_3(_VAL_) SET_REG(ADR_MRX_MCAST_CTRL3,_VAL_,0,0xfffffffc) #define SET_MRX_PHY_INFO(_VAL_) SET_REG(ADR_MRX_PHY_INFO,_VAL_,0,0x00000000) #define SET_DBG_BA_TYPE(_VAL_) SET_REG(ADR_MRX_BA_DBG,_VAL_,0,0xffffffc0) #define SET_DBG_BA_SEQ(_VAL_) SET_REG(ADR_MRX_BA_DBG,_VAL_,8,0xfff000ff) #define SET_MRX_FLT_TB0(_VAL_) SET_REG(ADR_MRX_FLT_TB0,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB1(_VAL_) SET_REG(ADR_MRX_FLT_TB1,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB2(_VAL_) SET_REG(ADR_MRX_FLT_TB2,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB3(_VAL_) SET_REG(ADR_MRX_FLT_TB3,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB4(_VAL_) SET_REG(ADR_MRX_FLT_TB4,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB5(_VAL_) SET_REG(ADR_MRX_FLT_TB5,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB6(_VAL_) SET_REG(ADR_MRX_FLT_TB6,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB7(_VAL_) SET_REG(ADR_MRX_FLT_TB7,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB8(_VAL_) SET_REG(ADR_MRX_FLT_TB8,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB9(_VAL_) SET_REG(ADR_MRX_FLT_TB9,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB10(_VAL_) SET_REG(ADR_MRX_FLT_TB10,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB11(_VAL_) SET_REG(ADR_MRX_FLT_TB11,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB12(_VAL_) SET_REG(ADR_MRX_FLT_TB12,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB13(_VAL_) SET_REG(ADR_MRX_FLT_TB13,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB14(_VAL_) SET_REG(ADR_MRX_FLT_TB14,_VAL_,0,0xffff8000) #define SET_MRX_FLT_TB15(_VAL_) SET_REG(ADR_MRX_FLT_TB15,_VAL_,0,0xffff8000) #define SET_MRX_FLT_EN0(_VAL_) SET_REG(ADR_MRX_FLT_EN0,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN1(_VAL_) SET_REG(ADR_MRX_FLT_EN1,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN2(_VAL_) SET_REG(ADR_MRX_FLT_EN2,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN3(_VAL_) SET_REG(ADR_MRX_FLT_EN3,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN4(_VAL_) SET_REG(ADR_MRX_FLT_EN4,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN5(_VAL_) SET_REG(ADR_MRX_FLT_EN5,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN6(_VAL_) SET_REG(ADR_MRX_FLT_EN6,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN7(_VAL_) SET_REG(ADR_MRX_FLT_EN7,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN8(_VAL_) SET_REG(ADR_MRX_FLT_EN8,_VAL_,0,0xffff0000) #define SET_MRX_LEN_FLT(_VAL_) SET_REG(ADR_MRX_LEN_FLT,_VAL_,0,0xffff0000) #define SET_RX_FLOW_DATA(_VAL_) SET_REG(ADR_RX_FLOW_DATA,_VAL_,0,0x00000000) #define SET_RX_FLOW_MNG(_VAL_) SET_REG(ADR_RX_FLOW_MNG,_VAL_,0,0xffff0000) #define SET_RX_FLOW_CTRL(_VAL_) SET_REG(ADR_RX_FLOW_CTRL,_VAL_,0,0xffff0000) #define SET_MRX_STP_EN(_VAL_) SET_REG(ADR_RX_TIME_STAMP_CFG,_VAL_,0,0xfffffffe) #define SET_MRX_STP_OFST(_VAL_) SET_REG(ADR_RX_TIME_STAMP_CFG,_VAL_,8,0xffff00ff) #define SET_DBG_FF_FULL(_VAL_) SET_REG(ADR_DBG_FF_FULL,_VAL_,0,0xffff0000) #define SET_DBG_FF_FULL_CLR(_VAL_) SET_REG(ADR_DBG_FF_FULL,_VAL_,31,0x7fffffff) #define SET_DBG_WFF_FULL(_VAL_) SET_REG(ADR_DBG_WFF_FULL,_VAL_,0,0xffff0000) #define SET_DBG_WFF_FULL_CLR(_VAL_) SET_REG(ADR_DBG_WFF_FULL,_VAL_,31,0x7fffffff) #define SET_DBG_MB_FULL(_VAL_) SET_REG(ADR_DBG_MB_FULL,_VAL_,0,0xffff0000) #define SET_DBG_MB_FULL_CLR(_VAL_) SET_REG(ADR_DBG_MB_FULL,_VAL_,31,0x7fffffff) #define SET_BA_CTRL(_VAL_) SET_REG(ADR_BA_CTRL,_VAL_,0,0xfffffffc) #define SET_BA_DBG_EN(_VAL_) SET_REG(ADR_BA_CTRL,_VAL_,2,0xfffffffb) #define SET_BA_AGRE_EN(_VAL_) SET_REG(ADR_BA_CTRL,_VAL_,3,0xfffffff7) #define SET_BA_TA_31_0(_VAL_) SET_REG(ADR_BA_TA_0,_VAL_,0,0x00000000) #define SET_BA_TA_47_32(_VAL_) SET_REG(ADR_BA_TA_1,_VAL_,0,0xffff0000) #define SET_BA_TID(_VAL_) SET_REG(ADR_BA_TID,_VAL_,0,0xfffffff0) #define SET_BA_ST_SEQ(_VAL_) SET_REG(ADR_BA_ST_SEQ,_VAL_,0,0xfffff000) #define SET_BA_SB0(_VAL_) SET_REG(ADR_BA_SB0,_VAL_,0,0x00000000) #define SET_BA_SB1(_VAL_) SET_REG(ADR_BA_SB1,_VAL_,0,0x00000000) #define SET_MRX_WD(_VAL_) SET_REG(ADR_MRX_WATCH_DOG,_VAL_,0,0xfffe0000) #define SET_ACK_GEN_EN(_VAL_) SET_REG(ADR_ACK_GEN_EN,_VAL_,0,0xfffffffe) #define SET_BA_GEN_EN(_VAL_) SET_REG(ADR_ACK_GEN_EN,_VAL_,1,0xfffffffd) #define SET_ACK_GEN_DUR(_VAL_) SET_REG(ADR_ACK_GEN_PARA,_VAL_,0,0xffff0000) #define SET_ACK_GEN_INFO(_VAL_) SET_REG(ADR_ACK_GEN_PARA,_VAL_,16,0xff00ffff) #define SET_ACK_GEN_RA_31_0(_VAL_) SET_REG(ADR_ACK_GEN_RA_0,_VAL_,0,0x00000000) #define SET_ACK_GEN_RA_47_32(_VAL_) SET_REG(ADR_ACK_GEN_RA_1,_VAL_,0,0xffff0000) #define SET_MIB_LEN_FAIL(_VAL_) SET_REG(ADR_MIB_LEN_FAIL,_VAL_,0,0xffff0000) #define SET_TRAP_HW_ID(_VAL_) SET_REG(ADR_TRAP_HW_ID,_VAL_,0,0xfffffff0) #define SET_ID_IN_USE(_VAL_) SET_REG(ADR_ID_IN_USE,_VAL_,0,0xffffff00) #define SET_MRX_ERR(_VAL_) SET_REG(ADR_MRX_ERR,_VAL_,0,0x00000000) #define SET_GRP_WSID(_VAL_) SET_REG(ADR_GROUP_WSID,_VAL_,0,0xfffffff0) #define SET_ADDR1A_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,0,0xfffffffc) #define SET_ADDR2A_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,2,0xfffffff3) #define SET_ADDR3A_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,4,0xffffffcf) #define SET_ADDR1B_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,6,0xffffff3f) #define SET_ADDR2B_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,8,0xfffffcff) #define SET_ADDR3B_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,10,0xfffff3ff) #define SET_ADDR3C_SEL(_VAL_) SET_REG(ADR_HDR_ADDR_SEL,_VAL_,12,0xffffcfff) #define SET_FRM_CTRL(_VAL_) SET_REG(ADR_FRAME_TYPE_CNTR_SET,_VAL_,0,0xffffffc0) #define SET_SCOREBOAD_SIZE(_VAL_) SET_REG(ADR_AMPDU_SCOREBOAD_SIZE,_VAL_,0,0xffffff80) #define SET_MASK_ABNORMAL_CRC(_VAL_) SET_REG(ADR_CHANNEL,_VAL_,0,0xfffffffe) #define SET_PS_EN(_VAL_) SET_REG(ADR_CHANNEL,_VAL_,1,0xfffffffd) #define SET_MULTI_AMPDU_W_EN(_VAL_) SET_REG(ADR_CHANNEL,_VAL_,2,0xfffffffb) #define SET_BA_H_QUEUE_EN(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,0,0xfffffffe) #define SET_EOSP_H_QUEUE_EN(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,1,0xfffffffd) #define SET_EOSP_HW_ID(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,2,0xffffffc3) #define SET_BA_HW_ID(_VAL_) SET_REG(ADR_HIGH_PRIORITY_FRM_HW_ID,_VAL_,6,0xfffffc3f) #define SET_IDX_EXTEND(_VAL_) SET_REG(ADR_DUAL_IDX_EXTEND,_VAL_,0,0xfffffffe) #define SET_MRX_FLT_EN9(_VAL_) SET_REG(ADR_MRX_FLT_EN9,_VAL_,0,0xffff0000) #define SET_MRX_FLT_EN10(_VAL_) SET_REG(ADR_MRX_FLT_EN10,_VAL_,0,0xffff0000) #define SET_CSR_PHY_INFO(_VAL_) SET_REG(ADR_PHY_INFO,_VAL_,0,0xffff8000) #define SET_AMPDU_SIG(_VAL_) SET_REG(ADR_AMPDU_SIG,_VAL_,0,0xffffff00) #define SET_MIB_AMPDU(_VAL_) SET_REG(ADR_MIB_AMPDU,_VAL_,0,0x00000000) #define SET_LEN_FLT(_VAL_) SET_REG(ADR_LEN_FLT,_VAL_,0,0xffff0000) #define SET_MIB_DELIMITER(_VAL_) SET_REG(ADR_MIB_DELIMITER,_VAL_,0,0xffff0000) #define SET_MTX_INT_Q0_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,16,0xfffeffff) #define SET_MTX_INT_Q0_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,17,0xfffdffff) #define SET_MTX_INT_Q1_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,18,0xfffbffff) #define SET_MTX_INT_Q1_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,19,0xfff7ffff) #define SET_MTX_INT_Q2_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,20,0xffefffff) #define SET_MTX_INT_Q2_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,21,0xffdfffff) #define SET_MTX_INT_Q3_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,22,0xffbfffff) #define SET_MTX_INT_Q3_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,23,0xff7fffff) #define SET_MTX_INT_Q4_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,24,0xfeffffff) #define SET_MTX_INT_Q4_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,25,0xfdffffff) #define SET_MTX_INT_Q5_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,26,0xfbffffff) #define SET_MTX_INT_Q5_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_STS,_VAL_,27,0xf7ffffff) #define SET_MTX_EN_INT_Q0_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,16,0xfffeffff) #define SET_MTX_EN_INT_Q0_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,17,0xfffdffff) #define SET_MTX_EN_INT_Q1_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,18,0xfffbffff) #define SET_MTX_EN_INT_Q1_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,19,0xfff7ffff) #define SET_MTX_EN_INT_Q2_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,20,0xffefffff) #define SET_MTX_EN_INT_Q2_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,21,0xffdfffff) #define SET_MTX_EN_INT_Q3_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,22,0xffbfffff) #define SET_MTX_EN_INT_Q3_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,23,0xff7fffff) #define SET_MTX_EN_INT_Q4_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,24,0xfeffffff) #define SET_MTX_EN_INT_Q4_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,25,0xfdffffff) #define SET_MTX_EN_INT_Q5_Q_EMPTY(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,26,0xfbffffff) #define SET_MTX_EN_INT_Q5_TXOP_RUNOUT(_VAL_) SET_REG(ADR_MTX_INT_EN,_VAL_,27,0xf7ffffff) #define SET_MTX_MTX2PHY_SLOW(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,0,0xfffffffe) #define SET_MTX_M2M_SLOW_PRD(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,1,0xfffffff1) #define SET_MTX_AMPDU_CRC8_AUTO(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,5,0xffffffdf) #define SET_MTX_BLOCKTX_IGNORE_BT_BUSY(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,6,0xffffffbf) #define SET_MTX_RAW_DATA_MODE(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,7,0xffffff7f) #define SET_MTX_BLOCKTX_IGNORE_TOMAC_TX_IP(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,11,0xfffff7ff) #define SET_MTX_BLOCKTX_IGNORE_TOMAC_RX_EN(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,12,0xffffefff) #define SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_CS(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,13,0xffffdfff) #define SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_SECONDARY(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,14,0xffffbfff) #define SET_MTX_BLOCKTX_IGNORE_TOMAC_CCA_ED_PRIMARY(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,15,0xffff7fff) #define SET_MTX_HALT_Q_MB(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,16,0xff80ffff) #define SET_MTX_IGNORE_PHYRX_IFS_DELTATIME(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,24,0xfeffffff) #define SET_MTX_SELFSTA_PS(_VAL_) SET_REG(ADR_MTX_MISC_EN,_VAL_,25,0xfdffffff) #define SET_NO_PKT_BUF_REDUCTION(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,0,0xfffffffe) #define SET_NO_REDUCE_TXALLFAIL_PKT(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,2,0xfffffffb) #define SET_NO_REDUCE_PKT_PEERPS_MPDU(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,4,0xffffffef) #define SET_NO_REDUCE_PKT_PEERPS_AMPDUV1P2(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,6,0xffffffbf) #define SET_NO_REDUCE_PKT_PEERPS_AMPDUV1P3(_VAL_) SET_REG(ADR_MTX_TX_REPORT_OPTION,_VAL_,7,0xffffff7f) #define SET_RO_PTC_SCHEDULE(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,0,0xfffffff0) #define SET_RO_FSM_MTXPTC(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,4,0xffffff8f) #define SET_RO_ACT_MASK(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,8,0xffff80ff) #define SET_RO_CAND_MASK(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,16,0xff80ffff) #define SET_RO_WAIT_RESPONSE_PHASE(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,24,0xfcffffff) #define SET_RO_FSM_MTXHALT(_VAL_) SET_REG(ADR_MTX_STATUS0,_VAL_,28,0xcfffffff) #define SET_RO_FSM_MTXDMA(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,0,0xfffffff8) #define SET_RO_FSM_MTXPHYTX(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,4,0xffffff8f) #define SET_RO_MTXDMA_CMD(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,8,0xffffc0ff) #define SET_RO_TXOP_INTERVAL(_VAL_) SET_REG(ADR_MTX_STATUS4,_VAL_,16,0x0000ffff) #define SET_MTX_HALT_MODE0(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,0,0xfffffffe) #define SET_BLOCK_TXQ(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,16,0xff80ffff) #define SET_MTX_HALT_IGNORE_TXREQ_EN(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,24,0xfeffffff) #define SET_MTX_HALT_IGNORE_RXREQ_EN(_VAL_) SET_REG(ADR_MTX_HALT_OPTION,_VAL_,25,0xfdffffff) #define SET_DBG_PHYTX_PROCEED(_VAL_) SET_REG(ADR_MTX_PHYTX_DBG1,_VAL_,0,0xfffffffe) #define SET_MTX_MIB_CNT0(_VAL_) SET_REG(ADR_MTX_MIB_WSID0,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN0(_VAL_) SET_REG(ADR_MTX_MIB_WSID0,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT1(_VAL_) SET_REG(ADR_MTX_MIB_WSID1,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN1(_VAL_) SET_REG(ADR_MTX_MIB_WSID1,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT2(_VAL_) SET_REG(ADR_MTX_MIB_WSID2,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN2(_VAL_) SET_REG(ADR_MTX_MIB_WSID2,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT3(_VAL_) SET_REG(ADR_MTX_MIB_WSID3,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN3(_VAL_) SET_REG(ADR_MTX_MIB_WSID3,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT4(_VAL_) SET_REG(ADR_MTX_MIB_WSID4,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN4(_VAL_) SET_REG(ADR_MTX_MIB_WSID4,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT5(_VAL_) SET_REG(ADR_MTX_MIB_WSID5,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN5(_VAL_) SET_REG(ADR_MTX_MIB_WSID5,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT6(_VAL_) SET_REG(ADR_MTX_MIB_WSID6,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN6(_VAL_) SET_REG(ADR_MTX_MIB_WSID6,_VAL_,30,0xbfffffff) #define SET_MTX_MIB_CNT7(_VAL_) SET_REG(ADR_MTX_MIB_WSID7,_VAL_,0,0xc0000000) #define SET_MTX_MIB_EN7(_VAL_) SET_REG(ADR_MTX_MIB_WSID7,_VAL_,30,0xbfffffff) #define SET_EN_UNEXPECT_WSID(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,0,0xfffffffe) #define SET_EN_STAT_FINISH_INT(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,1,0xfffffffd) #define SET_STAT_EN_MB(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,6,0xffffffbf) #define SET_STAT_MB_TARGET(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,7,0xffffff7f) #define SET_STAT_UNEXPECT_WSID(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,8,0xfffffeff) #define SET_STAT_FINISH(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,9,0xfffffdff) #define SET_STAT_PKT_ID(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,16,0xff80ffff) #define SET_STAT_FSM(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,24,0xe0ffffff) #define SET_STAT_ENABLE(_VAL_) SET_REG(ADR_STAT_CONF0,_VAL_,29,0xdfffffff) #define SET_STAT_WSID(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,0,0xfffffff8) #define SET_STAT_FREEZE(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,8,0xfffffeff) #define SET_STAT_CLR(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,9,0xfffffdff) #define SET_STAT_CLR_DONE(_VAL_) SET_REG(ADR_STAT_CONF1,_VAL_,10,0xfffffbff) #define SET_MAC_TX_PS_UNLOCK(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,0,0xffffff00) #define SET_MAC_TX_PEER_PS_LOCK_EN(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,8,0xfffffeff) #define SET_MAC_TX_PEER_PS_LOCK_AUTOLOCK_EN(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,9,0xfffffdff) #define SET_MAC_TX_PS_LOCK(_VAL_) SET_REG(ADR_MTX_PEER_PS_LOCK,_VAL_,24,0x00ffffff) #define SET_MAC_TX_PS_LOCK_STATUS(_VAL_) SET_REG(ADR_MTX_PEER_LOCK_STATUS,_VAL_,0,0xffffff00) #define SET_MTX_RATERPT_HWID(_VAL_) SET_REG(ADR_MTX_RATERPT,_VAL_,0,0xfffffff0) #define SET_CTYPE_RATE_RPT(_VAL_) SET_REG(ADR_MTX_RATERPT,_VAL_,4,0xffffff8f) #define SET_MTX_DBGOPT_FORCE_TXMAJOR_RATE(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE,_VAL_,0,0xffffff00) #define SET_MTX_DBGOPT_FORCE_TXCTRL_RATE(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE,_VAL_,8,0xffff00ff) #define SET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE,_VAL_,16,0xfffcffff) #define SET_MTX_DBGOPT_FORCE_TXMAJOR_RATE_EN(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE,_VAL_,0,0xfffffffe) #define SET_MTX_DBGOPT_FORCE_TXCTRL_RATE_EN(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE,_VAL_,2,0xfffffffb) #define SET_MTX_DBGOPT_FORCE_DO_RTS_CTS_MODE_EN(_VAL_) SET_REG(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE,_VAL_,4,0xffffffef) #define SET_RO_PHYTXIP_TIMEOUT_CNT(_VAL_) SET_REG(ADR_MTX_DBG_PHYTXIPTIMEOUT,_VAL_,0,0xfffffff0) #define SET_DBG_PHYTXIP_TIMEOUT_RECOVERY(_VAL_) SET_REG(ADR_MTX_DBG_PHYTXIPTIMEOUT,_VAL_,8,0xfffffeff) #define SET_DBG_MTX_IGNORE_NAV(_VAL_) SET_REG(ADR_MTX_DBG_MORE,_VAL_,0,0xfffffffe) #define SET_RO_IFSAIR1(_VAL_) SET_REG(ADR_MTX_DBG_ROIFSAIR1,_VAL_,0,0x00000000) #define SET_RO_IFSAIR2(_VAL_) SET_REG(ADR_MTX_DBG_ROIFSAIR2,_VAL_,0,0x00000000) #define SET_MTX_BCN_PKT_ID0(_VAL_) SET_REG(ADR_MTX_BCN_PKT_SET0,_VAL_,0,0xffffff80) #define SET_MTX_BCN_PKT_ID1(_VAL_) SET_REG(ADR_MTX_BCN_PKT_SET1,_VAL_,0,0xffffff80) #define SET_MTX_DTIM_OFST0(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_SET0,_VAL_,0,0xfffffc00) #define SET_MTX_DTIM_OFST1(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_SET1,_VAL_,0,0xfffffc00) #define SET_MTX_DTIM_NUM(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_CONFG,_VAL_,0,0xffffff00) #define SET_MTX_INT_DTIM_NUM(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_CONFG,_VAL_,8,0xffff00ff) #define SET_MTX_INT_DTIM(_VAL_) SET_REG(ADR_MTX_BCN_DTIM_INT_W1CLR,_VAL_,0,0xfffffffe) #define SET_MTX_INT_BCN(_VAL_) SET_REG(ADR_MTX_BCN_INT_STS,_VAL_,0,0xfffffffe) #define SET_MTX_EN_INT_BCN(_VAL_) SET_REG(ADR_MTX_BCN_EN_INT,_VAL_,1,0xfffffffd) #define SET_MTX_EN_INT_DTIM(_VAL_) SET_REG(ADR_MTX_BCN_EN_INT,_VAL_,3,0xfffffff7) #define SET_MTX_BCN_TIMER_EN(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,0,0xfffffffe) #define SET_MTX_TIME_STAMP_AUTO_FILL(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,1,0xfffffffd) #define SET_MTX_DTIM_CNT_AUTO_FILL(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,3,0xfffffff7) #define SET_MTX_TSF_TIMER_EN(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,5,0xffffffdf) #define SET_TXQ5_DTIM_BEACON_BURST_MNG(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,16,0xfffeffff) #define SET_MTX_BCN_AUTO_SEQ_NO(_VAL_) SET_REG(ADR_MTX_BCN_EN_MISC,_VAL_,17,0xfffdffff) #define SET_MTX_BCN_PKTID_CH_LOCK(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,0,0xfffffffe) #define SET_MTX_BCN_CFG_VLD(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,1,0xfffffff9) #define SET_MTX_AUTO_BCN_ONGOING(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,3,0xfffffff7) #define SET_MTX_BCN_TIMER(_VAL_) SET_REG(ADR_MTX_BCN_MISC,_VAL_,16,0x0000ffff) #define SET_MTX_BCN_PERIOD(_VAL_) SET_REG(ADR_MTX_BCN_PRD,_VAL_,0,0xffff0000) #define SET_MTX_BCN_TSF_L(_VAL_) SET_REG(ADR_MTX_BCN_TSF_L,_VAL_,0,0x00000000) #define SET_MTX_BCN_TSF_U(_VAL_) SET_REG(ADR_MTX_BCN_TSF_U,_VAL_,0,0x00000000) #define SET_TOUT_B(_VAL_) SET_REG(ADR_MTX_TIME_TOUT,_VAL_,0,0xffffff00) #define SET_TOUT_AGN(_VAL_) SET_REG(ADR_MTX_TIME_TOUT,_VAL_,8,0xffff00ff) #define SET_EIFS_IN_SLOT(_VAL_) SET_REG(ADR_MTX_TIME_TOUT,_VAL_,16,0xffc0ffff) #define SET_TXSIFS_SUB_MIN(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,0,0xfffffff0) #define SET_TXSIFS_SUB_MAX(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,4,0xffffff0f) #define SET_SLOTTIME(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,8,0xffffe0ff) #define SET_SIFS(_VAL_) SET_REG(ADR_MTX_TIME_IFS,_VAL_,16,0xffe0ffff) #define SET_NAVCS_PHYCS_FALL_OFFSET_STEP(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,0,0xffffff80) #define SET_TX_IP_FALL_OFFSET_STEP(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,8,0xffff80ff) #define SET_PHYTXSTART_NCYCLE(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,16,0xff80ffff) #define SET_SIGEXT(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,24,0xf0ffffff) #define SET_MAC_CLK_80M(_VAL_) SET_REG(ADR_MTX_TIME_FINETUNE,_VAL_,28,0xefffffff) #define SET_RO_MTX_TX_EN(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,20,0xffefffff) #define SET_RO_MAC_TX_FIFO_WINC(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,21,0xffdfffff) #define SET_RO_MAC_TX_FIFO_WFULL_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,22,0xffbfffff) #define SET_RO_MAC_TX_FIFO_WEMPTY(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,23,0xff7fffff) #define SET_TOMAC_TX_IP(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,24,0xfeffffff) #define SET_TOMAC_ED_CCA_PRIMARY_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,28,0xefffffff) #define SET_TOMAC_ED_CCA_SECONDARY_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,29,0xdfffffff) #define SET_TOMAC_CS_CCA_MX(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,30,0xbfffffff) #define SET_BT_BUSY(_VAL_) SET_REG(ADR_MTX_STATUS,_VAL_,31,0x7fffffff) #define SET_MTX_DBG_PHYRX_IFS_DELTATIME(_VAL_) SET_REG(ADR_MTX_PHYRXIFS_DBG,_VAL_,0,0xfffff800) #define SET_RO_IFSST0(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO0,_VAL_,0,0x00000000) #define SET_RO_IFSST1(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO1,_VAL_,0,0x00000000) #define SET_RO_IFSST2(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO2,_VAL_,0,0x00000000) #define SET_RO_IFSST3(_VAL_) SET_REG(ADR_MTX_DBG_IFSAIRRO3,_VAL_,0,0x00000000) #define SET_MTX_NAV(_VAL_) SET_REG(ADR_MTX_NAV,_VAL_,0,0xffff0000) #define SET_RO_MTX_BASE1(_VAL_) SET_REG(ADR_MTX_DBG_RO_BASE1,_VAL_,0,0x00000000) #define SET_RO_MTX_BASE2(_VAL_) SET_REG(ADR_MTX_DBG_RO_BASE2,_VAL_,0,0x00000000) #define SET_RO_MTX_BASE3(_VAL_) SET_REG(ADR_MTX_DBG_RO_BASE3,_VAL_,0,0x00000000) #define SET_TXQ0_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8) #define SET_TXQ0_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_MISC_EN,_VAL_,4,0xffffffef) #define SET_TXQ0_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff) #define SET_TXQ0_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,0,0xfffffff0) #define SET_TXQ0_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff) #define SET_TXQ0_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,12,0xffff0fff) #define SET_TXQ0_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_AIFSN,_VAL_,16,0x0000ffff) #define SET_TXQ0_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000) #define SET_TXQ0_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,0,0xfffffffc) #define SET_TXQ0_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,4,0xffffff0f) #define SET_TXQ0_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,8,0xfffffcff) #define SET_TXQ0_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,12,0xffff0fff) #define SET_TXQ0_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG,_VAL_,16,0x0000ffff) #define SET_TXQ0_RO_PKTID(_VAL_) SET_REG(ADR_TXQ0_MTX_Q_HWDBG2,_VAL_,0,0xffffff80) #define SET_TXQ1_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8) #define SET_TXQ1_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_MISC_EN,_VAL_,4,0xffffffef) #define SET_TXQ1_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff) #define SET_TXQ1_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,0,0xfffffff0) #define SET_TXQ1_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff) #define SET_TXQ1_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,12,0xffff0fff) #define SET_TXQ1_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_AIFSN,_VAL_,16,0x0000ffff) #define SET_TXQ1_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000) #define SET_TXQ1_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,0,0xfffffffc) #define SET_TXQ1_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,4,0xffffff0f) #define SET_TXQ1_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,8,0xfffffcff) #define SET_TXQ1_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,12,0xffff0fff) #define SET_TXQ1_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG,_VAL_,16,0x0000ffff) #define SET_TXQ1_RO_PKTID(_VAL_) SET_REG(ADR_TXQ1_MTX_Q_HWDBG2,_VAL_,0,0xffffff80) #define SET_TXQ2_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8) #define SET_TXQ2_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_MISC_EN,_VAL_,4,0xffffffef) #define SET_TXQ2_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff) #define SET_TXQ2_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,0,0xfffffff0) #define SET_TXQ2_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff) #define SET_TXQ2_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,12,0xffff0fff) #define SET_TXQ2_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_AIFSN,_VAL_,16,0x0000ffff) #define SET_TXQ2_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000) #define SET_TXQ2_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,0,0xfffffffc) #define SET_TXQ2_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,4,0xffffff0f) #define SET_TXQ2_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,8,0xfffffcff) #define SET_TXQ2_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,12,0xffff0fff) #define SET_TXQ2_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG,_VAL_,16,0x0000ffff) #define SET_TXQ2_RO_PKTID(_VAL_) SET_REG(ADR_TXQ2_MTX_Q_HWDBG2,_VAL_,0,0xffffff80) #define SET_TXQ3_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8) #define SET_TXQ3_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_MISC_EN,_VAL_,4,0xffffffef) #define SET_TXQ3_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff) #define SET_TXQ3_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,0,0xfffffff0) #define SET_TXQ3_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff) #define SET_TXQ3_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,12,0xffff0fff) #define SET_TXQ3_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_AIFSN,_VAL_,16,0x0000ffff) #define SET_TXQ3_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000) #define SET_TXQ3_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,0,0xfffffffc) #define SET_TXQ3_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,4,0xffffff0f) #define SET_TXQ3_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,8,0xfffffcff) #define SET_TXQ3_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,12,0xffff0fff) #define SET_TXQ3_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG,_VAL_,16,0x0000ffff) #define SET_TXQ3_RO_PKTID(_VAL_) SET_REG(ADR_TXQ3_MTX_Q_HWDBG2,_VAL_,0,0xffffff80) #define SET_TXQ4_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8) #define SET_TXQ4_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_MISC_EN,_VAL_,4,0xffffffef) #define SET_TXQ4_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff) #define SET_TXQ4_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,0,0xfffffff0) #define SET_TXQ4_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff) #define SET_TXQ4_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,12,0xffff0fff) #define SET_TXQ4_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_AIFSN,_VAL_,16,0x0000ffff) #define SET_TXQ4_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000) #define SET_TXQ4_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,0,0xfffffffc) #define SET_TXQ4_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,4,0xffffff0f) #define SET_TXQ4_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,8,0xfffffcff) #define SET_TXQ4_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,12,0xffff0fff) #define SET_TXQ4_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG,_VAL_,16,0x0000ffff) #define SET_TXQ4_RO_PKTID(_VAL_) SET_REG(ADR_TXQ4_MTX_Q_HWDBG2,_VAL_,0,0xffffff80) #define SET_TXQ5_MTX_Q_RND_MODE(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_MISC_EN,_VAL_,0,0xfffffff8) #define SET_TXQ5_MTX_Q_MB_NO_RLS(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_MISC_EN,_VAL_,4,0xffffffef) #define SET_TXQ5_Q_NULLDATAFRAME_GEN_EN(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_MISC_EN,_VAL_,31,0x7fffffff) #define SET_TXQ5_MTX_Q_AIFSN(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,0,0xfffffff0) #define SET_TXQ5_MTX_Q_ECWMIN(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,8,0xfffff0ff) #define SET_TXQ5_MTX_Q_ECWMAX(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,12,0xffff0fff) #define SET_TXQ5_MTX_Q_TXOP_LIMIT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_AIFSN,_VAL_,16,0x0000ffff) #define SET_TXQ5_MTX_Q_BKF_CNT_FIX(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_BKF_CNT_DBG,_VAL_,0,0xffff0000) #define SET_TXQ5_RO_FSM_TXQ(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,0,0xfffffffc) #define SET_TXQ5_RO_TRY_CNT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,4,0xffffff0f) #define SET_TXQ5_RO_RATESET_IDX(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,8,0xfffffcff) #define SET_TXQ5_RO_AIFS_CNT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,12,0xffff0fff) #define SET_TXQ5_RO_BKF_CNT(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG,_VAL_,16,0x0000ffff) #define SET_TXQ5_RO_PKTID(_VAL_) SET_REG(ADR_TXQ5_MTX_Q_HWDBG2,_VAL_,0,0xffffff80) #define SET_MTX_RESPFRM_RATE_EXCEPTION(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_00(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_00,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_01(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_01,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_02(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_02,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_03(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_03,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_11(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_11,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_12(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_12,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_13(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_13,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_90_B0(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_90_B0,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_91_B1(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_91_B1,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_92_B2(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_92_B2,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_93_B3(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_93_B3,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_94_B4(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_94_B4,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_95_B5(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_95_B5,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_96_B6(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_96_B6,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_97_B7(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_97_B7,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C0_E0(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C0_E0,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C1_E1(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C1_E1,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C2_E2(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C2_E2,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C3_E3(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C3_E3,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C4_E4(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C4_E4,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C5_E5(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C5_E5,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C6_E6(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C6_E6,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_C7_E7(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_C7_E7,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D0_F0(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D0_F0,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D1_F1(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D1_F1,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D2_F2(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D2_F2,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D3_F3(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D3_F3,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D4_F4(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D4_F4,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D5_F5(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D5_F5,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D6_F6(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D6_F6,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D7_F7(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D7_F7,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D8_F8(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D8_F8,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_D9_F9(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_D9_F9,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_DA_FA(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DA_FA,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_DB_FB(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DB_FB,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_DC_FC(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DC_FC,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_DD_FD(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DD_FD,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_DE_FE(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DE_FE,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_RATE_DF_FF(_VAL_) SET_REG(ADR_MTX_RESPFRM_RATE_TABLE_DF_FF,_VAL_,0,0xffff0000) #define SET_MTX_RESPFRM_INFO_EXCEPTION(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_00(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_00,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_01(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_01,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_02(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_02,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_03(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_03,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_11(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_11,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_12(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_12,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_13(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_13,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_90_B0(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_90_B0,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_91_B1(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_91_B1,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_92_B2(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_92_B2,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_93_B3(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_93_B3,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_94_B4(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_94_B4,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_95_B5(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_95_B5,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_96_B6(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_96_B6,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_97_B7(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_97_B7,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C0(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C0,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C1(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C1,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C2(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C2,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C3(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C3,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C4(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C4,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C5(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C5,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C6(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C6,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_C7(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_C7,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D0(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D0,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D1(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D1,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D2(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D2,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D3(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D3,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D4(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D4,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D5(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D5,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D6(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D6,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D7(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D7,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D8(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D8,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_D9(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_D9,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_DA(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DA,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_DB(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DB,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_DC(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DC,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_DD(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DD,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_DE(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DE,_VAL_,0,0xffe00000) #define SET_MTX_RESPFRM_INFO_DF(_VAL_) SET_REG(ADR_MTX_RESPFRM_INFO_DF,_VAL_,0,0xffe00000) #define SET_VALID0(_VAL_) SET_REG(ADR_WSID0,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN0(_VAL_) SET_REG(ADR_WSID0,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE0(_VAL_) SET_REG(ADR_WSID0,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE0(_VAL_) SET_REG(ADR_WSID0,_VAL_,4,0xffffffcf) #define SET_PEER_MAC0_31_0(_VAL_) SET_REG(ADR_PEER_MAC0_0,_VAL_,0,0x00000000) #define SET_PEER_MAC0_47_32(_VAL_) SET_REG(ADR_PEER_MAC0_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_0_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_0_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_0_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_0_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_0_7,_VAL_,0,0xfffff000) #define SET_VALID1(_VAL_) SET_REG(ADR_WSID1,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN1(_VAL_) SET_REG(ADR_WSID1,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE1(_VAL_) SET_REG(ADR_WSID1,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE1(_VAL_) SET_REG(ADR_WSID1,_VAL_,4,0xffffffcf) #define SET_PEER_MAC1_31_0(_VAL_) SET_REG(ADR_PEER_MAC1_0,_VAL_,0,0x00000000) #define SET_PEER_MAC1_47_32(_VAL_) SET_REG(ADR_PEER_MAC1_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_1_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_1_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_1_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_1_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_1_7,_VAL_,0,0xfffff000) #define SET_CH1_PRI(_VAL_) SET_REG(ADR_PACKET_ID_ALLOCATION_PRIORITY,_VAL_,0,0xfffffffc) #define SET_CH2_PRI(_VAL_) SET_REG(ADR_PACKET_ID_ALLOCATION_PRIORITY,_VAL_,8,0xfffffcff) #define SET_CH3_PRI(_VAL_) SET_REG(ADR_PACKET_ID_ALLOCATION_PRIORITY,_VAL_,16,0xfffcffff) #define SET_RG_MAC_LPBK(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,0,0xfffffffe) #define SET_RG_MAC_M2M(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,1,0xfffffffd) #define SET_RG_PHY_LPBK(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,2,0xfffffffb) #define SET_RG_LPBK_RX_EN(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,3,0xfffffff7) #define SET_EXT_MAC_MODE(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,4,0xffffffef) #define SET_EXT_PHY_MODE(_VAL_) SET_REG(ADR_MAC_MODE,_VAL_,5,0xffffffdf) #define SET_HCI_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,0,0xfffffffe) #define SET_CO_PROC_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,1,0xfffffffd) #define SET_MTX_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,2,0xfffffffb) #define SET_MTX_MISC_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,3,0xfffffff7) #define SET_MTX_QUE_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,4,0xffffffef) #define SET_MTX_CHST_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,5,0xffffffdf) #define SET_MTX_BCN_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,6,0xffffffbf) #define SET_MRX_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,7,0xffffff7f) #define SET_AMPDU_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,8,0xfffffeff) #define SET_MMU_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,9,0xfffffdff) #define SET_ID_MNG_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,11,0xfffff7ff) #define SET_MBOX_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,12,0xffffefff) #define SET_SCRT_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,13,0xffffdfff) #define SET_MIC_SW_RST(_VAL_) SET_REG(ADR_ALL_SOFTWARE_RESET,_VAL_,14,0xffffbfff) #define SET_CO_PROC_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,1,0xfffffffd) #define SET_MTX_MISC_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,3,0xfffffff7) #define SET_MTX_QUE_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,4,0xffffffef) #define SET_MTX_CHST_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,5,0xffffffdf) #define SET_MTX_BCN_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,6,0xffffffbf) #define SET_MRX_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,7,0xffffff7f) #define SET_AMPDU_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,8,0xfffffeff) #define SET_ID_MNG_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,14,0xffffbfff) #define SET_MBOX_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,15,0xffff7fff) #define SET_SCRT_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,16,0xfffeffff) #define SET_MIC_ENG_RST(_VAL_) SET_REG(ADR_ENG_SOFTWARE_RESET,_VAL_,17,0xfffdffff) #define SET_CO_PROC_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,1,0xfffffffd) #define SET_MTX_MISC_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,3,0xfffffff7) #define SET_MTX_QUE0_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,4,0xffffffef) #define SET_MTX_QUE1_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,5,0xffffffdf) #define SET_MTX_QUE2_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,6,0xffffffbf) #define SET_MTX_QUE3_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,7,0xffffff7f) #define SET_MTX_QUE4_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,8,0xfffffeff) #define SET_MTX_QUE5_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,9,0xfffffdff) #define SET_MRX_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,10,0xfffffbff) #define SET_AMPDU_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,11,0xfffff7ff) #define SET_SCRT_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,13,0xffffdfff) #define SET_ID_MNG_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,14,0xffffbfff) #define SET_MBOX_CSR_RST(_VAL_) SET_REG(ADR_CSR_SOFTWARE_RESET,_VAL_,15,0xffff7fff) #define SET_HCI_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,0,0xfffffffe) #define SET_CO_PROC_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,1,0xfffffffd) #define SET_MTX_MISC_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,3,0xfffffff7) #define SET_MTX_QUE_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,4,0xffffffef) #define SET_MRX_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,5,0xffffffdf) #define SET_AMPDU_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,6,0xffffffbf) #define SET_MMU_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,7,0xffffff7f) #define SET_ID_MNG_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,9,0xfffffdff) #define SET_MBOX_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,10,0xfffffbff) #define SET_SCRT_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,11,0xfffff7ff) #define SET_MIC_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,12,0xffffefff) #define SET_MIB_CLK_EN(_VAL_) SET_REG(ADR_MAC_CLOCK_ENABLE,_VAL_,13,0xffffdfff) #define SET_HCI_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,0,0xfffffffe) #define SET_CO_PROC_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,1,0xfffffffd) #define SET_MTX_MISC_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,3,0xfffffff7) #define SET_MTX_QUE_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,4,0xffffffef) #define SET_MRX_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,5,0xffffffdf) #define SET_AMPDU_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,6,0xffffffbf) #define SET_ID_MNG_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,12,0xffffefff) #define SET_MBOX_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,13,0xffffdfff) #define SET_SCRT_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,14,0xffffbfff) #define SET_MIC_ENG_CLK_EN(_VAL_) SET_REG(ADR_MAC_ENGINE_CLOCK_ENABLE,_VAL_,15,0xffff7fff) #define SET_CO_PROC_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,1,0xfffffffd) #define SET_MRX_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,10,0xfffffbff) #define SET_AMPDU_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,11,0xfffff7ff) #define SET_SCRT_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,13,0xffffdfff) #define SET_ID_MNG_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,14,0xffffbfff) #define SET_MBOX_CSR_CLK_EN(_VAL_) SET_REG(ADR_MAC_CSR_CLOCK_ENABLE,_VAL_,15,0xffff7fff) #define SET_OP_MODE(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,0,0xfffffffc) #define SET_HT_MODE(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,2,0xfffffff3) #define SET_QOS_EN(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,4,0xffffffef) #define SET_PB_OFFSET(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,8,0xffff00ff) #define SET_SNIFFER_MODE(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,16,0xfffeffff) #define SET_DUP_FLT(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,17,0xfffdffff) #define SET_TX_PKT_RSVD(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,18,0xffe3ffff) #define SET_AMPDU_SNIFFER(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,21,0xffdfffff) #define SET_CCMP_H_SEL(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,22,0xffbfffff) #define SET_LUT_SEL_V2(_VAL_) SET_REG(ADR_GLBLE_SET,_VAL_,23,0xff7fffff) #define SET_REASON_TRAP0(_VAL_) SET_REG(ADR_REASON_TRAP0,_VAL_,0,0x00000000) #define SET_REASON_TRAP1(_VAL_) SET_REG(ADR_REASON_TRAP1,_VAL_,0,0x00000000) #define SET_BSSID_31_0(_VAL_) SET_REG(ADR_BSSID_0,_VAL_,0,0x00000000) #define SET_BSSID_47_32(_VAL_) SET_REG(ADR_BSSID_1,_VAL_,0,0xffff0000) #define SET_STA_MAC_31_0(_VAL_) SET_REG(ADR_STA_MAC_0,_VAL_,0,0x00000000) #define SET_STA_MAC_47_32(_VAL_) SET_REG(ADR_STA_MAC_1,_VAL_,0,0xffff0000) #define SET_PAIR_SCRT(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,0,0xfffffff8) #define SET_GRP_SCRT(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,3,0xffffffc7) #define SET_SCRT_PKT_ID(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,6,0xffffe03f) #define SET_SCRT_RPLY_IGNORE(_VAL_) SET_REG(ADR_SCRT_SET,_VAL_,16,0xfffeffff) #define SET_SCRT_STATE(_VAL_) SET_REG(ADR_SCRT_STATE,_VAL_,0,0xfffffff0) #define SET_BSSID1_31_0(_VAL_) SET_REG(ADR_BSSID1_0,_VAL_,0,0x00000000) #define SET_BSSID1_47_32(_VAL_) SET_REG(ADR_BSSID1_1,_VAL_,0,0xffff0000) #define SET_STA_MAC1_31_0(_VAL_) SET_REG(ADR_STA_MAC1_0,_VAL_,0,0x00000000) #define SET_STA_MAC1_47_32(_VAL_) SET_REG(ADR_STA_MAC1_1,_VAL_,0,0xffff0000) #define SET_OP_MODE1(_VAL_) SET_REG(ADR_OP_MODE1,_VAL_,0,0xfffffffc) #define SET_COEXIST_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,0,0xfffffffe) #define SET_WIRE_MODE(_VAL_) SET_REG(ADR_BTCX0,_VAL_,1,0xfffffff1) #define SET_WL_RX_PRI(_VAL_) SET_REG(ADR_BTCX0,_VAL_,4,0xffffffef) #define SET_WL_TX_PRI(_VAL_) SET_REG(ADR_BTCX0,_VAL_,5,0xffffffdf) #define SET_GURAN_USE_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,8,0xfffffeff) #define SET_GURAN_USE_CTRL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,9,0xfffffdff) #define SET_BEACON_TIMEOUT_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,10,0xfffffbff) #define SET_WLAN_ACT_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,11,0xfffff7ff) #define SET_DUAL_ANT_EN(_VAL_) SET_REG(ADR_BTCX0,_VAL_,12,0xffffefff) #define SET_TRSW_PHY_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,16,0xfffeffff) #define SET_WIFI_TX_SW_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,17,0xfffdffff) #define SET_WIFI_RX_SW_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,18,0xfffbffff) #define SET_BT_SW_POL(_VAL_) SET_REG(ADR_BTCX0,_VAL_,19,0xfff7ffff) #define SET_BT_PRI_SMP_TIME(_VAL_) SET_REG(ADR_BTCX1,_VAL_,0,0xffffff00) #define SET_BT_STA_SMP_TIME(_VAL_) SET_REG(ADR_BTCX1,_VAL_,8,0xffff00ff) #define SET_BEACON_TIMEOUT(_VAL_) SET_REG(ADR_BTCX1,_VAL_,16,0xff00ffff) #define SET_WLAN_REMAIN_TIME(_VAL_) SET_REG(ADR_BTCX1,_VAL_,24,0x00ffffff) #define SET_SW_MANUAL_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,0,0xfffffffe) #define SET_SW_WL_TX(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,1,0xfffffffd) #define SET_SW_WL_RX(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,2,0xfffffffb) #define SET_SW_BT_TRX(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,3,0xfffffff7) #define SET_BT_TXBAR_MANUAL_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,4,0xffffffef) #define SET_BT_TXBAR_SET(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,5,0xffffffdf) #define SET_BT_BUSY_MANUAL_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,8,0xfffffeff) #define SET_BT_BUSY_SET(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,9,0xfffffdff) #define SET_SWITCH_2WIRE_EN(_VAL_) SET_REG(ADR_SWITCH_CTL,_VAL_,10,0xfffffbff) #define SET_RANDOM_SEED3(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,0,0xffffff00) #define SET_RANDOM_SEED2(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,8,0xffff00ff) #define SET_RANDOM_SEED1(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,16,0xff00ffff) #define SET_BT_TRX_SMP_TIME(_VAL_) SET_REG(ADR_RANDOM_CTL,_VAL_,24,0x00ffffff) #define SET_BTCX_INT_MASK(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,0,0xffffffe0) #define SET_BTCX_INTR(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,5,0xffffffdf) #define SET_AUTO_REMAIN(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,6,0xffffffbf) #define SET_PREDE_BT_TX(_VAL_) SET_REG(ADR_BTCX_MISC_CTL,_VAL_,7,0xffffff7f) #define SET_G0_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,2,0xfffffffb) #define SET_G0_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,3,0xfffffff7) #define SET_G1_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,4,0xffffffef) #define SET_G1_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,5,0xffffffdf) #define SET_Q0_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,6,0xffffffbf) #define SET_Q0_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,7,0xffffff7f) #define SET_Q1_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,8,0xfffffeff) #define SET_Q1_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,9,0xfffffdff) #define SET_Q2_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,10,0xfffffbff) #define SET_Q2_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,11,0xfffff7ff) #define SET_Q3_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,12,0xffffefff) #define SET_Q3_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,13,0xffffdfff) #define SET_SCRT_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,14,0xffffbfff) #define SET_SCRT_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,15,0xffff7fff) #define SET_MISC_PKT_CLS_MIB_EN(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,16,0xfffeffff) #define SET_MISC_PKT_CLS_ONGOING(_VAL_) SET_REG(ADR_MIB_EN,_VAL_,17,0xfffdffff) #define SET_MTX_WSID0_SUCC(_VAL_) SET_REG(ADR_MTX_WSID0_SUCC,_VAL_,0,0xffff0000) #define SET_MTX_WSID0_FRM(_VAL_) SET_REG(ADR_MTX_WSID0_FRM,_VAL_,0,0xffff0000) #define SET_MTX_WSID0_RETRY(_VAL_) SET_REG(ADR_MTX_WSID0_RETRY,_VAL_,0,0xffff0000) #define SET_MTX_WSID0_TOTAL(_VAL_) SET_REG(ADR_MTX_WSID0_TOTAL,_VAL_,0,0xffff0000) #define SET_MTX_GRP(_VAL_) SET_REG(ADR_MTX_GROUP,_VAL_,0,0xfff00000) #define SET_MTX_FAIL(_VAL_) SET_REG(ADR_MTX_FAIL,_VAL_,0,0xffff0000) #define SET_MTX_RETRY(_VAL_) SET_REG(ADR_MTX_RETRY,_VAL_,0,0xfff00000) #define SET_MTX_MULTI_RETRY(_VAL_) SET_REG(ADR_MTX_MULTI_RETRY,_VAL_,0,0xfff00000) #define SET_MTX_RTS_SUCC(_VAL_) SET_REG(ADR_MTX_RTS_SUCCESS,_VAL_,0,0xffff0000) #define SET_MTX_RTS_FAIL(_VAL_) SET_REG(ADR_MTX_RTS_FAIL,_VAL_,0,0xffff0000) #define SET_MTX_ACK_FAIL(_VAL_) SET_REG(ADR_MTX_ACK_FAIL,_VAL_,0,0xffff0000) #define SET_MTX_FRM(_VAL_) SET_REG(ADR_MTX_FRM,_VAL_,0,0xfff00000) #define SET_MTX_ACK_TX(_VAL_) SET_REG(ADR_MTX_ACK_TX,_VAL_,0,0xffff0000) #define SET_MTX_CTS_TX(_VAL_) SET_REG(ADR_MTX_CTS_TX,_VAL_,0,0xffff0000) #define SET_MRX_DUP(_VAL_) SET_REG(ADR_MRX_DUP_FRM,_VAL_,0,0xffff0000) #define SET_MRX_FRG(_VAL_) SET_REG(ADR_MRX_FRG_FRM,_VAL_,0,0xfff00000) #define SET_MRX_GRP(_VAL_) SET_REG(ADR_MRX_GROUP_FRM,_VAL_,0,0xfff00000) #define SET_MRX_FCS_ERR(_VAL_) SET_REG(ADR_MRX_FCS_ERR,_VAL_,0,0xffff0000) #define SET_MRX_FCS_SUC(_VAL_) SET_REG(ADR_MRX_FCS_SUCC,_VAL_,0,0xffff0000) #define SET_MRX_MISS(_VAL_) SET_REG(ADR_MRX_MISS,_VAL_,0,0xffff0000) #define SET_MRX_ALC_FAIL(_VAL_) SET_REG(ADR_MRX_ALC_FAIL,_VAL_,0,0xffff0000) #define SET_MRX_DAT_NTF(_VAL_) SET_REG(ADR_MRX_DAT_NTF,_VAL_,0,0xffff0000) #define SET_MRX_RTS_NTF(_VAL_) SET_REG(ADR_MRX_RTS_NTF,_VAL_,0,0xffff0000) #define SET_MRX_CTS_NTF(_VAL_) SET_REG(ADR_MRX_CTS_NTF,_VAL_,0,0xffff0000) #define SET_MRX_ACK_NTF(_VAL_) SET_REG(ADR_MRX_ACK_NTF,_VAL_,0,0xffff0000) #define SET_MRX_BA_NTF(_VAL_) SET_REG(ADR_MRX_BA_NTF,_VAL_,0,0xffff0000) #define SET_MRX_DATA_NTF(_VAL_) SET_REG(ADR_MRX_DATA_NTF,_VAL_,0,0xffff0000) #define SET_MRX_MNG_NTF(_VAL_) SET_REG(ADR_MRX_MNG_NTF,_VAL_,0,0xffff0000) #define SET_MRX_DAT_CRC_NTF(_VAL_) SET_REG(ADR_MRX_DAT_CRC_NTF,_VAL_,0,0xffff0000) #define SET_MRX_BAR_NTF(_VAL_) SET_REG(ADR_MRX_BAR_NTF,_VAL_,0,0xffff0000) #define SET_MRX_MB_MISS(_VAL_) SET_REG(ADR_MRX_MB_MISS,_VAL_,0,0xffff0000) #define SET_MRX_NIDLE_MISS(_VAL_) SET_REG(ADR_MRX_NIDLE_MISS,_VAL_,0,0xffff0000) #define SET_MRX_CSR_NTF(_VAL_) SET_REG(ADR_MRX_CSR_NTF,_VAL_,0,0xffff0000) #define SET_DBG_Q0_SUCC(_VAL_) SET_REG(ADR_DBG_Q0_FRM_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q0_FAIL(_VAL_) SET_REG(ADR_DBG_Q0_FRM_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q0_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q0_ACK_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q0_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q0_ACK_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q1_SUCC(_VAL_) SET_REG(ADR_DBG_Q1_FRM_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q1_FAIL(_VAL_) SET_REG(ADR_DBG_Q1_FRM_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q1_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q1_ACK_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q1_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q1_ACK_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q2_SUCC(_VAL_) SET_REG(ADR_DBG_Q2_FRM_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q2_FAIL(_VAL_) SET_REG(ADR_DBG_Q2_FRM_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q2_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q2_ACK_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q2_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q2_ACK_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q3_SUCC(_VAL_) SET_REG(ADR_DBG_Q3_FRM_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q3_FAIL(_VAL_) SET_REG(ADR_DBG_Q3_FRM_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_Q3_ACK_SUCC(_VAL_) SET_REG(ADR_DBG_Q3_ACK_SUCCESS,_VAL_,0,0xffff0000) #define SET_DBG_Q3_ACK_FAIL(_VAL_) SET_REG(ADR_DBG_Q3_ACK_FAIL,_VAL_,0,0xffff0000) #define SET_SCRT_TKIP_CERR(_VAL_) SET_REG(ADR_MIB_SCRT_TKIP0,_VAL_,0,0xfff00000) #define SET_SCRT_TKIP_MIC_ERR(_VAL_) SET_REG(ADR_MIB_SCRT_TKIP1,_VAL_,0,0xfff00000) #define SET_SCRT_TKIP_RPLY(_VAL_) SET_REG(ADR_MIB_SCRT_TKIP2,_VAL_,0,0xfff00000) #define SET_SCRT_CCMP_RPLY(_VAL_) SET_REG(ADR_MIB_SCRT_CCMP0,_VAL_,0,0xfff00000) #define SET_SCRT_CCMP_CERR(_VAL_) SET_REG(ADR_MIB_SCRT_CCMP1,_VAL_,0,0xfff00000) #define SET_DBG_LEN_CRC_FAIL(_VAL_) SET_REG(ADR_DBG_LEN_CRC_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_LEN_ALC_FAIL(_VAL_) SET_REG(ADR_DBG_LEN_ALC_FAIL,_VAL_,0,0xffff0000) #define SET_DBG_AMPDU_PASS(_VAL_) SET_REG(ADR_DBG_AMPDU_PASS,_VAL_,0,0xffff0000) #define SET_DBG_AMPDU_FAIL(_VAL_) SET_REG(ADR_DBG_AMPDU_FAIL,_VAL_,0,0xffff0000) #define SET_RXID_ALC_CNT_FAIL(_VAL_) SET_REG(ADR_ID_ALC_FAIL1,_VAL_,0,0xffff0000) #define SET_RXID_ALC_LEN_FAIL(_VAL_) SET_REG(ADR_ID_ALC_FAIL2,_VAL_,0,0xffff0000) #define SET_VALID2(_VAL_) SET_REG(ADR_WSID2,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN2(_VAL_) SET_REG(ADR_WSID2,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE2(_VAL_) SET_REG(ADR_WSID2,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE2(_VAL_) SET_REG(ADR_WSID2,_VAL_,4,0xffffffcf) #define SET_PEER_MAC2_31_0(_VAL_) SET_REG(ADR_PEER_MAC2_0,_VAL_,0,0x00000000) #define SET_PEER_MAC2_47_32(_VAL_) SET_REG(ADR_PEER_MAC2_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_2_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_2_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_2_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_2_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_2_7,_VAL_,0,0xfffff000) #define SET_VALID3(_VAL_) SET_REG(ADR_WSID3,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN3(_VAL_) SET_REG(ADR_WSID3,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE3(_VAL_) SET_REG(ADR_WSID3,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE3(_VAL_) SET_REG(ADR_WSID3,_VAL_,4,0xffffffcf) #define SET_PEER_MAC3_31_0(_VAL_) SET_REG(ADR_PEER_MAC3_0,_VAL_,0,0x00000000) #define SET_PEER_MAC3_47_32(_VAL_) SET_REG(ADR_PEER_MAC3_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_3_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_3_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_3_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_3_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_3_7,_VAL_,0,0xfffff000) #define SET_VALID4(_VAL_) SET_REG(ADR_WSID4,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN4(_VAL_) SET_REG(ADR_WSID4,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE4(_VAL_) SET_REG(ADR_WSID4,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE4(_VAL_) SET_REG(ADR_WSID4,_VAL_,4,0xffffffcf) #define SET_PEER_MAC4_31_0(_VAL_) SET_REG(ADR_PEER_MAC4_0,_VAL_,0,0x00000000) #define SET_PEER_MAC4_47_32(_VAL_) SET_REG(ADR_PEER_MAC4_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_4_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_4_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_4_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_4_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_4_7,_VAL_,0,0xfffff000) #define SET_VALID5(_VAL_) SET_REG(ADR_WSID5,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN5(_VAL_) SET_REG(ADR_WSID5,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE5(_VAL_) SET_REG(ADR_WSID5,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE5(_VAL_) SET_REG(ADR_WSID5,_VAL_,4,0xffffffcf) #define SET_PEER_MAC5_31_0(_VAL_) SET_REG(ADR_PEER_MAC5_0,_VAL_,0,0x00000000) #define SET_PEER_MAC5_47_32(_VAL_) SET_REG(ADR_PEER_MAC5_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_5_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_5_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_5_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_5_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_5_7,_VAL_,0,0xfffff000) #define SET_VALID6(_VAL_) SET_REG(ADR_WSID6,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN6(_VAL_) SET_REG(ADR_WSID6,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE6(_VAL_) SET_REG(ADR_WSID6,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE6(_VAL_) SET_REG(ADR_WSID6,_VAL_,4,0xffffffcf) #define SET_PEER_MAC6_31_0(_VAL_) SET_REG(ADR_PEER_MAC6_0,_VAL_,0,0x00000000) #define SET_PEER_MAC6_47_32(_VAL_) SET_REG(ADR_PEER_MAC6_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_6_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_6_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_6_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_6_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_6_7,_VAL_,0,0xfffff000) #define SET_VALID7(_VAL_) SET_REG(ADR_WSID7,_VAL_,0,0xfffffffe) #define SET_PEER_QOS_EN7(_VAL_) SET_REG(ADR_WSID7,_VAL_,1,0xfffffffd) #define SET_PEER_OP_MODE7(_VAL_) SET_REG(ADR_WSID7,_VAL_,2,0xfffffff3) #define SET_PEER_HT_MODE7(_VAL_) SET_REG(ADR_WSID7,_VAL_,4,0xffffffcf) #define SET_PEER_MAC7_31_0(_VAL_) SET_REG(ADR_PEER_MAC7_0,_VAL_,0,0x00000000) #define SET_PEER_MAC7_47_32(_VAL_) SET_REG(ADR_PEER_MAC7_1,_VAL_,0,0xffff0000) #define SET_TX_ACK_POLICY_7_0(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_0,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_0(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_0,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_1(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_1,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_1(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_1,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_2(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_2,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_2(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_2,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_3(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_3,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_3(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_3,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_4(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_4,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_4(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_4,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_5(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_5,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_5(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_5,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_6(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_6,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_6(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_6,_VAL_,0,0xfffff000) #define SET_TX_ACK_POLICY_7_7(_VAL_) SET_REG(ADR_TX_ACK_POLICY_7_7,_VAL_,0,0xfffffffc) #define SET_TX_SEQ_CTRL_7_7(_VAL_) SET_REG(ADR_TX_SEQ_CTRL_7_7,_VAL_,0,0xfffff000) #define SET_RG_GEMINIA_HW_PINSEL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_HS_3WIRE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_MODE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_RX_GAIN_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_TXGAIN_PHYCTRL(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_RX_AGC(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_MODE(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_GEMINIA_CAL_INDEX(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_GEMINIA_RFG(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_PGAG(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,18,0xffc3ffff) #define SET_RG_GEMINIA_TX_GAIN(_VAL_) SET_REG(ADR_GEMINIA_3_WIRE_REGISTER,_VAL_,24,0x80ffffff) #define SET_RG_GEMINIA_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_EN_TX_TRSW(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_EN_RX_LNA(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_EN_RX_MIXER(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_EN_RX_DIV2(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_GEMINIA_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_EN_RX_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_EN_RX_TZ(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_RX_FILTER_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_EN_RX_FILTER(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_RX_ADC_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_EN_RX_ADC(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_GEMINIA_RX_RSSI_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_EN_RX_RSSI(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_TX_PA_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_EN_TX_PA(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_GEMINIA_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_EN_TX_MOD(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_TX_DAC_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_EN_TX_DAC(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_EN_TX_DIV2(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_TX_BT_PA_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_EN_TX_BT_PA(_VAL_) SET_REG(ADR_GEMINIA_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_EN_LDO_ABB(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_EN_LDO_ADC(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_EN_LDO_DAC(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_EN_IREF_RX(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_TX_DAC_CAL_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_EN_TX_DAC_CAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_GEMINIA_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_EN_RX_IQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_EN_TX_DPD(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_GEMINIA_RXRCCALQ_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_EN_TX_TSSI(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_EN_SARADC(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_EN_TX_VTOI_2ND(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_GEMINIA_TXLPF_BYPASS(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_TX_EN_VOLTAGE_IN(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_EN_TX_DAC_OUT(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_EN_TX_DAC_VOUT(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_RX_ABBOUT_TRI_STATE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_EN_RX_TESTNODE(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_EN_RX_PADSW(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_LDO_RX_FE_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_LDO_RX_ABB_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_LDO_RX_ADC_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_LDO_TX_DAC_EN_BYP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_EN_LDO_RX_ADC_IQUP(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TEST_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_GEMINIA_LDO_LEVEL_ABB(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,3,0xffffffc7) #define SET_RG_GEMINIA_LDO_LEVEL_ADC(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,6,0xfffffe3f) #define SET_RG_GEMINIA_LDO_LEVEL_DAC(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,9,0xfffff1ff) #define SET_RG_GEMINIA_SX_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_GEMINIA_SX_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,15,0xfffc7fff) #define SET_RG_GEMINIA_DP_LDO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,21,0xff1fffff) #define SET_RG_GEMINIA_SX_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_GEMINIA_SX_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_LDO_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_WF_RX_ABBCTUNEI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_RX_ABBCTUNEQ(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_GEMINIA_WF_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_WF_RX_FILTERI1ST(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_GEMINIA_WF_RX_FILTERI2ND(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_WF_RX_FILTERI3RD(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_GEMINIA_WF_RX_ABBCFIX(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_WF_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_WF_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_WF_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_WF_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_WF_RX_EN_LOOPA(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_WF_RX_FILTERVCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_GEMINIA_WF_RX_OUTVCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_GEMINIA_BT_RX_ABBCTUNEI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_RX_ABBCTUNEQ(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_GEMINIA_BT_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_BT_RX_FILTERI1ST(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_GEMINIA_BT_RX_FILTERI2ND(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_BT_RX_FILTERI3RD(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_GEMINIA_BT_RX_ABBCFIX(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_BT_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_BT_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_BT_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_BT_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_BT_RX_EN_LOOPA(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_BT_RX_FILTERVCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_GEMINIA_BT_RX_OUTVCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FILTER_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_GEMINIA_RX_ADCRSSI_VCM(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_RX_REC_LPFCORNER(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_RX_ADCRSSI_CLKSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_RSSI_CLOCK_GATING(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_TX_DPD_DIV(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_TX_TSSI_DIV(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_GEMINIA_TX_TSSI_TEST(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_GEMINIA_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_EN_RX_RSSI_TESTNODE(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,25,0xf1ffffff) #define SET_RG_GEMINIA_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_GEMINIA_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_GEMINIA_RX_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_WF_TXPGA_CAPSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_WF_TX_DIV_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_WF_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_GEMINIA_WF_TX_VDDSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_BT_TXPGA_CAPSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_GEMINIA_BT_TX_DIV_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_GEMINIA_BT_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_BT_TX_VDDSW(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_FE_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_WF_PACELL_EN(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_GEMINIA_WF_PABIAS_CTRL(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_WF_TX_PA1_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_GEMINIA_WF_TX_PA2_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_GEMINIA_WF_TX_PA3_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_BT_PA_CAPSEL(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_BT_PABIAS_2X(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_BT_PABIAS_CTRL(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_GEMINIA_BT_TX_PA_VCAS(_VAL_) SET_REG(ADR_GEMINIA_WBT_TX_PA_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_GEMINIA_TXPGA_MAIN(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_TXPGA_STEER(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_GEMINIA_TXMOD_GMCELL(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_TXLPF_GMCELL(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_GEMINIA_WF_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,16,0xfff0ffff) #define SET_RG_GEMINIA_BT_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_GEMINIA_TX_VTOI_CURRENT(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_GEMINIA_TX_VTOI_GM(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_GEMINIA_TX_VTOI_OPTION(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_GEMINIA_TX_VTOI_FS(_VAL_) SET_REG(ADR_GEMINIA_TX_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_WF_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_WF_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_WF_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_WF_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_WF_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_WF_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_WF_RX_HG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_WF_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_WF_RX_HG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_WF_RX_HG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_WF_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_WF_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_WF_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_WF_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_WF_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_WF_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_WF_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_WF_RX_MG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_WF_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_WF_RX_MG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_WF_RX_MG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_WF_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_WF_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_WF_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_WF_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_WF_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_WF_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_WF_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_WF_RX_LG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_WF_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_WF_RX_LG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_WF_RX_LG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_WF_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_WF_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_WF_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_WF_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_WF_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_WF_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_WF_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_WF_RX_ULG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_WF_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_WF_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_WF_RX_ULG_TZI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_WF_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_BT_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_BT_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_BT_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_BT_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_BT_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_BT_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_BT_RX_HG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_BT_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_BT_RX_HG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_BT_RX_HG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_BT_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_HG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_BT_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_BT_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_BT_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_BT_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_BT_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_BT_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_BT_RX_MG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_BT_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_BT_RX_MG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_BT_RX_MG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_BT_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_MG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_BT_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_BT_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_BT_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_BT_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_BT_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_BT_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_BT_RX_LG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_BT_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_BT_RX_LG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_BT_RX_LG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_BT_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_LG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_BT_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_BT_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_BT_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_BT_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_BT_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_BT_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_BT_RX_ULG_SQDC(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_BT_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_BT_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,25,0xf9ffffff) #define SET_RG_GEMINIA_BT_RX_ULG_TZI(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_BT_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_RX_ADC_CLKSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_RX_ADC_DNLEN(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_RX_ADC_METAEN(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_RX_ADC_TFLAG(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_RX_ADC_TSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_WF_RX_ADC_ICMP(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_GEMINIA_WF_RX_ADC_VCMI(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_GEMINIA_WF_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_BT_RX_ADC_ICMP(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_BT_RX_ADC_VCMI(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_GEMINIA_BT_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_GEMINIA_SARADC_VRSEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_GEMINIA_EN_SAR_TEST(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_GEMINIA_SARADC_THERMAL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_SARADC_TSSI(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_CLK_SAR_SEL(_VAL_) SET_REG(ADR_GEMINIA_RX_ADC_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_WF_TX_DACI1ST(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_WF_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_WF_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_GEMINIA_WF_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_GEMINIA_WF_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_GEMINIA_WF_TX_DAC_IATTN(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_WF_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_WF_TX_DAC_RCAL(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_WF_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_WF_TX_DAC_OS(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_WF_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_GEMINIA_WF_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_GEMINIA_TX_DAC_TSEL(_VAL_) SET_REG(ADR_GEMINIA_WIFI_TX_DAC_REGISTER,_VAL_,28,0x0fffffff) #define SET_RG_GEMINIA_BT_TX_DACI1ST(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_BT_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_BT_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_GEMINIA_BT_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_GEMINIA_BT_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_GEMINIA_BT_TX_DAC_IATTN(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_BT_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_BT_TX_DAC_RCAL(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_BT_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_BT_TX_DAC_OS(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_BT_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_GEMINIA_BT_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_GEMINIA_BT_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_GEMINIA_SX_EN_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_SX_EN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_EN_SX_CP_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_EN_SX_CP(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_EN_SX_DIV_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_EN_SX_DIV(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_EN_SX_VCO_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_EN_SX_VCO(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,7,0xffffff7f) #define SET_RG_GEMINIA_SX_PFD_RST_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_SX_PFD_RST(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_SX_UOP_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_SX_UOP_EN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_EN_VCOBF_TXMB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_EN_VCOBF_TXMB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_EN_VCOBF_TXOB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_EN_VCOBF_TXOB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,15,0xffff7fff) #define SET_RG_GEMINIA_EN_VCOBF_RXMB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_EN_VCOBF_RXMB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_EN_VCOBF_RXOB_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_EN_VCOBF_RXOB(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,19,0xfff7ffff) #define SET_RG_GEMINIA_EN_VCOBF_DIVCK_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_EN_VCOBF_DIVCK(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_SX_SBCAL_DIS(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_SX_SBCAL_AW(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_SX_AAC_DIS(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_SX_TTL_DIS(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_SX_CAL_INIT(_VAL_) SET_REG(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,29,0x1fffffff) #define SET_RG_GEMINIA_EN_SX_LDO_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_EN_LDO_CP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_EN_LDO_DIV(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_EN_LDO_LO(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_EN_LDO_VCO(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_EN_LDO_CP_BYP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_EN_LDO_DIV_BYP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_GEMINIA_EN_LDO_LO_BYP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_EN_LDO_VCO_PSW(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_EN_LDO_VCO_VDD33(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_EN_LDO_CP_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_EN_LDO_DIV_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_EN_LDO_LO_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_EN_LDO_VCO_IQUP(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_SX_LDO_FCOFFT(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_GEMINIA_LDO_CP_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_LDO_CP_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_LDO_DIV_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_LDO_DIV_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_LDO_LO_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_LDO_LO_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_LDO_VCO_FC_MAN(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_LDO_VCO_FC(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_LDO_VCO_RCF(_VAL_) SET_REG(ADR_GEMINIA_SX_LDO_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_GEMINIA_SX_RFCTRL_F(_VAL_) SET_REG(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000) #define SET_RG_GEMINIA_SX_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff) #define SET_RG_GEMINIA_SX_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,0,0xfffffff8) #define SET_RG_GEMINIA_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_SX_XTAL_FREQ(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,5,0xffffff9f) #define SET_RG_GEMINIA_SX_FREF_DOUB(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,7,0xffffff7f) #define SET_RG_GEMINIA_SX_BTRX_SIDE(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_SX_LO_TIMES(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_SX_CHANNEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE,_VAL_,11,0xfff807ff) #define SET_RG_GEMINIA_SX_CP_ISEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,0,0xfffffff0) #define SET_RG_GEMINIA_SX_CP_ISEL50U_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_SX_CP_KP_DOUB_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_SX_CP_ISEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,7,0xfffff87f) #define SET_RG_GEMINIA_SX_CP_ISEL50U_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_SX_CP_KP_DOUB_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_SX_CP_IOST_POL(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,15,0xffff7fff) #define SET_RG_GEMINIA_SX_CP_IOST(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_SX_PFD_SEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_SX_PFD_SET(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_SX_PFD_SET1(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_SX_PFD_SET2(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_SX_PFD_TRUP(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_SX_PFD_TRDN(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_SX_PFD_TLSEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_PFD_CHP_,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_SX_LPF_C1_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,0,0xfffffff0) #define SET_RG_GEMINIA_SX_LPF_C2_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_SX_LPF_C3_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_SX_LPF_R2_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,9,0xffffe1ff) #define SET_RG_GEMINIA_SX_LPF_R3_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,13,0xffff1fff) #define SET_RG_GEMINIA_SX_LPF_C1_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,16,0xfff0ffff) #define SET_RG_GEMINIA_SX_LPF_C2_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,20,0xff0fffff) #define SET_RG_GEMINIA_SX_LPF_C3_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_SX_LPF_R2_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,25,0xe1ffffff) #define SET_RG_GEMINIA_SX_LPF_R3_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_LPF,_VAL_,29,0x1fffffff) #define SET_RG_GEMINIA_SX_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_SX_VCO_ISEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,1,0xffffffe1) #define SET_RG_GEMINIA_SX_VCO_LPM_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_SX_VCO_VCCBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,6,0xfffffe3f) #define SET_RG_GEMINIA_SX_VCO_KVDOUB_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_SX_VCO_ISEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,10,0xffffc3ff) #define SET_RG_GEMINIA_SX_VCO_LPM_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_SX_VCO_VCCBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,15,0xfffc7fff) #define SET_RG_GEMINIA_SX_VCO_KVDOUB_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_SX_VCO_VARBSEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,21,0xff9fffff) #define SET_RG_GEMINIA_SX_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_SX_VCO_CS_AWH(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCO,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_VOBF_TXMBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_VOBF_TXOBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_VOBF_RXMBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,4,0xffffffcf) #define SET_RG_GEMINIA_VOBF_RXOBSEL_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,6,0xffffff3f) #define SET_RG_GEMINIA_VOBF_TXMBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,10,0xfffff3ff) #define SET_RG_GEMINIA_VOBF_TXOBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,12,0xffffcfff) #define SET_RG_GEMINIA_VOBF_RXMBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,14,0xffff3fff) #define SET_RG_GEMINIA_VOBF_RXOBSEL_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_VOBF_DIVBFSEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,19,0xfff7ffff) #define SET_RG_GEMINIA_SX_VCO_TXOB_AW(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_SX_VCO_RXOB_AW(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_VOBF_CAPIMB_POL(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_VOBF_CAPIMB(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,27,0xc7ffffff) #define SET_RG_GEMINIA_EN_SX_VCOMON(_VAL_) SET_REG(ADR_GEMINIA_SYN_VCOBF,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_SX_DIV_PREVDD(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,0,0xfffffff0) #define SET_RG_GEMINIA_SX_DIV_PSCVDD(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_SX_DIV_RST_H(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_SX_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_SX_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_EN_SX_MOD(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_EN_SX_DITHER(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_SX_MOD_ORDER(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,19,0xffe7ffff) #define SET_RG_GEMINIA_SX_DITHER_WEIGHT(_VAL_) SET_REG(ADR_GEMINIA_SYN_DIV_SDM,_VAL_,21,0xff9fffff) #define SET_RG_GEMINIA_SX_SUB_SEL_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_SX_SUB_SEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,1,0xfffffe01) #define SET_RG_GEMINIA_SX_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_SX_SBCAL_CT(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,10,0xfffff3ff) #define SET_RG_GEMINIA_SX_SBCAL_WT(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_SX_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_SX_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,15,0xffff7fff) #define SET_RG_GEMINIA_SX_SBCAL_NTARG(_VAL_) SET_REG(ADR_GEMINIA_SYN_SBCAL,_VAL_,16,0x0000ffff) #define SET_RG_GEMINIA_VO_AAC_TAR_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,0,0xfffffff0) #define SET_RG_GEMINIA_VO_AAC_IOST_BT(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,4,0xffffffcf) #define SET_RG_GEMINIA_VO_AAC_TAR_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,7,0xfffff87f) #define SET_RG_GEMINIA_VO_AAC_IOST_WF(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,11,0xffffe7ff) #define SET_RG_GEMINIA_VO_AAC_IMAX(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,14,0xfffc3fff) #define SET_RG_GEMINIA_VO_AAC_INIT(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,18,0xfff3ffff) #define SET_RG_GEMINIA_VO_AAC_EVA_TS(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,20,0xffcfffff) #define SET_RG_GEMINIA_VO_AAC_EN_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,23,0xff7fffff) #define SET_RG_GEMINIA_VO_AAC_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_VO_AAC_EVA_MAN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_VO_AAC_EVA(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_VO_AAC_TEST_EN(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_VO_AAC_TEST_SEL(_VAL_) SET_REG(ADR_GEMINIA_SYN_AAC,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_SX_TTL_INIT(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_SX_TTL_FPT(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_SX_TTL_CPT(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,4,0xffffffcf) #define SET_RG_GEMINIA_SX_TTL_ACCUM(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,7,0xfffffe7f) #define SET_RG_GEMINIA_SX_TTL_SUB(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,10,0xfffff3ff) #define SET_RG_GEMINIA_SX_TTL_SUB_INV(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_SX_TTL_VH(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,14,0xffff3fff) #define SET_RG_GEMINIA_SX_TTL_VL(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_SX_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_GEMINIA_SYN_TTL,_VAL_,19,0xfff7ffff) #define SET_RG_GEMINIA_DP_BBPLL_PD(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_DP_BBPLL_BP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_EN_DP_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_DP_FREF_DOUB(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_DP_DAC320_DIVBY2(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_DP_ADC320_DIVBY2_BT(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_DP_ADC320_DIVBY2_WF(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_EN_DPL_MOD(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_DPL_MOD_ORDER(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,9,0xfffff9ff) #define SET_RG_GEMINIA_DP_REFDIV(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,11,0xfffc07ff) #define SET_RG_GEMINIA_DP_FODIV(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,18,0xfe03ffff) #define SET_RG_GEMINIA_EN_LDO_DP_BYP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_EN_LDO_DP_IQUP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_DP_OD_TEST(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_DP_BBPLL_TESTSEL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_TOP_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_GEMINIA_DP_BBPLL_ICP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_DP_BBPLL_IDUAL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_GEMINIA_DP_CP_IOSTPOL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_DP_CP_IOST(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,5,0xffffff9f) #define SET_RG_GEMINIA_DP_PFD_PFDSEL(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_GEMINIA_DP_BBPLL_PFD_DLY(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_GEMINIA_DP_RP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,11,0xffffc7ff) #define SET_RG_GEMINIA_DP_RHP(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_GEMINIA_EN_DP_VT_MON(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_DP_VT_TH_HI(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_GEMINIA_DP_VT_TH_LO(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_GEMINIA_DP_BBPLL_BS(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,23,0xe07fffff) #define SET_RG_GEMINIA_DP_BBPLL_SDM_EDGE(_VAL_) SET_REG(ADR_GEMINIA_DPLL_CKT_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_DPL_RFCTRL_F(_VAL_) SET_REG(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS,_VAL_,0,0xff000000) #define SET_RG_GEMINIA_DPL_RFCTRL_CH(_VAL_) SET_REG(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS,_VAL_,24,0x00ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_WF_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_WF_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_GEMINIA_BT_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_BT_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_GEMINIA_SX_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_GEMINIA_TXDAC_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_TXRF_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_TXPA_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_RXRF_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff) #define SET_RG_GEMINIA_TXBTPA_DELAY(_VAL_) SET_REG(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1,_VAL_,20,0xff0fffff) #define SET_RG_GEMINIA_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_GEMINIA_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_GEMINIA_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_GEMINIA_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_GEMINIA_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_GEMINIA_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_GEMINIA_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_GEMINIA_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_GEMINIA_WF_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_GEMINIA_BT_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_GEMINIA_RX_RCCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_GEMINIA_TX_LOCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_GEMINIA_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_GEMINIA_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_GEMINIA_PGAG_RCCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,0,0xfffffff0) #define SET_RG_GEMINIA_PGAG_TXCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,4,0xffffff0f) #define SET_RG_GEMINIA_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,8,0xffff80ff) #define SET_RG_GEMINIA_RFG_RXIQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,16,0xfffcffff) #define SET_RG_GEMINIA_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,18,0xffc3ffff) #define SET_RG_GEMINIA_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0,_VAL_,22,0xe03fffff) #define SET_RG_GEMINIA_RFG_DPDCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_PGAG_DPDCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1,_VAL_,2,0xffffffc3) #define SET_RG_GEMINIA_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xffffe03f) #define SET_DB_GEMINIA_AD_ADC_I_OUT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,0,0xfffffc00) #define SET_DB_GEMINIA_AD_ADC_Q_OUT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,10,0xfff003ff) #define SET_DB_GEMINIA_AD_RX_RSSIADC(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,20,0xff0fffff) #define SET_DB_GEMINIA_DA_SARADC_BIT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,24,0xc0ffffff) #define SET_GEMINIA_SAR_ADC_FSM_RDY(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_ADC,_VAL_,30,0xbfffffff) #define SET_DB_GEMINIA_DA_SX_SUB_SEL(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,0,0xffffff00) #define SET_DB_GEMINIA_DA_SX_VCO_ISEL(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,9,0xffffe1ff) #define SET_DB_GEMINIA_VO_AAC_COMPOUT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,13,0xffffdfff) #define SET_DB_GEMINIA_SX_TTL_VT_DET(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,15,0xfffe7fff) #define SET_DB_GEMINIA_AD_DP_VT_MON_Q(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX1,_VAL_,29,0x9fffffff) #define SET_DB_GEMINIA_SX_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX2,_VAL_,0,0xffff0000) #define SET_DB_GEMINIA_SX_SBCAL_NTARGET(_VAL_) SET_REG(ADR_GEMINIA_READ_ONLY_FLAGS_SX2,_VAL_,16,0x0000ffff) #define SET_RG_GEMINIA_NFRAC_DELTA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0,_VAL_,0,0xff000000) #define SET_RG_GEMINIA_40M_MODE(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_LO_UP_CH(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R0,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,0,0xffffffe0) #define SET_RG_GEMINIA_RX_IQ_THETA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,8,0xffffe0ff) #define SET_RG_GEMINIA_RX_IQ_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_RXIQ_NOSHRK(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_RX_RSSIADC_TH(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,20,0xff0fffff) #define SET_RG_GEMINIA_RSSI_EDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_Q_INV(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_I_INV(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_IQ_SWAP(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_SIGN_SWAP(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R2,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,0,0xffffffe0) #define SET_RG_GEMINIA_TX_IQ_THETA(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,8,0xffffe0ff) #define SET_RG_GEMINIA_TX_IQ_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_TXIQ_NOSHRK(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R3,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_TX_FREQ_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,0,0xffff0000) #define SET_RG_GEMINIA_TONE_SCALE(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,16,0xfe00ffff) #define SET_RG_GEMINIA_TX_UP8X_MAN_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,27,0xf7ffffff) #define SET_RG_GEMINIA_DIS_DAC_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_EXT_DAC_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_DPLL_CLK320BY2(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_CBW_20_40(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R4,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_DAC_DC_Q(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R5,_VAL_,0,0xfffffc00) #define SET_RG_GEMINIA_DAC_DC_I(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R5,_VAL_,16,0xfc00ffff) #define SET_RG_GEMINIA_DAC_Q_SET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,0,0xfffffc00) #define SET_RG_GEMINIA_DAC_MAN_Q_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_DAC_I_SET(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,16,0xfc00ffff) #define SET_RG_GEMINIA_DAC_MAN_I_EN(_VAL_) SET_REG(ADR_GEMINIA_DIGITAL_ADD_ON_R6,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_BW20_HB_COEF_01(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R0,_VAL_,0,0xffffe000) #define SET_RG_GEMINIA_BW20_HB_COEF_00(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R0,_VAL_,16,0xe000ffff) #define SET_RG_GEMINIA_BW20_HB_COEF_03(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R1,_VAL_,0,0xffffe000) #define SET_RG_GEMINIA_BW20_HB_COEF_02(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R1,_VAL_,16,0xe000ffff) #define SET_RG_GEMINIA_BW20_HB_COEF_05(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R2,_VAL_,0,0xffffe000) #define SET_RG_GEMINIA_BW20_HB_COEF_04(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R2,_VAL_,16,0xe000ffff) #define SET_RG_GEMINIA_BW20_HB_COEF_07(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R3,_VAL_,0,0xffffe000) #define SET_RG_GEMINIA_BW20_HB_COEF_06(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R3,_VAL_,16,0xe000ffff) #define SET_RG_GEMINIA_BW20_HB_COEF_09(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R4,_VAL_,0,0xffffe000) #define SET_RG_GEMINIA_BW20_HB_COEF_08(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R4,_VAL_,16,0xe000ffff) #define SET_RG_GEMINIA_BW20_HB_COEF_11(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R5,_VAL_,0,0xffffe000) #define SET_RG_GEMINIA_BW20_HB_COEF_10(_VAL_) SET_REG(ADR_GEMINIA_TX_UP8X_COEF_R5,_VAL_,16,0xe000ffff) #define SET_RG_GEMINIA_PHASE_STEP_VALUE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,0,0xffff0000) #define SET_RG_GEMINIA_PHASE_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_ALPHA_SEL(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,20,0xffcfffff) #define SET_RG_GEMINIA_SPECTRUM_BW(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,24,0xfcffffff) #define SET_RG_GEMINIA_SPECTRUM_EN(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R0,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_RX_RCCAL_TARG(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,0,0xfffffc00) #define SET_RG_GEMINIA_RX_DC_POLAR_INV(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_RCCAL_POLAR_INV(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,13,0xffffdfff) #define SET_RO_GEMINIA_WF_DCCAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,16,0xfffeffff) #define SET_RO_GEMINIA_BT_DCCAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,17,0xfffdffff) #define SET_RO_GEMINIA_RCCAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,18,0xfffbffff) #define SET_RO_GEMINIA_TXDC_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,19,0xfff7ffff) #define SET_RO_GEMINIA_TXIQ_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,20,0xffefffff) #define SET_RO_GEMINIA_RXIQ_DONE(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R1,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_PHASE_17P5M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R2,_VAL_,0,0xffff0000) #define SET_RG_GEMINIA_PHASE_2P5M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R2,_VAL_,16,0x0000ffff) #define SET_RG_GEMINIA_PHASE_RXIQ_1M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R3,_VAL_,0,0xffff0000) #define SET_RG_GEMINIA_PHASE_1M(_VAL_) SET_REG(ADR_GEMINIA_RF_D_CAL_TOP_R3,_VAL_,16,0x0000ffff) #define SET_RG_GEMINIA_EN_LDO_XO_BYP(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_EN_LDO_XO_IQUP(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_XO_LDO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,2,0xffffffe3) #define SET_RG_GEMINIA_XO_CBANKI(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,5,0xffffe01f) #define SET_RG_GEMINIA_XO_CBANKO(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,13,0xffe01fff) #define SET_RG_GEMINIA_EN_FDB(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_FDB_BYPASS(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_FDB_DUTY_LTH(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,23,0xfe7fffff) #define SET_RG_GEMINIA_EN_XOTEST(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_1,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_EN_FDB_DCC_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_EN_FDB_DELAYC_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_EN_FDB_DELAYF_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_EN_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,3,0xfffffff7) #define SET_RG_GEMINIA_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_FDB_CDELAY_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_FDB_FDELAY_MUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,12,0xffff0fff) #define SET_RG_GEMINIA_XO_TIMMER(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,16,0xffc0ffff) #define SET_RG_GEMINIA_DPL_SETTLING_TIMMER(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,22,0xff3fffff) #define SET_RG_GEMINIA_FDB_RDELAYF(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,24,0xfcffffff) #define SET_RG_GEMINIA_FDB_RDELAYS(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,26,0xf3ffffff) #define SET_RG_GEMINIA_FDB_RECAL_TIMMER(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,28,0xcfffffff) #define SET_RG_GEMINIA_EN_FDB_RECAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_LOAD_RFTABLE_RDY(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_2,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_DCDC_MODE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_BUCK_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,1,0xfffffff1) #define SET_RG_GEMINIA_DLDO_LEVEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,4,0xffffff8f) #define SET_RG_GEMINIA_DLDO_BOOST_IQ(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_BUCK_EN_PSM(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_BUCK_PSM_VTH(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_BUCK_VREF_SEL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,11,0xfffff7ff) #define SET_RG_GEMINIA_LDO_LEVEL_EFUSE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,12,0xffff8fff) #define SET_RG_GEMINIA_EN_LDO_EFUSE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_DCDC_PULLLOW_CON(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_DCDC_RES2_CON(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,19,0xfff7ffff) #define SET_RG_GEMINIA_DCDC_RES_CON(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_RTC_RS1(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_RTC_RS2(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_DCDC_CLK(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_3,_VAL_,24,0xfcffffff) #define SET_RG_GEMINIA_RTC_OFFSET(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,0,0xffffff00) #define SET_RG_GEMINIA_RTC_CAL_TARGET_COUNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,8,0xfff000ff) #define SET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,20,0xc00fffff) #define SET_RG_GEMINIA_RTC_CAL_MODE(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_SEL_DPLL_CLK(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_4,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_5,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_EN_RTC_CAL(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_5,_VAL_,1,0xfffffffd) #define SET_RO_GEMINIA_RTC_OSC_RES_SW(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_6,_VAL_,16,0xfc00ffff) #define SET_RO_GEMINIA_RTC_OSC_CAL_RES_RDY(_VAL_) SET_REG(ADR_GEMINIA_PMU_REG_6,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_BT_CLK_SW(_VAL_) SET_REG(ADR_GEMINIA_PMU_BT_CLK,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_BT_CLK32K_CAL_DONE(_VAL_) SET_REG(ADR_GEMINIA_PMU_BT_CLK,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_SLEEP_WAKE_CNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_SLEEP_REG,_VAL_,0,0xff000000) #define SET_RG_GEMINIA_PMU_ENTER_SLEEP_MODE(_VAL_) SET_REG(ADR_GEMINIA_PMU_SLEEP_REG,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_RTC_EN(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_CLK_RTC_SW(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,1,0xfffffffd) #define SET_RO_GEMINIA_PMU_WAKE_TRIG_EVENT(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,12,0xffffcfff) #define SET_RO_GEMINIA_RTC_TICK_CNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_0,_VAL_,16,0x8000ffff) #define SET_RG_GEMINIA_RTC_INT_SEC_MASK(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_RTC_INT_ALARM_MASK(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,1,0xfffffffd) #define SET_RO_GEMINIA_RTC_INT_SEC(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,16,0xfffeffff) #define SET_RO_GEMINIA_RTC_INT_ALARM(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_1,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_RTC_SEC_START_CNT(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_2,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RTC_SEC_ALARM_VALUE(_VAL_) SET_REG(ADR_GEMINIA_PMU_RTC_REG_3,_VAL_,0,0x00000000) #define SET_RO_GEMINIA_FDB_CDELAY(_VAL_) SET_REG(ADR_GEMINIA_PMU_FDB_REG_0,_VAL_,20,0xff0fffff) #define SET_RO_GEMINIA_FDB_FDELAY(_VAL_) SET_REG(ADR_GEMINIA_PMU_FDB_REG_0,_VAL_,24,0xf0ffffff) #define SET_RO_GEMINIA_FDB_PHASESWAP(_VAL_) SET_REG(ADR_GEMINIA_PMU_FDB_REG_0,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_GPIO16_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_GPIO16_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_GPIO16_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_GPIO17_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_GPIO17_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_GPIO17_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_GPIO18_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_GPIO18_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_GPIO18_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_GPIO19_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_GPIO19_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_GPIO19_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_GPIO20_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_GPIO20_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_GPIO20_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_SPIS_MISO_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_FPGA_CLK_REF_40M_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_FPGA_CLK_REF_40M_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_FPGA_CLK_REF_40M_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_0,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_GPIO08_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_GPIO08_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_GPIO08_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_GPIO09_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_GPIO09_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_GPIO09_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_GPIO10_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_GPIO10_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_GPIO10_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_GPIO11_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_GPIO11_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_GPIO11_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_GPIO12_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_GPIO12_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_GPIO12_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_GPIO13_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_GPIO13_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_GPIO13_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_GPIO14_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_GPIO14_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_GPIO14_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_GPIO15_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_GPIO15_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_GPIO15_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_1,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_GPIO00_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,0,0xfffffffe) #define SET_RG_GEMINIA_GPIO00_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,1,0xfffffffd) #define SET_RG_GEMINIA_GPIO00_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,2,0xfffffffb) #define SET_RG_GEMINIA_GPIO01_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,4,0xffffffef) #define SET_RG_GEMINIA_GPIO01_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,5,0xffffffdf) #define SET_RG_GEMINIA_GPIO01_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,6,0xffffffbf) #define SET_RG_GEMINIA_GPIO02_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,8,0xfffffeff) #define SET_RG_GEMINIA_GPIO02_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,9,0xfffffdff) #define SET_RG_GEMINIA_GPIO02_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,10,0xfffffbff) #define SET_RG_GEMINIA_GPIO03_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,12,0xffffefff) #define SET_RG_GEMINIA_GPIO03_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,13,0xffffdfff) #define SET_RG_GEMINIA_GPIO03_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,14,0xffffbfff) #define SET_RG_GEMINIA_GPIO04_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,16,0xfffeffff) #define SET_RG_GEMINIA_GPIO04_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,17,0xfffdffff) #define SET_RG_GEMINIA_GPIO04_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,18,0xfffbffff) #define SET_RG_GEMINIA_GPIO05_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,20,0xffefffff) #define SET_RG_GEMINIA_GPIO05_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,21,0xffdfffff) #define SET_RG_GEMINIA_GPIO05_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,22,0xffbfffff) #define SET_RG_GEMINIA_GPIO06_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,24,0xfeffffff) #define SET_RG_GEMINIA_GPIO06_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,25,0xfdffffff) #define SET_RG_GEMINIA_GPIO06_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,26,0xfbffffff) #define SET_RG_GEMINIA_GPIO07_DS(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,28,0xefffffff) #define SET_RG_GEMINIA_GPIO07_PD(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,29,0xdfffffff) #define SET_RG_GEMINIA_GPIO07_OE(_VAL_) SET_REG(ADR_GEMINIA_IO_REG_2,_VAL_,30,0xbfffffff) #define SET_RG_GEMINIA_RF_PHY_MODE_SEL(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,0,0xfffffffc) #define SET_RG_GEMINIA_RF_PHY_MODE_WIFI_MAC(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,4,0xffffff8f) #define SET_RG_GEMINIA_PAD_MUX_SEL(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,8,0xfffff0ff) #define SET_RG_GEMINIA_MODE_LATCH_LMT(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,12,0xffff8fff) #define SET_RG_GEMINIA_EXT_MCU_PWRUP(_VAL_) SET_REG(ADR_GEMINIA_MCU_REG_0,_VAL_,31,0x7fffffff) #define SET_RG_GEMINIA_RAM_00(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_00,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_01(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_01,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_02(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_02,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_03(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_03,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_04(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_04,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_05(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_05,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_06(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_06,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_07(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_07,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_08(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_08,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_09(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_09,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_10(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_10,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_11(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_11,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_12(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_12,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_13(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_13,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_14(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_14,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_15(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_15,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_16(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_16,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_17(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_17,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_18(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_18,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_19(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_19,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_20(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_20,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_21(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_21,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_22(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_22,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_23(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_23,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_24(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_24,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_25(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_25,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_26(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_26,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_27(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_27,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_28(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_28,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_29(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_29,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_30(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_30,_VAL_,0,0x00000000) #define SET_RG_GEMINIA_RAM_31(_VAL_) SET_REG(ADR_GEMINIA_PMU_RAM_31,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_HW_PINSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_HS_3WIRE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_MODE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_RX_GAIN_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_TXGAIN_PHYCTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_RX_AGC(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_CAL_INDEX(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_RFG(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_PGAG(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,18,0xffc3ffff) #define SET_RG_TURISMO_TRX_BW_HT40(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_BW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_TX_GAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_REGISTER,_VAL_,24,0x80ffffff) #define SET_RG_TURISMO_TRX_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_EN_TX_TRSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_EN_RX_LNA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_EN_RX_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_EN_RX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_EN_RX_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_EN_RX_TZ(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_RX_FILTER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_EN_RX_FILTER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_RX_ADC_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_EN_RX_ADC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_RX_RSSI_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_EN_RX_RSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_TX_PA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_EN_TX_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_EN_TX_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_TX_DAC_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_EN_TX_DAC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_EN_TX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_TX_BT_PA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_EN_TX_BT_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_EN_IOT_ADC_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_EN_IOT_ADC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_EN_LDO_AFE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_IREF_RX(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_TX_DAC_CAL_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_EN_TX_DAC_CAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_EN_RX_IQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_TX_DPD(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_EN_TX_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_EN_SARADC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_EN_TX_VTOI_2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_TXLPF_BYPASS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_TX_EN_VOLTAGE_IN(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_EN_TX_DAC_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_EN_TX_DAC_VOUT(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_RX_ABBOUT_TRI_STATE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_EN_RX_TESTNODE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_EN_RX_PADSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_RX_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_LDO_LEVEL_AFE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_TURISMO_TRX_EN_LDO_RX_AFE_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_TX_PA_LDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_DP_LDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_EN_LDO_DP_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_SX_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_EN_LDO_CP_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_SX_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_TURISMO_TRX_EN_LDO_LO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_SX_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_TURISMO_TRX_SX_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_TURISMO_TRX_EN_LDO_DIV_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_LDO_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_WF_RX_ABBCTUNE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_WF_RX_FILTERI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_WF_RX_FILTERI2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_WF_RX_FILTERI3RD(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_WF_RX_ABBCFIX(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_WF_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_WF_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_WF_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_WF_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_WF_RX_EN_LOOPA(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_WF_RX_FILTERVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_TURISMO_TRX_WF_RX_OUTVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_TURISMO_TRX_WF_N_RX_ABBCTUNE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_WF_N_RX_FILTERI3RD(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_WF_N_RX_ABBCFIX(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_WF_N_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_WF_N_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_WF_N_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_WF_N_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_WF_N_RX_EN_LOOPA(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_WF_N_RX_FILTERVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_TURISMO_TRX_WF_N_RX_OUTVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_TURISMO_TRX_BT_RX_ABBCTUNE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_BT_RX_FILTERI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_BT_RX_FILTERI2ND(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_BT_RX_FILTERI3RD(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_BT_RX_ABBCFIX(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_BT_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_BT_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_BT_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_BT_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_BT_RX_EN_LOOPA(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_BT_RX_FILTERVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_TURISMO_TRX_BT_RX_OUTVCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_TURISMO_TRX_RX_ADCRSSI_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_RX_REC_LPFCORNER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_RX_ADCRSSI_CLKSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_RSSI_CLOCK_GATING(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_RX_IDACA_COARSE_PMOS_ON(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_TX_DPD_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_TX_TSSI_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_TX_TSSI_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_EN_RX_RSSI_TESTNODE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,25,0xf1ffffff) #define SET_RG_TURISMO_TRX_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_TURISMO_TRX_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_TURISMO_TRX_WF_TXPGA_CAPSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_WF_TX_DIV_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_WF_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_WF_TX_BTPASW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_WF_EN_TX_PA_VIN33(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_BT_TXPGA_CAPSW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_BT_TX_DIV_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_BT_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_BT_TX_BTPASW(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_BT_EN_TX_PA_VIN33(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_TX_PA_LDO_SEL_RES(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_EN_LDO_TX_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_EN_TX_PA_LDO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_EN_TX_PA_LDO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_EN_TX_PA_LDO_VTH(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_WF_PACELL_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_WF_PABIAS_CTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_WF_TX_PA1_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_WF_TX_PA2_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_WF_TX_PA3_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_BT_PABIAS_2X(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_BT_PABIAS_CTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_BT_TX_PA_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_TURISMO_TRX_BT_TX_MOD_CS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_TURISMO_TRX_TXPGA_MAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_TXPGA_STEER(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_TURISMO_TRX_TXMOD_GMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_TXLPF_GMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_WF_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_BT_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_TX_VTOI_CURRENT(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_TX_VTOI_GM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_TURISMO_TRX_TX_VTOI_OPTION(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_TURISMO_TRX_TX_VTOI_FS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_TX_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_WF_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_WF_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_WF_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_WF_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_WF_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_WF_RX_HG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_WF_RX_HG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_WF_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_WF_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_WF_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_WF_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_WF_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_WF_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_WF_RX_MG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_WF_RX_MG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_WF_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_WF_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_WF_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_WF_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_WF_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_WF_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_WF_RX_LG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_WF_RX_LG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_WF_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_WF_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_WF_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_BT_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_BT_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_BT_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_BT_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_BT_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_BT_RX_HG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_BT_RX_HG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_BT_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_BT_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_BT_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_BT_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_BT_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_BT_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_BT_RX_MG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_BT_RX_MG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_BT_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_BT_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_BT_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_BT_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_BT_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_BT_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_BT_RX_LG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_BT_RX_LG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_BT_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_BT_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_BT_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_RX_ADC_CLKSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_RX_ADC_DNLEN(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_RX_ADC_METAEN(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_RX_ADC_TFLAG(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_RX_ADC_TSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_WF_RX_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_WF_RX_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_WF_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_BT_RX_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_BT_RX_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_TURISMO_TRX_BT_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_SARADC_5G_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_SARADC_VRSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_EN_SAR_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_TURISMO_TRX_SARADC_THERMAL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_SARADC_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_CLK_SAR_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_TURISMO_TRX_WF_TX_DACI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_WF_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_WF_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_WF_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_TURISMO_TRX_WF_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_WF_TX_DAC_IATTN(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_WF_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_WF_TX_DAC_RCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_WF_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_WF_TX_DAC_OS(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_WF_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_WF_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_TX_DAC_TSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER,_VAL_,28,0x0fffffff) #define SET_RG_TURISMO_TRX_BT_TX_DACI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_BT_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_BT_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_BT_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_TURISMO_TRX_BT_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_BT_TX_DAC_IATTN(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_BT_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_BT_TX_DAC_RCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_BT_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_BT_TX_DAC_OS(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_BT_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_BT_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_SX_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SX_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_SX_CP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_EN_SX_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_EN_SX_DIV_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_EN_SX_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_EN_SX_VCO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_EN_SX_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_SX_PFD_RST_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_SX_PFD_RST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX_UOP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_SX_UOP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_VCOBF_TXMB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_EN_VCOBF_TXMB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_EN_VCOBF_TXOB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_EN_VCOBF_TXOB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_EN_VCOBF_RXMB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_EN_VCOBF_RXMB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_EN_VCOBF_RXOB_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_EN_VCOBF_RXOB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_EN_VCOBF_DIVCK_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_EN_VCOBF_DIVCK(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_SX_SBCAL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_SX_SBCAL_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_SX_AAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_SX_TTL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_SX_CAL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_EN_SX_LDO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_EN_LDO_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_LDO_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_EN_LDO_LO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_EN_LDO_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_EN_LDO_VCO_PSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_EN_LDO_VCO_VDD33(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_EN_LDO_CP_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_LDO_DIV_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_EN_LDO_LO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_EN_LDO_VCO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_SX_LDO_FCOFFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_LDO_CP_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_LDO_CP_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_LDO_DIV_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_LDO_DIV_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_LDO_LO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_LDO_LO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_LDO_VCO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_LDO_VCO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_LDO_VCO_RCF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_TURISMO_TRX_SX_RFCTRL_F(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000) #define SET_RG_TURISMO_TRX_SX_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff) #define SET_RG_TURISMO_TRX_SX_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_SX_XTAL_FREQ(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,5,0xffffff9f) #define SET_RG_TURISMO_TRX_SX_FREF_DOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_SX_BTRX_SIDE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_SX_LO_TIMES(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX_CHANNEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,11,0xfff807ff) #define SET_RG_TURISMO_TRX_SX_CP_ISEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SX_CP_ISEL50U_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_SX_CP_KP_DOUB_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_SX_CP_ISEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,7,0xfffff87f) #define SET_RG_TURISMO_TRX_SX_CP_ISEL50U_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_SX_CP_KP_DOUB_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_SX_CP_IOST_POL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_SX_CP_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_SX_PFD_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_SX_PFD_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_SX_PFD_SET1(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_SX_PFD_SET2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_SX_PFD_REF_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_SX_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_SX_PFD_TRUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_SX_PFD_TRDN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_SX_PFD_TLSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_SX_LPF_C1_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SX_LPF_C2_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_SX_LPF_C3_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_SX_LPF_R2_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,9,0xffffe1ff) #define SET_RG_TURISMO_TRX_SX_LPF_R3_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,13,0xffff1fff) #define SET_RG_TURISMO_TRX_SX_LPF_C1_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_SX_LPF_C2_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_SX_LPF_C3_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_SX_LPF_R2_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,25,0xe1ffffff) #define SET_RG_TURISMO_TRX_SX_LPF_R3_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_LPF,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_SX_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SX_VCO_ISEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,1,0xffffffe1) #define SET_RG_TURISMO_TRX_SX_VCO_LPM_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,6,0xfffffe3f) #define SET_RG_TURISMO_TRX_SX_VCO_KVDOUB_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX_VCO_ISEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,10,0xffffc3ff) #define SET_RG_TURISMO_TRX_SX_VCO_LPM_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_SX_VCO_VCCBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,15,0xfffc7fff) #define SET_RG_TURISMO_TRX_SX_VCO_KVDOUB_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SX_VCO_VARBSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,21,0xff9fffff) #define SET_RG_TURISMO_TRX_SX_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_SX_VCO_CS_AWH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCO,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_VOBF_TXMBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_VOBF_TXOBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_VOBF_RXMBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_VOBF_RXOBSEL_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,6,0xffffff3f) #define SET_RG_TURISMO_TRX_VOBF_TXMBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_VOBF_TXOBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_VOBF_RXMBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_VOBF_RXOBSEL_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_VOBF_DIVBFSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_SX_VCO_TXOB_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_SX_VCO_RXOB_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_VOBF_CAPIMB_POL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_VOBF_CAPIMB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,27,0xc7ffffff) #define SET_RG_TURISMO_TRX_EN_SX_VCOMON(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_VCOBF,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_SX_DIV_PREVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SX_DIV_PSCVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_SX_DIV_RST_H(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_SX_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_SX_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_EN_SX_DITHER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SX_MOD_ORDER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,19,0xffe7ffff) #define SET_RG_TURISMO_TRX_SX_DITHER_WEIGHT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM,_VAL_,21,0xff9fffff) #define SET_RG_TURISMO_TRX_SX_SUB_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SX_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,1,0xfffffe01) #define SET_RG_TURISMO_TRX_SX_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX_SBCAL_CT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_SX_SBCAL_WT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_SX_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_SX_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_SX_SBCAL_NTARG(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_SBCAL,_VAL_,16,0x0000ffff) #define SET_RG_TURISMO_TRX_VO_AAC_TAR_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_VO_AAC_IOST_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_VO_AAC_TAR_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,7,0xfffff87f) #define SET_RG_TURISMO_TRX_VO_AAC_IOST_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,11,0xffffe7ff) #define SET_RG_TURISMO_TRX_VO_AAC_IMAX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,14,0xfffc3fff) #define SET_RG_TURISMO_TRX_VO_AAC_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,18,0xfff3ffff) #define SET_RG_TURISMO_TRX_VO_AAC_EVA_TS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_VO_AAC_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_VO_AAC_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_VO_AAC_EVA_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_VO_AAC_EVA(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_VO_AAC_TEST_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_VO_AAC_TEST_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_AAC,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_SX_TTL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_SX_TTL_FPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_SX_TTL_CPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_SX_TTL_ACCUM(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,7,0xfffffe7f) #define SET_RG_TURISMO_TRX_SX_TTL_SUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_SX_TTL_SUB_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_SX_TTL_VH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_SX_TTL_VL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_SX_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_2_4GB_TTL,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_DP_BBPLL_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_DP_BBPLL_BP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_DP_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_DP_FREF_DOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_DP_DAC320_DIVBY2(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_BT(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_DP_ADC320_DIVBY2_WF(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_EN_DPL_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_DPL_MOD_ORDER(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,9,0xfffff9ff) #define SET_RG_TURISMO_TRX_DP_REFDIV(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,11,0xfffc07ff) #define SET_RG_TURISMO_TRX_DP_FODIV(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,18,0xfe03ffff) #define SET_RG_TURISMO_TRX_EN_LDO_DP_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_DP_OD_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_DP_BBPLL_TESTSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_TOP_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_TURISMO_TRX_DP_BBPLL_ICP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_DP_BBPLL_IDUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_DP_CP_IOSTPOL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_DP_CP_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,5,0xffffff9f) #define SET_RG_TURISMO_TRX_DP_PFD_PFDSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_DP_BBPLL_PFD_DLY(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_DP_RP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,11,0xffffc7ff) #define SET_RG_TURISMO_TRX_DP_RHP(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_EN_DP_VT_MON(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_DP_VT_TH_HI(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_TURISMO_TRX_DP_VT_TH_LO(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_DP_BBPLL_BS(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,23,0xe07fffff) #define SET_RG_TURISMO_TRX_DP_BBPLL_SDM_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_CKT_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_DPL_RFCTRL_F(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS,_VAL_,0,0xff000000) #define SET_RG_TURISMO_TRX_DPL_RFCTRL_CH(_VAL_) SET_REG(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS,_VAL_,24,0x00ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_WF_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_WF_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_BT_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_BT_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_SX_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_TXDAC_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_TXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_TXPA_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_RXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_TXBTPA_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_TURISMO_TRX_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_TURISMO_TRX_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_TURISMO_TRX_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_TURISMO_TRX_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_TURISMO_TRX_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_TURISMO_TRX_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_TURISMO_TRX_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_TURISMO_TRX_WF_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_BT_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_TURISMO_TRX_RX_RCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_TURISMO_TRX_RX_N_RCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_TURISMO_TRX_PGAG_RCCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_PGAG_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,8,0xffff80ff) #define SET_RG_TURISMO_TRX_RFG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,18,0xffc3ffff) #define SET_RG_TURISMO_TRX_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0,_VAL_,22,0xe03fffff) #define SET_RG_TURISMO_TRX_RFG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_PGAG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,2,0xffffffc3) #define SET_RG_TURISMO_TRX_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xffffe03f) #define SET_RG_TURISMO_TRX_IOT_ADC_CLKSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_IOT_ADC_DNLEN(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_IOT_ADC_METAEN(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_IOT_ADC_TFLAG(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_IOT_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_IOT_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_IOT_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_IOT_ADC_CLK_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,26,0xf3ffffff) #define SET_RG_TURISMO_TRX_IOT_ADC_CLK_SH_DUTY(_VAL_) SET_REG(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1,_VAL_,28,0xefffffff) #define SET_DB_TURISMO_TRX_AD_ADC_I_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,0,0xfffffc00) #define SET_DB_TURISMO_TRX_AD_ADC_Q_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,10,0xfff003ff) #define SET_DB_TURISMO_TRX_AD_RX_RSSIADC(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,20,0xff0fffff) #define SET_DB_TURISMO_TRX_DA_SARADC_BIT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,24,0xc0ffffff) #define SET_TURISMO_TRX_SAR_ADC_FSM_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC,_VAL_,30,0xbfffffff) #define SET_DB_TURISMO_TRX_DA_SX_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,0,0xffffff00) #define SET_DB_TURISMO_TRX_DA_SX_VCO_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,8,0xfffff0ff) #define SET_DB_TURISMO_TRX_VO_AAC_COMPOUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,12,0xffffefff) #define SET_DB_TURISMO_TRX_SX_TTL_VT_DET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,14,0xffff3fff) #define SET_DB_TURISMO_TRX_AD_DP_VT_MON_Q(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,16,0xfffcffff) #define SET_DB_TURISMO_TRX_AD_IOT_ADC_OUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,20,0xc00fffff) #define SET_DB_TURISMO_TRX_SX_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,0,0xffff0000) #define SET_DB_TURISMO_TRX_SX_SBCAL_NTARGET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,16,0x0000ffff) #define SET_RG_TURISMO_TRX_5G_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_5G_EN_TX_TRSW(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_5G_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_5G_EN_RX_LNA(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_5G_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_5G_EN_RX_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_5G_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_5G_EN_RX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_5G_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_5G_EN_RX_LOBUF(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_5G_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_5G_EN_RX_TZ(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_5G_TX_PA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_5G_EN_TX_PA(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_5G_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_5G_EN_TX_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_5G_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_5G_EN_TX_DIV2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_5G_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_5G_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_5G_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_5G_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_5G_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_5G_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_5G_EN_RX_IQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_5G_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_5G_EN_TX_DPD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_5G_EN_TX_TSSI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_5G_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_SX5GB_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_TURISMO_TRX_EN_LDO_5G_CP_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_SX5GB_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_LO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_SX5GB_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_SX5GB_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_DIV_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_5G_EN_IREF_RX(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_5G_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_5G_RX_SCA_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_5G_RX_SCA_MA(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,1,0xfffffff1) #define SET_RG_TURISMO_TRX_5G_RX_SCA_LOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,4,0xffffff8f) #define SET_RG_TURISMO_TRX_5G_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_5G_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_5G_RX_GM_IDB(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_5G_GM_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,13,0xffff9fff) #define SET_RG_TURISMO_TRX_5G_RX_DIV2_BUF(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_5G_RX_DIV2_CML(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,18,0xfff3ffff) #define SET_RG_TURISMO_TRX_5G_RX_DIV_CMLISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_5G_RX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_5G_RX_TZ_COURSE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_5G_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER1,_VAL_,28,0x0fffffff) #define SET_RG_TURISMO_TRX_5G_TX_DPD_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_5G_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,4,0xffffff8f) #define SET_RG_TURISMO_TRX_5G_TX_TSSI_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_5G_TX_TSSI_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_5G_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_5G_RX_ADC_ICMP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_5G_RX_ADC_VCMI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,18,0xfff3ffff) #define SET_RG_TURISMO_TRX_5G_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_REGISTER2,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_5G_TXPGA_CAPSW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_5G_TXPGA_CAPSW(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,1,0xfffffff1) #define SET_RG_TURISMO_TRX_5G_TX_ADDGMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_5G_PACELL_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,5,0xffffff1f) #define SET_RG_TURISMO_TRX_5G_PABIAS_CTRL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_5G_TX_PAFB_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_5G_TX_PA1_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,13,0xffff1fff) #define SET_RG_TURISMO_TRX_5G_TX_PA2_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_TX_PA3_VCAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_TURISMO_TRX_5G_TX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_5G_TX_DIV_CMLISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_5G_TX_DIV_CMLVSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_TURISMO_TRX_5G_TX_DIV_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_TURISMO_TRX_5G_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_FE_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_TURISMO_TRX_5G_TXPGA_MAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_TXPGA_STEER(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_TURISMO_TRX_5G_TXMOD_GMCELL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_5G_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_5G_TX_GAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_REGISTER,_VAL_,20,0xf80fffff) #define SET_RG_TURISMO_TRX_5G_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_5G_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_5G_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_5G_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_RX_HG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_5G_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_5G_RX_HG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_5G_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_5G_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_5G_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_5G_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_5G_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_RX_MG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_5G_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_5G_RX_MG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_5G_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_5G_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_5G_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_5G_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_5G_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_RX_LG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_5G_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_5G_RX_LG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_5G_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_5G_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_SQDC(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_TZI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_TURISMO_TRX_5G_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_5G_TX_DACI1ST(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_5G_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_TURISMO_TRX_5G_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_5G_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_TURISMO_TRX_5G_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_TURISMO_TRX_5G_TX_DAC_IATTN(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_5G_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_5G_TX_DAC_RCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_5G_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_5G_TX_DAC_OS(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_5G_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_SX5GB_RFCTRL_F(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000) #define SET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff) #define SET_RG_TURISMO_TRX_SX5GB_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_SX5GB_RFCH_MAP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_SX5GB_LO_TIMES(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_SX5GB_CHANNEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xffff00ff) #define SET_RG_TURISMO_TRX_SX_5GB_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SX_5GB_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_SX5GB_CP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_EN_SX5GB_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_EN_SX5GB_DIV_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_EN_SX5GB_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_EN_SX5GB_VCO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_EN_SX5GB_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_SX5GB_PFD_RST_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_RST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX5GB_UOP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_SX5GB_UOP_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_SX5GB_HSDIV_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_EN_SX5GB_HSDIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_SX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_EN_HSDIV_OBF_MX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_EN_SX_MIX_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_EN_SX_MIX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_EN_SX_REP_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_EN_SX_REP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_2ND_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_AW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_SX5GB_VOAAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_SX5GB_MIXAAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_SX5GB_REPAAC_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_SX5GB_CAL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,29,0x1fffffff) #define SET_RG_TURISMO_TRX_EN_SX5GB_LDO_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_EN_LDO_5G_CP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_LDO_5G_DIV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_EN_LDO_5G_LO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_PSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_VDD33(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_CP_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_DIV_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_LO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_EN_LDO_5G_VCO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_SX5GB_LDO_FCOFFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TURISMO_TRX_LDO_5G_CP_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_LDO_5G_CP_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TURISMO_TRX_LDO_5G_DIV_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_LDO_5G_DIV_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_LDO_5G_LO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_LDO_5G_LO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_LDO_5G_VCO_FC_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_LDO_5G_VCO_FC(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_LDO_5G_VCO_RCF(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_TURISMO_TRX_SX5GB_CP_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SX5GB_CP_ISEL50U(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_SX5GB_CP_KP_DOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_SX5GB_CP_IOST_POL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,7,0xffffff7f) #define SET_RG_TURISMO_TRX_SX5GB_CP_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_SET1(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_SET2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_TRUP(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_TRDN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_TLSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_REF_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_SX5GB_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_SX5GB_LPF_C1(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SX5GB_LPF_C2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_SX5GB_LPF_C3(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_SX5GB_LPF_R2(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,9,0xffffe1ff) #define SET_RG_TURISMO_TRX_SX5GB_LPF_R3(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,13,0xffff1fff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_FPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,18,0xfff3ffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_CPT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_ACCUM(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_SUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_SUB_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_VH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,27,0xe7ffffff) #define SET_RG_TURISMO_TRX_SX5GB_TTL_VL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,29,0x9fffffff) #define SET_RG_TURISMO_TRX_SX5GB_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LPF_TTL,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_SX5GB_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,1,0xffffffe1) #define SET_RG_TURISMO_TRX_SX5GB_VCO_VCCBSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,6,0xfffffe3f) #define SET_RG_TURISMO_TRX_SX5GB_VCO_KVDOUB(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX5GB_VCO_VARBSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,11,0xffffe7ff) #define SET_RG_TURISMO_TRX_SX5GB_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_SX5GB_VCO_CS_AWH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_HSDIV_INBFSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,15,0xfffe7fff) #define SET_RG_TURISMO_TRX_HSDIV_OBFMX_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_HSDIV_OBFSX_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_HSDIV_VRSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,19,0xffe7ffff) #define SET_RG_TURISMO_TRX_SXMIX_IBIAS_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,21,0xff9fffff) #define SET_RG_TURISMO_TRX_SXMIX_SWB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,23,0xfe7fffff) #define SET_RG_TURISMO_TRX_SXMIX_GMSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,25,0xf9ffffff) #define SET_RG_TURISMO_TRX_SXREP_SWB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,27,0xe7ffffff) #define SET_RG_TURISMO_TRX_SXREP_CSSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,29,0x9fffffff) #define SET_RG_TURISMO_TRX_EN_SX5GB_VCOMON(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_SX5GB_DIV_PREVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SX5GB_DIV_PSCVDD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_SX5GB_DIV_RST_H(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX5GB_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_SX5GB_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_EN_SX5GB_MOD(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_EN_SX5GB_DITHER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SX5GB_MOD_ORDER(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,19,0xffe7ffff) #define SET_RG_TURISMO_TRX_SX5GB_DITHER_WEIGHT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_DIV_SDM,_VAL_,21,0xff9fffff) #define SET_RG_TURISMO_TRX_SX5GB_SUB_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,1,0xfffffe01) #define SET_RG_TURISMO_TRX_SX5GB_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_CT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_WT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,15,0xffff7fff) #define SET_RG_TURISMO_TRX_SX5GB_SBCAL_NTARG(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_SBCAL,_VAL_,16,0x0000ffff) #define SET_RG_TURISMO_TRX_SX5GB_VOAAC_TAR(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_VO5GB_AAC_IOST(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_VO5GB_AAC_IMAX(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,6,0xfffffc3f) #define SET_RG_TURISMO_TRX_SX5GB_AAC_ACCUMH(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,10,0xfffff3ff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_ACCUML(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_INIT(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,14,0xffff3fff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_EVA_TS(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,16,0xfffcffff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_EVA_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_EVA(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_AAC5GB_TAR_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_AAC5GB_PDSW_EN_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_EN_AAC5GB_VOPDSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_EN_AAC5GB_MXPDSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_EN_AAC5GB_RPPDSW(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_TEST_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_SX5GB_AAC_TEST_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_SX5GB_MIXAAC_TAR(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_SXMIX_SCA_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,6,0xfffff03f) #define SET_RG_TURISMO_TRX_SX5GB_REPAAC_TAR(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,13,0xfffe1fff) #define SET_RG_TURISMO_TRX_SXREP_SCA_SEL_MAN(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION,_VAL_,19,0xfe07ffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff) #define SET_RG_TURISMO_TRX_5G_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_5G_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff) #define SET_RG_TURISMO_TRX_SX5GB_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_5G_TXDAC_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_5G_TXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_5G_TXPA_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_5G_RXRF_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_5G_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_TURISMO_TRX_5G_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_TURISMO_TRX_5G_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_TURISMO_TRX_5G_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_TURISMO_TRX_5G_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_TURISMO_TRX_5G_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_TURISMO_TRX_5G_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_TURISMO_TRX_5G_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_TURISMO_TRX_5G_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_5G_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TURISMO_TRX_5G_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_5G_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_5G_PGAG_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_5G_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,24,0x80ffffff) #define SET_RG_TURISMO_TRX_5G_PGAG_RCCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_5G_RFG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,4,0xffffffcf) #define SET_RG_TURISMO_TRX_5G_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xfffffc3f) #define SET_RG_TURISMO_TRX_5G_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,10,0xfffe03ff) #define SET_RG_TURISMO_TRX_5G_RFG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfff9ffff) #define SET_RG_TURISMO_TRX_5G_PGAG_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xff87ffff) #define SET_RG_TURISMO_TRX_5G_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,23,0xc07fffff) #define SET_DB_TURISMO_TRX_DA_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,0,0xffffff00) #define SET_DB_TURISMO_TRX_DA_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,8,0xfffff0ff) #define SET_DB_TURISMO_TRX_DA_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,13,0xfff81fff) #define SET_DB_TURISMO_TRX_DA_SXMIX_GMSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,19,0xffe7ffff) #define SET_DB_TURISMO_TRX_DA_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,21,0xf81fffff) #define SET_DB_TURISMO_TRX_DA_SXREP_CSSEL(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,27,0xe7ffffff) #define SET_DB_TURISMO_TRX_AD_SX5GB_AAC_COMPOUT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,29,0xdfffffff) #define SET_DB_TURISMO_TRX_SX5GB_TTL_VT_DET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,30,0x3fffffff) #define SET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A1(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,0,0xffffffc0) #define SET_DB_TURISMO_TRX_SXMIX_SCA_SEL_A2(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,7,0xffffe07f) #define SET_DB_TURISMO_TRX_SXREP_SCA_SEL_B1(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,14,0xfff03fff) #define SET_DB_TURISMO_TRX_SXREP_SCA_SEL_B2(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,21,0xf81fffff) #define SET_DB_TURISMO_TRX_SX5GB_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,0,0xffff0000) #define SET_DB_TURISMO_TRX_SX5GB_SBCAL_NTARGET(_VAL_) SET_REG(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,16,0x0000ffff) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_RX_SCAMA_STEP6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_RX_SCALOAD_STEP6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP0(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,0,0xfffffff0) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP1(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP2(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP3(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP4(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,16,0xfff0ffff) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP5(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_TX_CAPSW_STEP6(_VAL_) SET_REG(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_NFRAC_DELTA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0,_VAL_,0,0xff000000) #define SET_RG_TURISMO_TRX_40M_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_LO_UP_CH(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_BT_TRX_IF(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_1,_VAL_,16,0xf800ffff) #define SET_RG_TURISMO_TRX_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,0,0xffffffe0) #define SET_RG_TURISMO_TRX_RX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,8,0xffffe0ff) #define SET_RG_TURISMO_TRX_RX_IQ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_RXIQ_NOSHRK(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_RX_RSSIADC_TH(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,20,0xff0fffff) #define SET_RG_TURISMO_TRX_SUB_DC(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_IOT_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_RSSI_EDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_Q_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_I_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_IQ_SWAP(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_SIGN_SWAP(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,0,0xffffffe0) #define SET_RG_TURISMO_TRX_TX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,8,0xffffe0ff) #define SET_RG_TURISMO_TRX_TX_IQ_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_TXIQ_NOSHRK(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_TX_IQCAL_TIME(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_TX_FREQ_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,0,0xffff0000) #define SET_RG_TURISMO_TRX_TONE_SCALE(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,16,0xfe00ffff) #define SET_RG_TURISMO_TRX_BB_SIG_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_TONE_GEN_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_TX_UP8X_MAN_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_DIS_DAC_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_CLK_320M_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_DPLL_CLK320BY2(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_CBW_20_40(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_DAC_DC_Q(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5,_VAL_,0,0xfffffc00) #define SET_RG_TURISMO_TRX_DAC_DC_I(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5,_VAL_,16,0xfc00ffff) #define SET_RG_TURISMO_TRX_DAC_Q_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,0,0xfffffc00) #define SET_RG_TURISMO_TRX_DAC_MAN_Q_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_DAC_I_SET(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,16,0xfc00ffff) #define SET_RG_TURISMO_TRX_DAC_MAN_I_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_01(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00,_VAL_,0,0xffffe000) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_00(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00,_VAL_,16,0xe000ffff) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_03(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01,_VAL_,0,0xffffe000) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_02(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01,_VAL_,16,0xe000ffff) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_05(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02,_VAL_,0,0xffffe000) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_04(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02,_VAL_,16,0xe000ffff) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_07(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03,_VAL_,0,0xffffe000) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_06(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03,_VAL_,16,0xe000ffff) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_09(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04,_VAL_,0,0xffffe000) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_08(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04,_VAL_,16,0xe000ffff) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_11(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05,_VAL_,0,0xffffe000) #define SET_RG_TURISMO_TRX_BW20_HB_COEF_10(_VAL_) SET_REG(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05,_VAL_,16,0xe000ffff) #define SET_RG_TURISMO_TRX_PHASE_STEP_VALUE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,0,0xffff0000) #define SET_RG_TURISMO_TRX_PHASE_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_ALPHA_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,20,0xffcfffff) #define SET_RG_TURISMO_TRX_SPECTRUM_BW(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_SPECTRUM_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_0,_VAL_,28,0xefffffff) #define SET_RO_TURISMO_TRX_WF_DCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,16,0xfffeffff) #define SET_RO_TURISMO_TRX_BT_DCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,17,0xfffdffff) #define SET_RO_TURISMO_TRX_RCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,18,0xfffbffff) #define SET_RO_TURISMO_TRX_TXDC_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,19,0xfff7ffff) #define SET_RO_TURISMO_TRX_TXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,20,0xffefffff) #define SET_RO_TURISMO_TRX_RXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,21,0xffdfffff) #define SET_RO_TURISMO_TRX_5G_TXDC_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,22,0xffbfffff) #define SET_RO_TURISMO_TRX_5G_TXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,23,0xff7fffff) #define SET_RO_TURISMO_TRX_5G_RXIQ_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,24,0xfeffffff) #define SET_RO_TURISMO_TRX_5G_DCCAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,25,0xfdffffff) #define SET_RO_TURISMO_TRX_PRE_DC_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_1,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_PHASE_17P5M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_2,_VAL_,0,0xffff0000) #define SET_RG_TURISMO_TRX_PHASE_2P5M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_2,_VAL_,16,0x0000ffff) #define SET_RG_TURISMO_TRX_PHASE_RXIQ_1M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_3,_VAL_,0,0xffff0000) #define SET_RG_TURISMO_TRX_PHASE_1M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_3,_VAL_,16,0x0000ffff) #define SET_RG_TURISMO_TRX_PHASE_PADPD(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_4,_VAL_,0,0xffff0000) #define SET_RG_TURISMO_TRX_PHASE_35M(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_4,_VAL_,16,0x0000ffff) #define SET_RO_TURISMO_TRX_RX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,0,0xffffffe0) #define SET_RO_TURISMO_TRX_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,8,0xffffe0ff) #define SET_RO_TURISMO_TRX_TX_IQ_THETA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,16,0xffe0ffff) #define SET_RO_TURISMO_TRX_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_5,_VAL_,24,0xe0ffffff) #define SET_RG_TURISMO_TRX_RX_RCCAL_TARG(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,0,0xfffffc00) #define SET_RG_TURISMO_TRX_RX_DC_POLAR_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_RCCAL_POLAR_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_RX_DC_RESOLUTION(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_RX_RCCAL_40M_TARG(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_6,_VAL_,16,0xfc00ffff) #define SET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_39_32(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_7,_VAL_,0,0xffffff00) #define SET_RG_TURISMO_TRX_SPECTRUM_LO_FIX(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_7,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_SPECTRUM_PWR_UPDATE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_7,_VAL_,20,0xffefffff) #define SET_RO_TURISMO_TRX_SPECTRUM_IQ_PWR_31_0(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_8,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_PROC_DELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_PRE_DC_POLA_INV(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_RX_PRE_DC_RESOLUTION(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_PRE_DC_AUTO(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_CAL_TOP_9,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_HS3W_TX_RF_GAIN(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,0,0xffffff80) #define SET_RG_TURISMO_TRX_HS3W_PGAGC(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_HS3W_RFGC(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,12,0xffffcfff) #define SET_RG_TURISMO_TRX_HS3W_RXAGC(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_HS3W_RF_PHY_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_HS3W_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_HS3W_COMM_DATA(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,24,0xf8ffffff) #define SET_RG_TURISMO_TRX_HS3W_START_SENT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL1,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_10_8(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL2,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_HS3W_SX_RFCH_MAP_EN_INT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL2,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_HS3W_SX_CHANNEL_INT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL2,_VAL_,11,0xfff807ff) #define SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_F_INT(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL3,_VAL_,0,0xff000000) #define SET_RG_TURISMO_TRX_HS3W_SX_RFCTRL_CH_INT_7_0(_VAL_) SET_REG(ADR_TURISMO_TRX_HS3W_CTRL3,_VAL_,24,0x00ffffff) #define SET_RG_TURISMO_TRX_MODE_BY_HS_3WIRE(_VAL_) SET_REG(ADR_TURISMO_TRX_RF_D_MODE_CTRL,_VAL_,0,0xfffffffe) #define SET_RO_TURISMO_TRX_DC_CAL_Q(_VAL_) SET_REG(ADR_TURISMO_TRX_RX_DC_CAL_RESULT,_VAL_,0,0xffffff80) #define SET_RO_TURISMO_TRX_DC_CAL_I(_VAL_) SET_REG(ADR_TURISMO_TRX_RX_DC_CAL_RESULT,_VAL_,16,0xff80ffff) #define SET_RG_TURISMO_TRX_XO_LDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,0,0xfffffff8) #define SET_RG_TURISMO_TRX_EN_LDO_XO_IQUP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_EN_LDO_XO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_EN_DLDO_BYP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_XO_CBANKI(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,8,0xfffe00ff) #define SET_RG_TURISMO_TRX_XO_CBANKO(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,17,0xfc01ffff) #define SET_RG_TURISMO_TRX_EN_FDB(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_FDB_BYPASS(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,27,0xf7ffffff) #define SET_RG_TURISMO_TRX_FDB_DUTY_LTH(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,28,0xcfffffff) #define SET_RG_TURISMO_TRX_EN_XOTEST(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_1,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_EN_FDB_DCC_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_EN_FDB_DELAYC_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_EN_FDB_DELAYF_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_EN_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,3,0xfffffff7) #define SET_RG_TURISMO_TRX_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_FDB_CDELAY_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_FDB_FDELAY_MUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,12,0xffff0fff) #define SET_RG_TURISMO_TRX_XO_TIMMER(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,16,0xffc0ffff) #define SET_RG_TURISMO_TRX_DPL_SETTLING_TIMMER(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,22,0xff3fffff) #define SET_RG_TURISMO_TRX_FDB_RDELAYF(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,24,0xfcffffff) #define SET_RG_TURISMO_TRX_FDB_RDELAYS(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,26,0xf3ffffff) #define SET_RG_TURISMO_TRX_FDB_RECAL_TIMMER(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,28,0xcfffffff) #define SET_RG_TURISMO_TRX_EN_FDB_RECAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_LOAD_RFTABLE_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_2,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_DCDC_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_DLDO_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,1,0xfffffff1) #define SET_RG_TURISMO_TRX_BUCK_LEVEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,4,0xffffff0f) #define SET_RG_TURISMO_TRX_DLDO_BOOST_IQ(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_BUCK_EN_PSM(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_BUCK_PSM_VTH(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_BUCK_VREF_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,11,0xfffff7ff) #define SET_RG_TURISMO_TRX_LDO_LEVEL_EFUSE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_EN_LDO_EFUSE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_DCDC_PULLLOW_CON(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_DCDC_RES2_CON(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,19,0xfff7ffff) #define SET_RG_TURISMO_TRX_DCDC_RES_CON(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_RTC_RS1(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_RTC_RS2(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_DCDC_CLK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,24,0xf0ffffff) #define SET_RG_TURISMO_TRX_BUCK_RCZERO(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_BUCK_SLOP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_3,_VAL_,29,0x9fffffff) #define SET_RG_TURISMO_TRX_RTC_OFFSET(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,0,0xffffff00) #define SET_RG_TURISMO_TRX_RTC_CAL_TARGET_COUNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,8,0xfff000ff) #define SET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,20,0xc00fffff) #define SET_RG_TURISMO_TRX_RTC_CAL_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_SEL_DPLL_CLK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_4,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_5,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_EN_RTC_CAL(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_5,_VAL_,1,0xfffffffd) #define SET_RO_TURISMO_TRX_FDB_CDELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,0,0xfffffff0) #define SET_RO_TURISMO_TRX_FDB_FDELAY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,4,0xffffff0f) #define SET_RO_TURISMO_TRX_FDB_PHASESWAP(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,8,0xfffffeff) #define SET_RO_TURISMO_TRX_XO_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,9,0xfffffdff) #define SET_RO_TURISMO_TRX_RTC_OSC_CAL_RES_RDY(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,10,0xfffffbff) #define SET_RO_TURISMO_TRX_RTC_OSC_RES_SW(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_REG_6,_VAL_,11,0xffe007ff) #define SET_RG_TURISMO_TRX_PMU_ENTER_SLEEP_MODE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_SLEEP_METHOD(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_1,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_INT_PMU_MASK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_1,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_SLEEP_WAKE_CNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_SLEEP_REG_2,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_SEC_CNT_VALUE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_0,_VAL_,0,0xffff8000) #define SET_RG_TURISMO_TRX_RTC_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_0,_VAL_,15,0xffff7fff) #define SET_RO_TURISMO_TRX_RTC_TICK_CNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_0,_VAL_,16,0x8000ffff) #define SET_RG_TURISMO_TRX_RTC_INT_SEC_MASK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_RTC_INT_ALARM_MASK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,1,0xfffffffd) #define SET_RO_TURISMO_TRX_PMU_WAKE_TRIG_EVENT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,12,0xffff8fff) #define SET_RO_TURISMO_TRX_RTC_INT_SEC(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,16,0xfffeffff) #define SET_RO_TURISMO_TRX_RTC_INT_ALARM(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_1,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_RTC_SEC_START_CNT(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_2,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RTC_SEC_ALARM_VALUE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RTC_REG_3,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_EN(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_CTRL_REG,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_CLK_RTC_SW(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_CTRL_REG,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_PHY_RST_N(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_CTRL_REG,_VAL_,4,0xffffffef) #define SET_RO_TURISMO_TRX_PMU_STATE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_STATE_REG,_VAL_,0,0xfffffff8) #define SET_RO_TURISMO_TRX_AD_VBAT_OK(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_STATE_REG,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_BT_CLK_SW(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_BT_CLK,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_BT_CLK32K_CAL_DONE(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_BT_CLK,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_GPIO16_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_GPIO16_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_GPIO16_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_GPIO17_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_GPIO17_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_GPIO17_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_GPIO18_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_GPIO18_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_GPIO18_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_GPIO19_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_GPIO19_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_GPIO19_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_GPIO20_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_GPIO20_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_GPIO20_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_SPIS_MISO_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_FPGA_CLK_REF_40M_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_0,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_GPIO08_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_GPIO08_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_GPIO08_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_GPIO09_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_GPIO09_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_GPIO09_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_GPIO10_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_GPIO10_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_GPIO10_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_GPIO11_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_GPIO11_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_GPIO11_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_GPIO12_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_GPIO12_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_GPIO12_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_GPIO13_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_GPIO13_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_GPIO13_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_GPIO14_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_GPIO14_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_GPIO14_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_GPIO15_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_GPIO15_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_GPIO15_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_1,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_GPIO00_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,0,0xfffffffe) #define SET_RG_TURISMO_TRX_GPIO00_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,1,0xfffffffd) #define SET_RG_TURISMO_TRX_GPIO00_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,2,0xfffffffb) #define SET_RG_TURISMO_TRX_GPIO01_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,4,0xffffffef) #define SET_RG_TURISMO_TRX_GPIO01_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,5,0xffffffdf) #define SET_RG_TURISMO_TRX_GPIO01_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,6,0xffffffbf) #define SET_RG_TURISMO_TRX_GPIO02_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,8,0xfffffeff) #define SET_RG_TURISMO_TRX_GPIO02_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,9,0xfffffdff) #define SET_RG_TURISMO_TRX_GPIO02_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,10,0xfffffbff) #define SET_RG_TURISMO_TRX_GPIO03_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,12,0xffffefff) #define SET_RG_TURISMO_TRX_GPIO03_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,13,0xffffdfff) #define SET_RG_TURISMO_TRX_GPIO03_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,14,0xffffbfff) #define SET_RG_TURISMO_TRX_GPIO04_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,16,0xfffeffff) #define SET_RG_TURISMO_TRX_GPIO04_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,17,0xfffdffff) #define SET_RG_TURISMO_TRX_GPIO04_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,18,0xfffbffff) #define SET_RG_TURISMO_TRX_GPIO05_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,20,0xffefffff) #define SET_RG_TURISMO_TRX_GPIO05_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,21,0xffdfffff) #define SET_RG_TURISMO_TRX_GPIO05_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,22,0xffbfffff) #define SET_RG_TURISMO_TRX_GPIO06_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,24,0xfeffffff) #define SET_RG_TURISMO_TRX_GPIO06_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,25,0xfdffffff) #define SET_RG_TURISMO_TRX_GPIO06_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,26,0xfbffffff) #define SET_RG_TURISMO_TRX_GPIO07_DS(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,28,0xefffffff) #define SET_RG_TURISMO_TRX_GPIO07_PD(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,29,0xdfffffff) #define SET_RG_TURISMO_TRX_GPIO07_OE(_VAL_) SET_REG(ADR_TURISMO_TRX_IO_REG_2,_VAL_,30,0xbfffffff) #define SET_RG_TURISMO_TRX_RF_PHY_MODE_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,0,0xfffffffc) #define SET_RG_TURISMO_TRX_RF_PHY_MODE_WIFI_MAC(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,4,0xffffff8f) #define SET_RG_TURISMO_TRX_PAD_MUX_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,8,0xfffff0ff) #define SET_RG_TURISMO_TRX_MODE_LATCH_LMT(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,12,0xffff8fff) #define SET_RG_TURISMO_TRX_CLK_MON_SEL(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,16,0xfff8ffff) #define SET_RG_TURISMO_TRX_EXT_MCU_PWRUP(_VAL_) SET_REG(ADR_TURISMO_TRX_MCU_REG_0,_VAL_,31,0x7fffffff) #define SET_RG_TURISMO_TRX_RAM_00(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_00,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_01(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_01,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_02(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_02,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_03(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_03,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_04(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_04,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_05(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_05,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_06(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_06,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_07(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_07,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_08(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_08,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_09(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_09,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_10(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_10,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_11(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_11,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_12(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_12,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_13(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_13,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_14(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_14,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_15(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_15,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_16(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_16,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_17(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_17,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_18(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_18,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_19(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_19,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_20(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_20,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_21(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_21,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_22(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_22,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_23(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_23,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_24(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_24,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_25(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_25,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_26(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_26,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_27(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_27,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_28(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_28,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_29(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_29,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_30(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_30,_VAL_,0,0x00000000) #define SET_RG_TURISMO_TRX_RAM_31(_VAL_) SET_REG(ADR_TURISMO_TRX_PMU_RAM_31,_VAL_,0,0x00000000) #define SET_RG_HW_PINSEL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_HS_3WIRE_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_MODE_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_5G_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_RX_GAIN_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_TX_GAIN_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_TXGAIN_PHYCTRL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_RX_AGC(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_MODE(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_CAL_INDEX(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_RFG(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_PGAG(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,18,0xffc3ffff) #define SET_RG_BW_HT40(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_BW_MANUAL(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TX_GAIN(_VAL_) SET_REG(ADR_MODE_REGISTER,_VAL_,24,0x80ffffff) #define SET_RG_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_EN_TX_TRSW(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_EN_RX_LNA(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_EN_RX_MIXER(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_EN_RX_DIV2(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_EN_RX_LOBUF(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_EN_RX_TZ(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_RX_FILTER_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_EN_RX_FILTER(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_RX_ADC_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_EN_RX_ADC(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_RX_RSSI_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_EN_RX_RSSI(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TX_PA_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_EN_TX_PA(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_EN_TX_MOD(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_TX_DAC_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_EN_TX_DAC(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_EN_TX_DIV2(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_TX_BT_PA_MANUAL(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_EN_TX_BT_PA(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_EN_IOT_ADC_BUF(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_EN_IOT_ADC(_VAL_) SET_REG(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_EN_LDO_AFE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_EN_IREF_RX(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_TX_DAC_CAL_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_EN_TX_DAC_CAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_EN_RX_IQCAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_EN_TX_DPD(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_EN_TX_TSSI(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_EN_SARADC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_EN_TX_VTOI_2ND(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_TXLPF_BYPASS(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_TX_EN_VOLTAGE_IN(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_EN_TX_DAC_OUT(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_EN_TX_DAC_VOUT(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_RX_ABBOUT_TRI_STATE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_EN_RX_TESTNODE(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_EN_RX_PADSW(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_EN_LDO_RX_AFE_FC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_EN_LDO_RX_AFE_IQUP(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_RX_SQDC(_VAL_) SET_REG(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_LDO_LEVEL_AFE(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_EN_LDO_RX_AFE_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_SX_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_EN_LDO_CP_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_SX_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_EN_LDO_LO_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_SX_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_SX_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_EN_LDO_DIV_BYP(_VAL_) SET_REG(ADR_2_4G_LDO_REGISTER,_VAL_,31,0x7fffffff) #define SET_RG_WF_RX_ABBCTUNE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_WF_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_WF_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_WF_RX_FILTERI1ST(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_WF_RX_FILTERI2ND(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_WF_RX_FILTERI3RD(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_WF_RX_ABBCFIX(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_WF_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_WF_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_WF_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_WF_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_WF_RX_EN_LOOPA(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_WF_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_WF_RX_FILTERVCM(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_WF_RX_OUTVCM(_VAL_) SET_REG(ADR_WIFI_HT20_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_WF_N_RX_ABBCTUNE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_WF_N_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_WF_N_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_WF_N_RX_FILTERI1ST(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_WF_N_RX_FILTERI2ND(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_WF_N_RX_FILTERI3RD(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_WF_N_RX_ABBCFIX(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_WF_N_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_WF_N_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_WF_N_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_WF_N_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_WF_N_RX_EN_LOOPA(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_WF_N_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_WF_N_RX_FILTERVCM(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_WF_N_RX_OUTVCM(_VAL_) SET_REG(ADR_WIFI_HT40_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_BT_RX_ABBCTUNE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_BT_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_BT_RX_FILTERI_COARSE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_BT_RX_FILTERI1ST(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_BT_RX_FILTERI2ND(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_BT_RX_FILTERI3RD(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_BT_RX_ABBCFIX(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,16,0xfffeffff) #define SET_RG_BT_RX_ABB_N_MODE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,17,0xfffdffff) #define SET_RG_BT_RX_ABB_BT_MODE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_BT_RX_ABB_IDIV3(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_BT_RX_EN_IDACA_COARSE(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_BT_RX_EN_LOOPA(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_BT_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_BT_RX_FILTERVCM(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_BT_RX_OUTVCM(_VAL_) SET_REG(ADR_BT_RX_FILTER_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_RX_ADCRSSI_VCM(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_RX_REC_LPFCORNER(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_RX_ADCRSSI_CLKSEL(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_RSSI_CLOCK_GATING(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_RX_IDACA_COARSE_PMOS_ON(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_TX_DPD_DIV(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_TX_TSSI_DIV(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_TX_TSSI_TEST(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_EN_RX_RSSI_TESTNODE(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,25,0xf1ffffff) #define SET_RG_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_2_4G_RX_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_WF_TXPGA_CAPSW(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_WF_TX_DIV_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_WF_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_WF_TXMOD_GMCELL_FINE(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_BT_TXPGA_CAPSW(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_BT_TX_DIV_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_BT_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_BT_TXMOD_GMCELL_FINE(_VAL_) SET_REG(ADR_2_4G_TX_FE_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_WF_PACELL_EN(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_WF_PABIAS_CTRL(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_WF_TX_PA1_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_WF_TX_PA2_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_WF_TX_PA3_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_WF_BTPASW(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_BTRX_BTPASW(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_BTTX_BTPASW(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_BT_PABIAS_2X(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_BT_PABIAS_CTRL(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_BT_TX_PA_VCAS(_VAL_) SET_REG(ADR_2_4G_TX_PA_REGISTER,_VAL_,28,0x8fffffff) #define SET_RG_TXPGA_MAIN(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_TXPGA_STEER(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_TXMOD_GMCELL(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_TXLPF_GMCELL(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_WF_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,16,0xfff0ffff) #define SET_RG_BT_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_TX_VTOI_CURRENT(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_TX_VTOI_GM(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_TX_VTOI_OPTION(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_TX_VTOI_FS(_VAL_) SET_REG(ADR_2_4G_TX_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_WF_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_WF_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_WF_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_WF_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_WF_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_WF_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_WF_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_WF_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_WF_RX_HG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_WF_RX_HG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_WF_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_WF_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_WF_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_WF_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_WF_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_WF_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_WF_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_WF_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_WF_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_WF_RX_MG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_WF_RX_MG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_WF_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_WF_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_WF_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_WF_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_WF_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_WF_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_WF_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_WF_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_WF_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_WF_RX_LG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_WF_RX_LG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_WF_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_WF_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_WF_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_WF_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_WF_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_WF_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_WF_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_WF_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_WF_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_WF_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_WF_RX_ULG_TZI(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_WF_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_2_4G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_BT_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_BT_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_BT_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_BT_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_BT_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_BT_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_BT_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_BT_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_BT_RX_HG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_BT_RX_HG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_BT_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_BT_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_BT_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_BT_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_BT_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_BT_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_BT_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_BT_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_BT_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_BT_RX_MG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_BT_RX_MG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_BT_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_BT_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_BT_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_BT_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_BT_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_BT_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_BT_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_BT_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_BT_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_BT_RX_LG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_BT_RX_LG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_BT_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_BT_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_BT_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_BT_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_BT_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_BT_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_BT_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_BT_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_BT_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_BT_RX_ULG_LOBUF(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_BT_RX_ULG_TZI(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_BT_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_BT_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_RX_ADC_CLKSEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_RX_ADC_DNLEN(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_RX_ADC_METAEN(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_RX_ADC_TFLAG(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_RX_ADC_TSEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_WF_RX_ADC_ICMP(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_WF_RX_ADC_VCMI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,10,0xfffff3ff) #define SET_RG_WF_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_WF_RX_ADC_PSW(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_BT_RX_ADC_ICMP(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,16,0xfffcffff) #define SET_RG_BT_RX_ADC_VCMI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,18,0xfff3ffff) #define SET_RG_BT_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,20,0xffcfffff) #define SET_RG_BT_RX_ADC_PSW(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_SARADC_5G_TSSI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_SARADC_VRSEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_EN_SAR_TEST(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_SARADC_THERMAL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_SARADC_TSSI(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_CLK_SAR_SEL(_VAL_) SET_REG(ADR_WBT_RX_ADC_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_WF_TX_DACI1ST(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_WF_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_WF_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_WF_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_WF_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_WF_TX_DAC_IATTN(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_WF_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_WF_TX_DAC_RCAL(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_WF_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_WF_TX_DAC_OS(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_WF_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_WF_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_TX_DAC_TSEL(_VAL_) SET_REG(ADR_WIFI_TX_DAC_REGISTER,_VAL_,28,0x0fffffff) #define SET_RG_BT_TX_DACI1ST(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_BT_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_BT_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_BT_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_BT_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_BT_TX_DAC_IATTN(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_BT_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_BT_TX_DAC_RCAL(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_BT_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_BT_TX_DAC_OS(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_BT_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_BT_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_BT_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_SX_EN_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,0,0xfffffffe) #define SET_RG_SX_EN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,1,0xfffffffd) #define SET_RG_EN_SX_CP_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,2,0xfffffffb) #define SET_RG_EN_SX_CP(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,3,0xfffffff7) #define SET_RG_EN_SX_DIV_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,4,0xffffffef) #define SET_RG_EN_SX_DIV(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,5,0xffffffdf) #define SET_RG_EN_SX_VCO_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,6,0xffffffbf) #define SET_RG_EN_SX_VCO(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,7,0xffffff7f) #define SET_RG_SX_PFD_RST_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,8,0xfffffeff) #define SET_RG_SX_PFD_RST(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,9,0xfffffdff) #define SET_RG_SX_UOP_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,10,0xfffffbff) #define SET_RG_SX_UOP_EN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,11,0xfffff7ff) #define SET_RG_EN_VCOBF_TXMB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,12,0xffffefff) #define SET_RG_EN_VCOBF_TXMB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,13,0xffffdfff) #define SET_RG_EN_VCOBF_TXOB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,14,0xffffbfff) #define SET_RG_EN_VCOBF_TXOB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,15,0xffff7fff) #define SET_RG_EN_VCOBF_RXMB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,16,0xfffeffff) #define SET_RG_EN_VCOBF_RXMB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,17,0xfffdffff) #define SET_RG_EN_VCOBF_RXOB_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,18,0xfffbffff) #define SET_RG_EN_VCOBF_RXOB(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,19,0xfff7ffff) #define SET_RG_EN_VCOBF_DIVCK_MAN(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,20,0xffefffff) #define SET_RG_EN_VCOBF_DIVCK(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,21,0xffdfffff) #define SET_RG_SX_SBCAL_DIS(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,23,0xff7fffff) #define SET_RG_SX_SBCAL_AW(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,24,0xfeffffff) #define SET_RG_SX_AAC_DIS(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,26,0xfbffffff) #define SET_RG_SX_TTL_DIS(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,27,0xf7ffffff) #define SET_RG_SX_CAL_INIT(_VAL_) SET_REG(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER,_VAL_,29,0x1fffffff) #define SET_RG_EN_SX_LDO_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_EN_LDO_CP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_EN_LDO_DIV(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_EN_LDO_LO(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_EN_LDO_VCO(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_EN_LDO_VCO_PSW(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_EN_LDO_VCO_VDD33(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_EN_LDO_CP_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_EN_LDO_DIV_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_EN_LDO_LO_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_EN_LDO_VCO_IQUP(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_SX_LDO_FCOFFT(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_LDO_CP_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_LDO_CP_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_LDO_DIV_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_LDO_DIV_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_LDO_LO_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_LDO_LO_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_LDO_VCO_FC_MAN(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_LDO_VCO_FC(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_LDO_VCO_RCF(_VAL_) SET_REG(ADR_SX_2_4G_LDO_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_SX_RFCTRL_F(_VAL_) SET_REG(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000) #define SET_RG_SX_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff) #define SET_RG_SX_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8) #define SET_RG_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,3,0xfffffff7) #define SET_RG_SX_FREF_DOUB_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,6,0xffffffbf) #define SET_RG_SX_FREF_DOUB(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,7,0xffffff7f) #define SET_RG_SX_BTRX_SIDE(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xfffffeff) #define SET_RG_SX_LO_TIMES(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,9,0xfffffdff) #define SET_RG_SX_CHANNEL(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,11,0xfff807ff) #define SET_RG_SX_XTAL_FREQ(_VAL_) SET_REG(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,20,0xff0fffff) #define SET_RG_SX_CP_ISEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,0,0xfffffff0) #define SET_RG_SX_CP_ISEL50U_BT(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,4,0xffffffef) #define SET_RG_SX_CP_KP_DOUB_BT(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,5,0xffffffdf) #define SET_RG_SX_CP_ISEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,7,0xfffff87f) #define SET_RG_SX_CP_ISEL50U_WF(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,11,0xfffff7ff) #define SET_RG_SX_CP_KP_DOUB_WF(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,12,0xffffefff) #define SET_RG_SX_CP_IOST_POL(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,15,0xffff7fff) #define SET_RG_SX_CP_IOST(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,16,0xfff8ffff) #define SET_RG_SX_PFD_SEL(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,22,0xffbfffff) #define SET_RG_SX_PFD_SET(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,23,0xff7fffff) #define SET_RG_SX_PFD_SET1(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,24,0xfeffffff) #define SET_RG_SX_PFD_SET2(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,25,0xfdffffff) #define SET_RG_SX_PFD_REF_EDGE(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,26,0xfbffffff) #define SET_RG_SX_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,27,0xf7ffffff) #define SET_RG_SX_PFD_TRUP(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,28,0xefffffff) #define SET_RG_SX_PFD_TRDN(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,29,0xdfffffff) #define SET_RG_SX_PFD_TLSEL(_VAL_) SET_REG(ADR_SX_2_4GB_PFD_CHP_,_VAL_,30,0xbfffffff) #define SET_RG_SX_LPF_C1_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,0,0xfffffff0) #define SET_RG_SX_LPF_C2_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,4,0xffffff0f) #define SET_RG_SX_LPF_C3_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,8,0xfffffeff) #define SET_RG_SX_LPF_R2_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,9,0xffffe1ff) #define SET_RG_SX_LPF_R3_BT(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,13,0xffff1fff) #define SET_RG_SX_LPF_C1_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,16,0xfff0ffff) #define SET_RG_SX_LPF_C2_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,20,0xff0fffff) #define SET_RG_SX_LPF_C3_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,24,0xfeffffff) #define SET_RG_SX_LPF_R2_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,25,0xe1ffffff) #define SET_RG_SX_LPF_R3_WF(_VAL_) SET_REG(ADR_SX_2_4GB_LPF,_VAL_,29,0x1fffffff) #define SET_RG_SX_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,0,0xfffffffe) #define SET_RG_SX_VCO_ISEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,1,0xffffffe1) #define SET_RG_SX_VCO_LPM_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,5,0xffffffdf) #define SET_RG_SX_VCO_VCCBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,6,0xfffffe3f) #define SET_RG_SX_VCO_KVDOUB_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,9,0xfffffdff) #define SET_RG_SX_VCO_ISEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,10,0xffffc3ff) #define SET_RG_SX_VCO_LPM_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,14,0xffffbfff) #define SET_RG_SX_VCO_VCCBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,15,0xfffc7fff) #define SET_RG_SX_VCO_KVDOUB_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,18,0xfffbffff) #define SET_RG_SX_VCO_VARBSEL(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,21,0xff9fffff) #define SET_RG_SX_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,23,0xff7fffff) #define SET_RG_SX_VCO_CS_AWH(_VAL_) SET_REG(ADR_SX_2_4GB_VCO,_VAL_,24,0xfeffffff) #define SET_RG_VOBF_TXMBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,0,0xfffffffc) #define SET_RG_VOBF_TXOBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,2,0xfffffff3) #define SET_RG_VOBF_RXMBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,4,0xffffffcf) #define SET_RG_VOBF_RXOBSEL_BT(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,6,0xffffff3f) #define SET_RG_VOBF_TXMBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,10,0xfffff3ff) #define SET_RG_VOBF_TXOBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,12,0xffffcfff) #define SET_RG_VOBF_RXMBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,14,0xffff3fff) #define SET_RG_VOBF_RXOBSEL_WF(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,16,0xfffcffff) #define SET_RG_VOBF_DIVBFSEL(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,19,0xfff7ffff) #define SET_RG_SX_VCO_TXOB_AW(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,20,0xffefffff) #define SET_RG_SX_VCO_RXOB_AW(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,21,0xffdfffff) #define SET_RG_VOBF_CAPIMB_POL(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,26,0xfbffffff) #define SET_RG_VOBF_CAPIMB(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,27,0xc7ffffff) #define SET_RG_EN_SX_VCOMON(_VAL_) SET_REG(ADR_SX_2_4GB_VCOBF,_VAL_,31,0x7fffffff) #define SET_RG_SX_DIV_PREVDD(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,0,0xfffffff0) #define SET_RG_SX_DIV_PSCVDD(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,4,0xffffff0f) #define SET_RG_SX_DIV_RST_H(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,9,0xfffffdff) #define SET_RG_SX_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,10,0xfffffbff) #define SET_RG_SX_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,11,0xfffff7ff) #define SET_RG_EN_SX_MOD(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,17,0xfffdffff) #define SET_RG_EN_SX_DITHER(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,18,0xfffbffff) #define SET_RG_SX_MOD_ORDER(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,19,0xffe7ffff) #define SET_RG_SX_DITHER_WEIGHT(_VAL_) SET_REG(ADR_SX_2_4GB_DIV_SDM,_VAL_,21,0xff9fffff) #define SET_RG_SX_SUB_SEL_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,0,0xfffffffe) #define SET_RG_SX_SUB_SEL(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,1,0xfffffe01) #define SET_RG_SX_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,9,0xfffffdff) #define SET_RG_SX_SBCAL_CT(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,10,0xfffff3ff) #define SET_RG_SX_SBCAL_WT(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,12,0xffffefff) #define SET_RG_SX_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,13,0xffffdfff) #define SET_RG_SX_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,15,0xffff7fff) #define SET_RG_SX_SBCAL_NTARG(_VAL_) SET_REG(ADR_SX_2_4GB_SBCAL,_VAL_,16,0x0000ffff) #define SET_RG_VO_AAC_TAR_BT(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,0,0xfffffff0) #define SET_RG_VO_AAC_IOST_BT(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,4,0xffffffcf) #define SET_RG_VO_AAC_TAR_WF(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,7,0xfffff87f) #define SET_RG_VO_AAC_IOST_WF(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,11,0xffffe7ff) #define SET_RG_VO_AAC_IMAX(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,14,0xfffc3fff) #define SET_RG_VO_AAC_INIT(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,18,0xfff3ffff) #define SET_RG_VO_AAC_EVA_TS(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,20,0xffcfffff) #define SET_RG_VO_AAC_EN_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,23,0xff7fffff) #define SET_RG_VO_AAC_EN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,24,0xfeffffff) #define SET_RG_VO_AAC_EVA_MAN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,25,0xfdffffff) #define SET_RG_VO_AAC_EVA(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,26,0xfbffffff) #define SET_RG_VO_AAC_TEST_EN(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,28,0xefffffff) #define SET_RG_VO_AAC_TEST_SEL(_VAL_) SET_REG(ADR_SX_2_4GB_AAC,_VAL_,29,0xdfffffff) #define SET_RG_SX_TTL_INIT(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,0,0xfffffffc) #define SET_RG_SX_TTL_FPT(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,2,0xfffffff3) #define SET_RG_SX_TTL_CPT(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,4,0xffffffcf) #define SET_RG_SX_TTL_ACCUM(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,7,0xfffffe7f) #define SET_RG_SX_TTL_SUB(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,10,0xfffff3ff) #define SET_RG_SX_TTL_SUB_INV(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,12,0xffffefff) #define SET_RG_SX_TTL_VH(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,14,0xffff3fff) #define SET_RG_SX_TTL_VL(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,16,0xfffcffff) #define SET_RG_SX_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_SX_2_4GB_TTL,_VAL_,19,0xfff7ffff) #define SET_DPLL_TOP_REGISTER(_VAL_) SET_REG(ADR_DPLL_TOP_REGISTER,_VAL_,0,0x00000000) #define SET_DPLL_CKT_REGISTER(_VAL_) SET_REG(ADR_DPLL_CKT_REGISTER,_VAL_,0,0x00000000) #define SET_DPLL_FB_DIVISION__REGISTERS(_VAL_) SET_REG(ADR_DPLL_FB_DIVISION__REGISTERS,_VAL_,0,0x00000000) #define SET_RG_WF_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_WF_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_WF_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_WF_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_WF_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0) #define SET_RG_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff) #define SET_RG_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff) #define SET_RG_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff) #define SET_RG_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0) #define SET_RG_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff) #define SET_RG_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff) #define SET_RG_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff) #define SET_RG_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0) #define SET_RG_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff) #define SET_RG_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff) #define SET_RG_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff) #define SET_RG_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0) #define SET_RG_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff) #define SET_RG_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff) #define SET_RG_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff) #define SET_RG_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0) #define SET_RG_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff) #define SET_RG_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff) #define SET_RG_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_WF_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_BT_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_BT_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_BT_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_BT_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_BT_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_SX_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_TXDAC_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f) #define SET_RG_TXRF_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff) #define SET_RG_TXPA_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff) #define SET_RG_RXRF_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff) #define SET_RG_TXBTPA_DELAY(_VAL_) SET_REG(ADR_MODE_DECODER_TIMER_REGISTER1,_VAL_,20,0xff0fffff) #define SET_RG_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_WIFI_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_WIFI_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_WF_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_BT_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_RX_RCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_RX_N_RCCAL_DELAY(_VAL_) SET_REG(ADR_CALIBRATION_TIMER_REGISTER,_VAL_,24,0xf8ffffff) #define SET_RG_PGAG_RCCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,0,0xfffffff0) #define SET_RG_PGAG_TXCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,4,0xffffff0f) #define SET_RG_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,8,0xffff80ff) #define SET_RG_RFG_RXIQCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,16,0xfffcffff) #define SET_RG_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,18,0xffc3ffff) #define SET_RG_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER0,_VAL_,22,0xe03fffff) #define SET_RG_RFG_DPDCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffffc) #define SET_RG_PGAG_DPDCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,2,0xffffffc3) #define SET_RG_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xffffe03f) #define SET_RG_IOT_ADC_CLKSEL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,16,0xfffeffff) #define SET_RG_IOT_ADC_DNLEN(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfffdffff) #define SET_RG_IOT_ADC_METAEN(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,18,0xfffbffff) #define SET_RG_IOT_ADC_TFLAG(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xfff7ffff) #define SET_RG_IOT_ADC_ICMP(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,20,0xffcfffff) #define SET_RG_IOT_ADC_VCMI(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,22,0xff3fffff) #define SET_RG_IOT_ADC_CLOAD(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,24,0xfcffffff) #define SET_RG_IOT_ADC_CLK_DIV(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,26,0xf3ffffff) #define SET_RG_IOT_ADC_CLK_SH_DUTY(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,28,0xefffffff) #define SET_RG_IOT_ADC_VSEN_SEL(_VAL_) SET_REG(ADR_CALIBRATION_GAIN_REGISTER1,_VAL_,29,0x9fffffff) #define SET_DB_AD_ADC_I_OUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,0,0xfffffc00) #define SET_DB_AD_ADC_Q_OUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,10,0xfff003ff) #define SET_DB_AD_RX_RSSIADC(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,20,0xff0fffff) #define SET_DB_DA_SARADC_BIT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,24,0xc0ffffff) #define SET_SAR_ADC_FSM_RDY(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_ADC,_VAL_,30,0xbfffffff) #define SET_DB_DA_SX_SUB_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,0,0xffffff00) #define SET_DB_DA_SX_VCO_ISEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,8,0xfffff0ff) #define SET_DB_VO_AAC_COMPOUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,12,0xffffefff) #define SET_DB_SX_TTL_VT_DET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,14,0xffff3fff) #define SET_DB_AD_DP_VT_MON_Q(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,16,0xfffcffff) #define SET_DB_AD_IOT_ADC_OUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_1,_VAL_,20,0xc00fffff) #define SET_DB_SX_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,0,0xffff0000) #define SET_DB_SX_SBCAL_NTARGET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_2_4GB_2,_VAL_,16,0x0000ffff) #define SET_RG_5G_TX_TRSW_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_5G_EN_TX_TRSW(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_5G_RX_LNA_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_5G_EN_RX_LNA(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_5G_RX_MIXER_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_5G_EN_RX_MIXER(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,5,0xffffffdf) #define SET_RG_5G_RX_DIV2_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_5G_EN_RX_DIV2(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_5G_RX_LOBUF_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,8,0xfffffeff) #define SET_RG_5G_EN_RX_LOBUF(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_5G_RX_TZ_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_5G_EN_RX_TZ(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_5G_TX_PA_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_5G_EN_TX_PA(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_5G_TX_MOD_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_5G_EN_TX_MOD(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,15,0xffff7fff) #define SET_RG_5G_TX_DIV2_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,18,0xfffbffff) #define SET_RG_5G_EN_TX_DIV2(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_5G_TX_DIV2_BUF_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,20,0xffefffff) #define SET_RG_5G_EN_TX_DIV2_BUF(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,21,0xffdfffff) #define SET_RG_5G_RX_TZ_OUT_TRISTATE_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_5G_RX_TZ_OUT_TRISTATE(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_5G_TX_SELF_MIXER_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_5G_EN_TX_SELF_MIXER(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_5G_RX_IQCAL_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_5G_EN_RX_IQCAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_5G_TX_DPD_MANUAL(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_5G_EN_TX_DPD(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_5G_EN_TX_TSSI(_VAL_) SET_REG(ADR_5G_TRX_MANUAL_ENABLE_REGISTER,_VAL_,30,0xbfffffff) #define SET_RG_5G_LDO_LEVEL_RX_FE(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_5G_EN_LDO_RX_FE_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_SX5GB_LDO_CP_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,4,0xffffff8f) #define SET_RG_EN_LDO_5G_CP_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_SX5GB_LDO_LO_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_EN_LDO_5G_LO_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_SX5GB_LDO_VCO_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_SX5GB_LDO_DIV_LEVEL(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_EN_LDO_5G_DIV_BYP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_5G_EN_LDO_RX_FE(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_5G_EN_IREF_RX(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_5G_EN_LDO_RX_FE_FC(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_5G_EN_LDO_RX_FE_IQUP(_VAL_) SET_REG(ADR_5G_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_5G_RX_SCA_MANUAL(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,0,0xfffffffe) #define SET_RG_5G_RX_SCA_MA(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,1,0xfffffff1) #define SET_RG_5G_RX_SCA_LOAD(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,4,0xffffff8f) #define SET_RG_5G_RX_LNA_TRI_SEL(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,8,0xfffffcff) #define SET_RG_5G_RX_LNA_SETTLE(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,10,0xfffff3ff) #define SET_RG_5G_GM_BIAS(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,12,0xffff8fff) #define SET_RG_5G_RX_DIV2_BUF(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,16,0xfffcffff) #define SET_RG_5G_RX_DIV2_CML(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,18,0xfff3ffff) #define SET_RG_5G_RX_DIV_CMLISEL(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,20,0xffcfffff) #define SET_RG_5G_RX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,22,0xffbfffff) #define SET_RG_5G_RX_TZ_COURSE(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,24,0xfcffffff) #define SET_RG_5G_TX_DPDGM_BIAS(_VAL_) SET_REG(ADR_5G_RX_REGISTER1,_VAL_,28,0x0fffffff) #define SET_RG_5G_TX_DPD_DIV(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,0,0xfffffff0) #define SET_RG_5G_TX_TSSI_BIAS(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,4,0xffffff8f) #define SET_RG_5G_TX_TSSI_DIV(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,8,0xfffff8ff) #define SET_RG_5G_TX_TSSI_TEST(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,12,0xffffcfff) #define SET_RG_5G_TX_TSSI_TESTMODE(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,14,0xffffbfff) #define SET_RG_5G_RX_ADC_ICMP(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,16,0xfffcffff) #define SET_RG_5G_RX_ADC_VCMI(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,18,0xfff3ffff) #define SET_RG_5G_RX_ADC_CLOAD(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,20,0xffcfffff) #define SET_RG_5G_RX_ADC_PSW(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,22,0xffbfffff) #define SET_RG_5G_RX_TZ_CMZ_C(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,23,0xfe7fffff) #define SET_RG_5G_RX_TZ_CMZ_R(_VAL_) SET_REG(ADR_5G_RX_REGISTER2,_VAL_,25,0xf9ffffff) #define SET_RG_5G_TXPAPGA_MANUAL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_5G_TXPGA_CAPSW(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,1,0xfffffff1) #define SET_RG_5G_PACELL_EN(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,5,0xffffff1f) #define SET_RG_5G_PABIAS_CTRL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_5G_TX_PAFB_EN(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_5G_TX_PA1_VCAS(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,13,0xffff1fff) #define SET_RG_5G_TX_PA2_VCAS(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_PABIAS_2X(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,19,0xfff7ffff) #define SET_RG_5G_TX_PA3_VCAS(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,20,0xff8fffff) #define SET_RG_5G_TX_DIV_PREBUFS2(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_5G_TX_DIV_CMLISEL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_5G_TX_DIV_CMLVSEL(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,26,0xf3ffffff) #define SET_RG_5G_TX_DIV_VSET(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_5G_TX_LOBUF_VSET(_VAL_) SET_REG(ADR_5G_TX_FE_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_5G_TXPGA_MAIN(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,0,0xffffffc0) #define SET_RG_5G_TXPGA_STEER(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,6,0xfffff03f) #define SET_RG_5G_TXMOD_GMCELL(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_5G_TXLPF_GMCELL(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,14,0xffff3fff) #define SET_RG_5G_TX_GAIN_OFFSET(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,16,0xfff0ffff) #define SET_RG_5G_TX_GAIN(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,20,0xf80fffff) #define SET_RG_5G_TX_ADDGMCELL(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_5G_TXMOD_LOBIAS(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,28,0xcfffffff) #define SET_RG_5G_TXMOD_PGABIAS(_VAL_) SET_REG(ADR_5G_TX_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_5G_RX_HG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_5G_RX_HG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_5G_RX_HG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_5G_RX_HG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_5G_RX_HG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_5G_RX_HG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_RX_HG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_5G_RX_HG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_5G_RX_HG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_5G_RX_HG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_5G_RX_HG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_HG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_5G_RX_MG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_5G_RX_MG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_5G_RX_MG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_5G_RX_MG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_5G_RX_MG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_5G_RX_MG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_RX_MG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_5G_RX_MG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_5G_RX_MG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_5G_RX_MG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_5G_RX_MG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_MG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_5G_RX_LG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_5G_RX_LG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_5G_RX_LG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_5G_RX_LG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_5G_RX_LG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_5G_RX_LG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_RX_LG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_5G_RX_LG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_5G_RX_LG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_5G_RX_LG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_5G_RX_LG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_LG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_5G_RX_ULG_LNA_GC(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_5G_RX_ULG_TZ_GC(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_5G_RX_ULG_LNAHGN_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,4,0xffffff0f) #define SET_RG_5G_RX_ULG_LNAHGP_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,8,0xfffff0ff) #define SET_RG_5G_RX_ULG_LNALG_BIAS(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,12,0xffff0fff) #define SET_RG_5G_RX_ULG_TZ_CAP(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_RX_ULG_SQDC(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_5G_RX_ULG_DIV2_CORE(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,22,0xff3fffff) #define SET_RG_5G_RX_ULG_TZ_GC_BOOST(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,24,0xfcffffff) #define SET_RG_5G_RX_ULG_TZI(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,26,0xe3ffffff) #define SET_RG_5G_RX_ULG_TZ_VCM(_VAL_) SET_REG(ADR_5G_RX_FE_ULG_REGISTER,_VAL_,29,0x1fffffff) #define SET_RG_5G_TX_DACI1ST(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,0,0xfffffffc) #define SET_RG_5G_TX_DACLPF_ICOARSE(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,2,0xfffffff3) #define SET_RG_5G_TX_DACLPF_IFINE(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,4,0xffffffcf) #define SET_RG_5G_TX_DACLPF_VCM(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,6,0xffffff3f) #define SET_RG_5G_TX_DAC_IBIAS(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,8,0xfffffcff) #define SET_RG_5G_TX_DAC_IATTN(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_5G_TXLPF_BOOSTI(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_5G_TX_DAC_RCAL(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,12,0xffffcfff) #define SET_RG_5G_TX_DAC_CKEDGE_SEL(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_5G_TX_DAC_OS(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_TX_DAC_IOFFSET(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_5G_TX_DAC_QOFFSET(_VAL_) SET_REG(ADR_5G_TX_DAC_REGISTER,_VAL_,24,0xf0ffffff) #define SET_RG_SX5GB_RFCTRL_F(_VAL_) SET_REG(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,0,0xff000000) #define SET_RG_SX5GB_RFCTRL_CH_7_0(_VAL_) SET_REG(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS,_VAL_,24,0x00ffffff) #define SET_RG_SX5GB_RFCTRL_CH_10_8(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,0,0xfffffff8) #define SET_RG_SX5GB_RFCH_MAP_EN(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,4,0xffffffef) #define SET_RG_SX5GB_LO_TIMES(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,5,0xffffffdf) #define SET_RG_SX5GB_CHANNEL(_VAL_) SET_REG(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE,_VAL_,8,0xffff00ff) #define SET_RG_SX_5GB_EN_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,0,0xfffffffe) #define SET_RG_SX_5GB_EN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,1,0xfffffffd) #define SET_RG_EN_SX5GB_CP_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,2,0xfffffffb) #define SET_RG_EN_SX5GB_CP(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,3,0xfffffff7) #define SET_RG_EN_SX5GB_DIV_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,4,0xffffffef) #define SET_RG_EN_SX5GB_DIV(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,5,0xffffffdf) #define SET_RG_EN_SX5GB_VCO_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,6,0xffffffbf) #define SET_RG_EN_SX5GB_VCO(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,7,0xffffff7f) #define SET_RG_SX5GB_PFD_RST_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,8,0xfffffeff) #define SET_RG_SX5GB_PFD_RST(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,9,0xfffffdff) #define SET_RG_SX5GB_UOP_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,10,0xfffffbff) #define SET_RG_SX5GB_UOP_EN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,11,0xfffff7ff) #define SET_RG_EN_SX5GB_HSDIV_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,12,0xffffefff) #define SET_RG_EN_SX5GB_HSDIV(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,13,0xffffdfff) #define SET_RG_EN_HSDIV_OBF_SX_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,14,0xffffbfff) #define SET_RG_EN_HSDIV_OBF_SX(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,15,0xffff7fff) #define SET_RG_EN_HSDIV_OBF_MX_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,16,0xfffeffff) #define SET_RG_EN_HSDIV_OBF_MX(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,17,0xfffdffff) #define SET_RG_EN_SX_MIX_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,18,0xfffbffff) #define SET_RG_EN_SX_MIX(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,19,0xfff7ffff) #define SET_RG_EN_SX_REP_MAN(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,20,0xffefffff) #define SET_RG_EN_SX_REP(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,21,0xffdfffff) #define SET_RG_SX5GB_SBCAL_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,22,0xffbfffff) #define SET_RG_SX5GB_SBCAL_2ND_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,23,0xff7fffff) #define SET_RG_SX5GB_SBCAL_AW(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,24,0xfeffffff) #define SET_RG_SX5GB_VOAAC_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,25,0xfdffffff) #define SET_RG_SX5GB_MIXAAC_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,26,0xfbffffff) #define SET_RG_SX5GB_REPAAC_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,27,0xf7ffffff) #define SET_RG_SX5GB_TTL_DIS(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,28,0xefffffff) #define SET_RG_SX5GB_CAL_INIT(_VAL_) SET_REG(ADR_SX_5GB_ENABLE_TOP_CONTROLLER,_VAL_,29,0x1fffffff) #define SET_RG_EN_SX5GB_LDO_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,0,0xfffffffe) #define SET_RG_EN_LDO_5G_CP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,1,0xfffffffd) #define SET_RG_EN_LDO_5G_DIV(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,2,0xfffffffb) #define SET_RG_EN_LDO_5G_LO(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,3,0xfffffff7) #define SET_RG_EN_LDO_5G_VCO(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,4,0xffffffef) #define SET_RG_EN_SXMIX_INBF_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,6,0xffffffbf) #define SET_RG_EN_SXMIX_INBF(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,7,0xffffff7f) #define SET_RG_EN_LDO_5G_VCO_PSW(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,9,0xfffffdff) #define SET_RG_EN_LDO_5G_VCO_VDD33(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,10,0xfffffbff) #define SET_RG_EN_LDO_5G_CP_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,11,0xfffff7ff) #define SET_RG_EN_LDO_5G_DIV_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,12,0xffffefff) #define SET_RG_EN_LDO_5G_LO_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,13,0xffffdfff) #define SET_RG_EN_LDO_5G_VCO_IQUP(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,14,0xffffbfff) #define SET_RG_SX5GB_LDO_FCOFFT(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,19,0xffc7ffff) #define SET_RG_LDO_5G_CP_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,22,0xffbfffff) #define SET_RG_LDO_5G_CP_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,23,0xff7fffff) #define SET_RG_LDO_5G_DIV_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,24,0xfeffffff) #define SET_RG_LDO_5G_DIV_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,25,0xfdffffff) #define SET_RG_LDO_5G_LO_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,26,0xfbffffff) #define SET_RG_LDO_5G_LO_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,27,0xf7ffffff) #define SET_RG_LDO_5G_VCO_FC_MAN(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,28,0xefffffff) #define SET_RG_LDO_5G_VCO_FC(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,29,0xdfffffff) #define SET_RG_LDO_5G_VCO_RCF(_VAL_) SET_REG(ADR_SX_5GB_LDO_REGISTER,_VAL_,30,0x3fffffff) #define SET_RG_SX5GB_CP_ISEL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,0,0xfffffff0) #define SET_RG_SX5GB_CP_ISEL50U(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,4,0xffffffef) #define SET_RG_SX5GB_CP_KP_DOUB(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,5,0xffffffdf) #define SET_RG_SX5GB_CP_IOST_POL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,7,0xffffff7f) #define SET_RG_SX5GB_CP_IOST(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,8,0xfffff8ff) #define SET_RG_SX5GB_PFD_SEL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,12,0xffffefff) #define SET_RG_SX5GB_PFD_SET(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,13,0xffffdfff) #define SET_RG_SX5GB_PFD_SET1(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,14,0xffffbfff) #define SET_RG_SX5GB_PFD_SET2(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,15,0xffff7fff) #define SET_RG_SX5GB_PFD_TRUP(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,16,0xfffeffff) #define SET_RG_SX5GB_PFD_TRDN(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,17,0xfffdffff) #define SET_RG_SX5GB_PFD_TLSEL(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,18,0xfffbffff) #define SET_RG_SX5GB_PFD_REF_EDGE(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,19,0xfff7ffff) #define SET_RG_SX5GB_PFD_DIV_EDGE(_VAL_) SET_REG(ADR_SX_5GB_PFD_CHP_,_VAL_,20,0xffefffff) #define SET_RG_SX5GB_LPF_C1(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,0,0xfffffff0) #define SET_RG_SX5GB_LPF_C2(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,4,0xffffff0f) #define SET_RG_SX5GB_LPF_C3(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,8,0xfffffeff) #define SET_RG_SX5GB_LPF_R2(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,9,0xffffe1ff) #define SET_RG_SX5GB_LPF_R3(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,13,0xffff1fff) #define SET_RG_SX5GB_TTL_INIT(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,16,0xfffcffff) #define SET_RG_SX5GB_TTL_FPT(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,18,0xfff3ffff) #define SET_RG_SX5GB_TTL_CPT(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,20,0xffcfffff) #define SET_RG_SX5GB_TTL_ACCUM(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,22,0xff3fffff) #define SET_RG_SX5GB_TTL_SUB(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,24,0xfcffffff) #define SET_RG_SX5GB_TTL_SUB_INV(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,26,0xfbffffff) #define SET_RG_SX5GB_TTL_VH(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,27,0xe7ffffff) #define SET_RG_SX5GB_TTL_VL(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,29,0x9fffffff) #define SET_RG_SX5GB_LPF_VTUNE_TEST(_VAL_) SET_REG(ADR_SX_5GB_LPF_TTL,_VAL_,31,0x7fffffff) #define SET_RG_SX5GB_VCO_ISEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,0,0xfffffffe) #define SET_RG_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,1,0xffffffe1) #define SET_RG_SX5GB_VCO_VCCBSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,6,0xfffffe3f) #define SET_RG_SX5GB_VCO_KVDOUB(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,9,0xfffffdff) #define SET_RG_SX5GB_VCO_VARBSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,11,0xffffe7ff) #define SET_RG_SX5GB_VCO_RTAIL_SHIFT(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,13,0xffffdfff) #define SET_RG_SX5GB_VCO_CS_AWH(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,14,0xffffbfff) #define SET_RG_HSDIV_INBFSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,15,0xfffe7fff) #define SET_RG_HSDIV_OBFMX_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,17,0xfffdffff) #define SET_RG_HSDIV_OBFSX_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,18,0xfffbffff) #define SET_RG_HSDIV_VRSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,19,0xffe7ffff) #define SET_RG_SXMIX_IBIAS_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,21,0xff9fffff) #define SET_RG_SXMIX_SWB_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,23,0xfe7fffff) #define SET_RG_SXMIX_GMSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,25,0xf9ffffff) #define SET_RG_SXREP_SWB_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,27,0xe7ffffff) #define SET_RG_SXREP_CSSEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,29,0x9fffffff) #define SET_RG_EN_SX5GB_VCOMON(_VAL_) SET_REG(ADR_SX_5GB_VCO_LOGEN,_VAL_,31,0x7fffffff) #define SET_RG_SX5GB_DIV_PREVDD(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,0,0xfffffff0) #define SET_RG_SX5GB_DIV_PSCVDD(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,4,0xffffff0f) #define SET_RG_SX5GB_DIV_RST_H(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,9,0xfffffdff) #define SET_RG_SX5GB_DIV_SDM_EDGE(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,10,0xfffffbff) #define SET_RG_SX5GB_DIV_DMYBUF_EN(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,11,0xfffff7ff) #define SET_RG_EN_SX5GB_MOD(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,17,0xfffdffff) #define SET_RG_EN_SX5GB_DITHER(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,18,0xfffbffff) #define SET_RG_SX5GB_MOD_ORDER(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,19,0xffe7ffff) #define SET_RG_SX5GB_DITHER_WEIGHT(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,21,0xff9fffff) #define SET_RG_SXMIX_INBF_SEL(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,24,0xfcffffff) #define SET_RG_SXMIX_GMBIAS_OP1(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,26,0xfbffffff) #define SET_RG_SXMIX_SWBIAS_OP1(_VAL_) SET_REG(ADR_SX_5GB_DIV_SDM,_VAL_,27,0xf7ffffff) #define SET_RG_SX5GB_SUB_SEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,0,0xfffffffe) #define SET_RG_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,1,0xfffffe01) #define SET_RG_SX5GB_SUB_C0P5_DIS(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,9,0xfffffdff) #define SET_RG_SX5GB_SBCAL_CT(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,10,0xfffff3ff) #define SET_RG_SX5GB_SBCAL_WT(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,12,0xffffefff) #define SET_RG_SX5GB_SBCAL_DIFFMIN(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,13,0xffffdfff) #define SET_RG_SX5GB_SBCAL_NTARG_MAN(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,15,0xffff7fff) #define SET_RG_SX5GB_SBCAL_NTARG(_VAL_) SET_REG(ADR_SX_5GB_SBCAL,_VAL_,16,0x0000ffff) #define SET_RG_SX5GB_VOAAC_TAR(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0) #define SET_RG_VO5GB_AAC_IOST(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,4,0xffffffcf) #define SET_RG_VO5GB_AAC_IMAX(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,6,0xfffffc3f) #define SET_RG_SX5GB_AAC_ACCUMH(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,10,0xfffff3ff) #define SET_RG_SX5GB_AAC_ACCUML(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,12,0xffffcfff) #define SET_RG_SX5GB_AAC_INIT(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,14,0xffff3fff) #define SET_RG_SX5GB_AAC_EVA_TS(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,16,0xfffcffff) #define SET_RG_SX5GB_AAC_EN_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff) #define SET_RG_SX5GB_AAC_EN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,19,0xfff7ffff) #define SET_RG_SX5GB_AAC_EVA_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,20,0xffefffff) #define SET_RG_SX5GB_AAC_EVA(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,21,0xffdfffff) #define SET_RG_AAC5GB_TAR_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,22,0xffbfffff) #define SET_RG_AAC5GB_PDSW_EN_MAN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,24,0xfeffffff) #define SET_RG_EN_AAC5GB_VOPDSW(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,25,0xfdffffff) #define SET_RG_EN_AAC5GB_MXPDSW(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,26,0xfbffffff) #define SET_RG_EN_AAC5GB_RPPDSW(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,27,0xf7ffffff) #define SET_RG_SX5GB_AAC_TEST_EN(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,30,0xbfffffff) #define SET_RG_SX5GB_AAC_TEST_SEL(_VAL_) SET_REG(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION,_VAL_,31,0x7fffffff) #define SET_RG_SX5GB_MIXAAC_TAR(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,0,0xfffffff0) #define SET_RG_SXMIX_SCA_SEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,5,0xffffffdf) #define SET_RG_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,6,0xfffff03f) #define SET_RG_SX5GB_REPAAC_TAR(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,13,0xfffe1fff) #define SET_RG_SXREP_SCA_SEL_MAN(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,18,0xfffbffff) #define SET_RG_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_SX_5GB_LOGEN_CALIBRATION,_VAL_,19,0xfe07ffff) #define SET_RG_5G_IDACAI_TZ0_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER1,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER2,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER3,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER4,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER5,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER6,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER7,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER8,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG15(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG14(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER9,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG13(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG12(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER10,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG11(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG10(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER11,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG9(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG8(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER12,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG7(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG6(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER13,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG5(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER14,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER15,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_PGAG1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_PGAG0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER16,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER17,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ0_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ0_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER18,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ0_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ0_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_COARSE4(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER19,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_COARSE3(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_COARSE2(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER20,_VAL_,24,0xc0ffffff) #define SET_RG_5G_IDACAI_TZ1_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,0,0xffffffc0) #define SET_RG_5G_IDACAQ_TZ1_COARSE1(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,8,0xffffc0ff) #define SET_RG_5G_IDACAI_TZ1_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,16,0xffc0ffff) #define SET_RG_5G_IDACAQ_TZ1_COARSE0(_VAL_) SET_REG(ADR_5G_DCOC_IDAC_REGISTER21,_VAL_,24,0xc0ffffff) #define SET_RG_SX5GB_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_5G_TXDAC_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,4,0xffffff0f) #define SET_RG_5G_TXRF_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,8,0xfffff0ff) #define SET_RG_5G_TXPA_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,12,0xffff0fff) #define SET_RG_5G_RXRF_DELAY(_VAL_) SET_REG(ADR_5G_MODE_DECODER_TIMER_REGISTER1,_VAL_,16,0xfff0ffff) #define SET_RG_5G_TXDAC_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_5G_TXRF_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_5G_TXPA_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_5G_RXRF_T2R_DELAY(_VAL_) SET_REG(ADR_5G_T2R_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_5G_TXDAC_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,0,0xffffffe0) #define SET_RG_5G_TXRF_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,8,0xffffe0ff) #define SET_RG_5G_TXPA_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,16,0xffe0ffff) #define SET_RG_5G_RXRF_R2T_DELAY(_VAL_) SET_REG(ADR_5G_R2T_TIMER_REGISTER,_VAL_,24,0xe0ffffff) #define SET_RG_5G_RX_DCCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,0,0xfffffff8) #define SET_RG_5G_TX_DCCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,8,0xfffff8ff) #define SET_RG_5G_TX_IQCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,12,0xffff8fff) #define SET_RG_5G_RX_IQCAL_DELAY(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,16,0xfff8ffff) #define SET_RG_5G_PGAG_TXCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,20,0xff0fffff) #define SET_RG_5G_TX_GAIN_TXCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER,_VAL_,24,0x80ffffff) #define SET_RG_5G_PGAG_RCCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,0,0xfffffff0) #define SET_RG_5G_RFG_RXIQCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,4,0xffffffcf) #define SET_RG_5G_PGAG_RXIQCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,6,0xfffffc3f) #define SET_RG_5G_TX_GAIN_RXIQCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,10,0xfffe03ff) #define SET_RG_5G_RFG_DPDCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,17,0xfff9ffff) #define SET_RG_5G_PGAG_DPDCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,19,0xff87ffff) #define SET_RG_5G_TX_GAIN_DPDCAL(_VAL_) SET_REG(ADR_5G_CALIBRATION_GAIN_REGISTER1,_VAL_,23,0xc07fffff) #define SET_DB_DA_SX5GB_SUB_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,0,0xffffff00) #define SET_DB_DA_SX5GB_VCO_ISEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,8,0xfffff0ff) #define SET_DB_DA_SXMIX_SCA_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,13,0xfff81fff) #define SET_DB_DA_SXMIX_GMSEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,19,0xffe7ffff) #define SET_DB_DA_SXREP_SCA_SEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,21,0xf81fffff) #define SET_DB_DA_SXREP_CSSEL(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,27,0xe7ffffff) #define SET_DB_AD_SX5GB_AAC_COMPOUT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,29,0xdfffffff) #define SET_DB_SX5GB_TTL_VT_DET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_1,_VAL_,30,0x3fffffff) #define SET_DB_SXMIX_SCA_SEL_A1(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,0,0xffffffc0) #define SET_DB_SXMIX_SCA_SEL_A2(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,7,0xffffe07f) #define SET_DB_SXREP_SCA_SEL_B1(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,14,0xfff03fff) #define SET_DB_SXREP_SCA_SEL_B2(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_2,_VAL_,21,0xf81fffff) #define SET_DB_SX5GB_SBCAL_NCOUNT(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,0,0xffff0000) #define SET_DB_SX5GB_SBCAL_NTARGET(_VAL_) SET_REG(ADR_READ_ONLY_FLAGS_SX_5GB_3,_VAL_,16,0x0000ffff) #define SET_RG_RX_SCAMA_STEP0(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,0,0xfffffff0) #define SET_RG_RX_SCAMA_STEP1(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,4,0xffffff0f) #define SET_RG_RX_SCAMA_STEP2(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,8,0xfffff0ff) #define SET_RG_RX_SCAMA_STEP3(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,12,0xffff0fff) #define SET_RG_RX_SCAMA_STEP4(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,16,0xfff0ffff) #define SET_RG_RX_SCAMA_STEP5(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,20,0xff0fffff) #define SET_RG_RX_SCAMA_STEP6(_VAL_) SET_REG(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL,_VAL_,24,0xf0ffffff) #define SET_RG_RX_SCALOAD_STEP0(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,0,0xfffffff0) #define SET_RG_RX_SCALOAD_STEP1(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,4,0xffffff0f) #define SET_RG_RX_SCALOAD_STEP2(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,8,0xfffff0ff) #define SET_RG_RX_SCALOAD_STEP3(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,12,0xffff0fff) #define SET_RG_RX_SCALOAD_STEP4(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,16,0xfff0ffff) #define SET_RG_RX_SCALOAD_STEP5(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,20,0xff0fffff) #define SET_RG_RX_SCALOAD_STEP6(_VAL_) SET_REG(ADR_5G_RX_LNA_LOAD_SCA_CONTROL,_VAL_,24,0xf0ffffff) #define SET_RG_5G_TXPGA_CAPSW_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,0,0xfffffff8) #define SET_RG_5G_PABIAS_CTRL_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,3,0xffffff87) #define SET_RG_5G_TX_PA1_VCAS_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,7,0xfffffc7f) #define SET_RG_5G_TX_PA2_VCAS_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,10,0xffffe3ff) #define SET_RG_5G_TX_PA3_VCAS_F0(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,13,0xffff1fff) #define SET_RG_5G_TXPGA_CAPSW_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,16,0xfff8ffff) #define SET_RG_5G_PABIAS_CTRL_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,19,0xff87ffff) #define SET_RG_5G_TX_PA1_VCAS_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,23,0xfc7fffff) #define SET_RG_5G_TX_PA2_VCAS_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,26,0xe3ffffff) #define SET_RG_5G_TX_PA3_VCAS_F1(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_I,_VAL_,29,0x1fffffff) #define SET_RG_5G_TXPGA_CAPSW_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,0,0xfffffff8) #define SET_RG_5G_PABIAS_CTRL_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,3,0xffffff87) #define SET_RG_5G_TX_PA1_VCAS_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,7,0xfffffc7f) #define SET_RG_5G_TX_PA2_VCAS_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,10,0xffffe3ff) #define SET_RG_5G_TX_PA3_VCAS_F2(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,13,0xffff1fff) #define SET_RG_5G_TXPGA_CAPSW_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,16,0xfff8ffff) #define SET_RG_5G_PABIAS_CTRL_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,19,0xff87ffff) #define SET_RG_5G_TX_PA1_VCAS_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,23,0xfc7fffff) #define SET_RG_5G_TX_PA2_VCAS_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,26,0xe3ffffff) #define SET_RG_5G_TX_PA3_VCAS_F3(_VAL_) SET_REG(ADR_5G_TX_PGA_CAPSW_CONTROL_II,_VAL_,29,0x1fffffff) #define SET_RG_5G_TX_PAFB_EN_F0(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,0,0xfffffffe) #define SET_RG_5G_TX_PAFB_EN_F1(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,1,0xfffffffd) #define SET_RG_5G_TX_PAFB_EN_F2(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,2,0xfffffffb) #define SET_RG_5G_TX_PAFB_EN_F3(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,3,0xfffffff7) #define SET_RG_5G_TX_GAIN_F0(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,4,0xfffff80f) #define SET_RG_5G_TX_GAIN_F1(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,11,0xfffc07ff) #define SET_RG_5G_TX_GAIN_F2(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,18,0xfe03ffff) #define SET_RG_5G_TX_GAIN_F3(_VAL_) SET_REG(ADR_5G_TX_GAIN_PAFB_CONTROL,_VAL_,25,0x01ffffff) #define SET_RG_NFRAC_DELTA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_0,_VAL_,0,0xff000000) #define SET_RG_40M_MODE(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_0,_VAL_,24,0xfeffffff) #define SET_RG_LO_UP_CH(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_0,_VAL_,28,0xefffffff) #define SET_RG_BT_TRX_IF(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_1,_VAL_,16,0xf800ffff) #define SET_RG_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,0,0xffffffe0) #define SET_RG_RX_IQ_THETA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,8,0xffffe0ff) #define SET_RG_RX_IQ_MANUAL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,16,0xfffeffff) #define SET_RG_RXIQ_NOSHRK(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,17,0xfffdffff) #define SET_RG_RX_RSSIADC_TH(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,20,0xff0fffff) #define SET_RG_SUB_DC(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,24,0xfeffffff) #define SET_RG_RSSI_EDGE_SEL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,26,0xfbffffff) #define SET_RG_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,27,0xf7ffffff) #define SET_RG_Q_INV(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,28,0xefffffff) #define SET_RG_I_INV(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,29,0xdfffffff) #define SET_RG_IQ_SWAP(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,30,0xbfffffff) #define SET_RG_SIGN_SWAP(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_2,_VAL_,31,0x7fffffff) #define SET_RG_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,0,0xffffffe0) #define SET_RG_TX_IQ_THETA(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,8,0xffffe0ff) #define SET_RG_TX_IQ_MANUAL(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,16,0xfffeffff) #define SET_RG_TXIQ_NOSHRK(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,17,0xfffdffff) #define SET_RG_TX_IQCAL_TIME(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_3,_VAL_,20,0xffcfffff) #define SET_RG_TX_FREQ_OFFSET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,0,0xffff0000) #define SET_RG_TONE_SCALE(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,16,0xfe00ffff) #define SET_RG_BB_SIG_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,25,0xfdffffff) #define SET_RG_TONE_GEN_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,26,0xfbffffff) #define SET_RG_TX_UP8X_MAN_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,27,0xf7ffffff) #define SET_RG_DIS_DAC_OFFSET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,28,0xefffffff) #define SET_RG_CLK_320M_INV(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,29,0xdfffffff) #define SET_RG_DPLL_CLK320BY2(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,30,0xbfffffff) #define SET_RG_CBW_20_40(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_4,_VAL_,31,0x7fffffff) #define SET_RG_DAC_DC_Q(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_5,_VAL_,0,0xfffffc00) #define SET_RG_DAC_DC_I(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_5,_VAL_,16,0xfc00ffff) #define SET_RG_DAC_Q_SET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,0,0xfffffc00) #define SET_RG_DAC_MAN_Q_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,12,0xffffefff) #define SET_RG_DAC_I_SET(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,16,0xfc00ffff) #define SET_RG_DAC_MAN_I_EN(_VAL_) SET_REG(ADR_DIGITAL_ADD_ON_6,_VAL_,28,0xefffffff) #define SET_RG_WF_RX_ABBCTUNE_TUNE(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,0,0xffffff80) #define SET_RG_WF_RX_ABBCTUNE_TUNE_EN(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,8,0xfffffeff) #define SET_RG_WF_N_RX_ABBCTUNE_TUNE(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,16,0xff80ffff) #define SET_RG_WF_N_RX_ABBCTUNE_TUNE_EN(_VAL_) SET_REG(ADR_RX_RC_VALUE_TUNE,_VAL_,24,0xfeffffff) #define SET_RG_RX_IQ_2500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,0,0xffffffe0) #define SET_RG_RX_IQ_2500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,8,0xffffe0ff) #define SET_RG_TX_IQ_2500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,16,0xffe0ffff) #define SET_RG_TX_IQ_2500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_2G,_VAL_,24,0xe0ffffff) #define SET_RG_RX_IQ_5100_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,0,0xffffffe0) #define SET_RG_RX_IQ_5100_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,8,0xffffe0ff) #define SET_RG_TX_IQ_5100_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,16,0xffe0ffff) #define SET_RG_TX_IQ_5100_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_0,_VAL_,24,0xe0ffffff) #define SET_RG_RX_IQ_5500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,0,0xffffffe0) #define SET_RG_RX_IQ_5500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,8,0xffffe0ff) #define SET_RG_TX_IQ_5500_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,16,0xffe0ffff) #define SET_RG_TX_IQ_5500_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_1,_VAL_,24,0xe0ffffff) #define SET_RG_RX_IQ_5700_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,0,0xffffffe0) #define SET_RG_RX_IQ_5700_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,8,0xffffe0ff) #define SET_RG_TX_IQ_5700_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,16,0xffe0ffff) #define SET_RG_TX_IQ_5700_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_2,_VAL_,24,0xe0ffffff) #define SET_RG_RX_IQ_5900_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,0,0xffffffe0) #define SET_RG_RX_IQ_5900_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,8,0xffffe0ff) #define SET_RG_TX_IQ_5900_ALPHA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,16,0xffe0ffff) #define SET_RG_TX_IQ_5900_THETA(_VAL_) SET_REG(ADR_TRX_IQ_COMP_5G_3,_VAL_,24,0xe0ffffff) #define SET_RG_PHASE_STEP_VALUE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,0,0xffff0000) #define SET_RG_PHASE_MANUAL(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,16,0xfffeffff) #define SET_RG_ALPHA_SEL(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,20,0xffcfffff) #define SET_RG_SPECTRUM_BW(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,24,0xfcffffff) #define SET_RG_SPECTRUM_EN(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_0,_VAL_,28,0xefffffff) #define SET_RO_WF_DCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,16,0xfffeffff) #define SET_RO_BT_DCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,17,0xfffdffff) #define SET_RO_RCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,18,0xfffbffff) #define SET_RO_TXDC_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,19,0xfff7ffff) #define SET_RO_TXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,20,0xffefffff) #define SET_RO_RXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,21,0xffdfffff) #define SET_RO_5G_TXDC_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,22,0xffbfffff) #define SET_RO_5G_TXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,23,0xff7fffff) #define SET_RO_5G_RXIQ_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,24,0xfeffffff) #define SET_RO_5G_DCCAL_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,25,0xfdffffff) #define SET_RO_PRE_DC_DONE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_1,_VAL_,26,0xfbffffff) #define SET_RG_PHASE_17P5M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_2,_VAL_,0,0xffff0000) #define SET_RG_PHASE_2P5M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_2,_VAL_,16,0x0000ffff) #define SET_RG_PHASE_RXIQ_1M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_3,_VAL_,0,0xffff0000) #define SET_RG_PHASE_1M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_3,_VAL_,16,0x0000ffff) #define SET_RG_PHASE_35M(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_4,_VAL_,16,0x0000ffff) #define SET_RO_RX_IQ_THETA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,0,0xffffffe0) #define SET_RO_RX_IQ_ALPHA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,8,0xffffe0ff) #define SET_RO_TX_IQ_THETA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,16,0xffe0ffff) #define SET_RO_TX_IQ_ALPHA(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_5,_VAL_,24,0xe0ffffff) #define SET_RG_RX_RCCAL_TARG(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,0,0xfffffc00) #define SET_RG_RX_DC_POLAR_INV(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,12,0xffffefff) #define SET_RG_RCCAL_POLAR_INV(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,13,0xffffdfff) #define SET_RG_RX_DC_RESOLUTION(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,14,0xffffbfff) #define SET_RG_RX_RCCAL_40M_TARG(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_6,_VAL_,16,0xfc00ffff) #define SET_RO_SPECTRUM_IQ_PWR_39_32(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_7,_VAL_,0,0xffffff00) #define SET_RG_SPECTRUM_LO_FIX(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_7,_VAL_,16,0xfffeffff) #define SET_RG_SPECTRUM_PWR_UPDATE(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_7,_VAL_,20,0xffefffff) #define SET_RO_SPECTRUM_IQ_PWR_31_0(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_8,_VAL_,0,0x00000000) #define SET_RG_PROC_DELAY(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,0,0xfffffff8) #define SET_RG_PRE_DC_POLA_INV(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,4,0xffffffef) #define SET_RG_RX_PRE_DC_RESOLUTION(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,5,0xffffffdf) #define SET_RG_PRE_DC_AUTO(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,6,0xffffffbf) #define SET_RG_FILTER_AVERAGE_EN(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,7,0xffffff7f) #define SET_RG_PHASE_RND_EN(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,8,0xfffffeff) #define SET_RG_RCCAL_DATA_SEL(_VAL_) SET_REG(ADR_RF_D_CAL_TOP_9,_VAL_,9,0xfffffdff) #define SET_RG_HS3W_TX_RF_GAIN(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,0,0xffffff80) #define SET_RG_HS3W_PGAGC(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,8,0xfffff0ff) #define SET_RG_HS3W_RFGC(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,12,0xffffcfff) #define SET_RG_HS3W_RXAGC(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,14,0xffffbfff) #define SET_RG_HS3W_RF_PHY_MODE(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,16,0xfff8ffff) #define SET_RG_HS3W_MANUAL(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,20,0xffefffff) #define SET_RG_HS3W_COMM_DATA(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,24,0xf8ffffff) #define SET_RG_HS3W_START_SENT(_VAL_) SET_REG(ADR_HS3W_CTRL1,_VAL_,28,0xefffffff) #define SET_RG_HS3W_SX_RFCTRL_CH_INT_10_8(_VAL_) SET_REG(ADR_HS3W_CTRL2,_VAL_,0,0xfffffff8) #define SET_RG_HS3W_SX_RFCH_MAP_EN_INT(_VAL_) SET_REG(ADR_HS3W_CTRL2,_VAL_,4,0xffffffef) #define SET_RG_HS3W_SX_CHANNEL_INT(_VAL_) SET_REG(ADR_HS3W_CTRL2,_VAL_,11,0xfff807ff) #define SET_RG_HS3W_SX_RFCTRL_F_INT(_VAL_) SET_REG(ADR_HS3W_CTRL3,_VAL_,0,0xff000000) #define SET_RG_HS3W_SX_RFCTRL_CH_INT_7_0(_VAL_) SET_REG(ADR_HS3W_CTRL3,_VAL_,24,0x00ffffff) #define SET_RG_MODE_BY_HS_3WIRE(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,0,0xfffffffe) #define SET_RG_MODE_BY_PHY(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,4,0xffffffef) #define SET_RG_MODE_BY_HWPIN(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,8,0xfffffeff) #define SET_RO_RF_PHY_MODE(_VAL_) SET_REG(ADR_RF_D_MODE_CTRL,_VAL_,16,0xfff8ffff) #define SET_RO_HS3W_SX_CHANNEL(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,0,0xffffff00) #define SET_RO_HS3W_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,8,0xfffffeff) #define SET_RO_GAIN_TX(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,16,0xff80ffff) #define SET_RO_ABBPGA(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,24,0xf0ffffff) #define SET_RO_RFPGA(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,28,0xcfffffff) #define SET_RO_DA_RX_AGC(_VAL_) SET_REG(ADR_HS3W_READ_OUT_1,_VAL_,31,0x7fffffff) #define SET_RO_HS3W_SX_RFCTRL_CH(_VAL_) SET_REG(ADR_HS3W_READ_OUT_2_,_VAL_,0,0xfffff800) #define SET_RO_HS3W_SX_RFCTRL_F(_VAL_) SET_REG(ADR_HS3W_READ_OUT_3,_VAL_,0,0xff000000) #define SET_RO_REFREG_KHZ_OUT(_VAL_) SET_REG(ADR_SX_LOCK_FREQ_1,_VAL_,0,0xff800000) #define SET_RO_RF_CH_FREQ(_VAL_) SET_REG(ADR_SX_LOCK_FREQ_2,_VAL_,0,0xffffe000) #define SET_RO_DC_CAL_Q(_VAL_) SET_REG(ADR_RX_DC_CAL_RESULT,_VAL_,0,0xffffff80) #define SET_RO_DC_CAL_I(_VAL_) SET_REG(ADR_RX_DC_CAL_RESULT,_VAL_,16,0xff80ffff) #define SET_RG_AUDIO_VOLUME(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,0,0xfffffc00) #define SET_RG_AUDIO_ALPHA(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,12,0xffffcfff) #define SET_RG_AUDIO_FIL_EN(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,16,0xfffeffff) #define SET_RG_IOT_ADC_SIGN_SWAP(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,24,0xfeffffff) #define SET_RG_IOT_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,25,0xfdffffff) #define SET_RG_BYPASS_AUDIO_LWDF(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,28,0xefffffff) #define SET_RG_PDM_EDGE_SEL(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,29,0xdfffffff) #define SET_RG_AUDIO_TYPE(_VAL_) SET_REG(ADR_AUDIO_CTRL_REG,_VAL_,30,0xbfffffff) #define SET_RG_PDM_LOW_LEVEL(_VAL_) SET_REG(ADR_AUDIO_PDM_REG,_VAL_,0,0xffffc000) #define SET_RG_PDM_HIGH_LEVEL(_VAL_) SET_REG(ADR_AUDIO_PDM_REG,_VAL_,16,0xc000ffff) #define SET_RG_5G_TX_BAND_F1(_VAL_) SET_REG(ADR_RF_5G_TX_PARTITION_BAND1,_VAL_,0,0xffffe000) #define SET_RG_5G_TX_BAND_F0(_VAL_) SET_REG(ADR_RF_5G_TX_PARTITION_BAND1,_VAL_,16,0xe000ffff) #define SET_RG_5G_TX_BAND_F2(_VAL_) SET_REG(ADR_RF_5G_TX_PARTITION_BAND2,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG0,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG1,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG1,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG2,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG2,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG3,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG3,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG4,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG4,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG5,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG5,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG6,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG6,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG7,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG7,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG8,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG8,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG9,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REG9,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGA,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGA,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGB,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGB,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGC,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5100_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_GAIN_REGC,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5100_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG0,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG0,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG1,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG1,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG2,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG2,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG3,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG3,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG4,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG4,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG5,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG5,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG6,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG6,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG7,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG7,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG8,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG8,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG9,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REG9,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGA,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGA,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGB,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGB,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5100_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGC,_VAL_,0,0xffffe000) #define SET_RG_DPD_5100_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5100_PHASE_REGC,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG0,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG1,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG1,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG2,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG2,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG3,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG3,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG4,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG4,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG5,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG5,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG6,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG6,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG7,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG7,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG8,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG8,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG9,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REG9,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGA,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGA,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGB,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGB,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGC,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5500_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_GAIN_REGC,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5500_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG0,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG0,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG1,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG1,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG2,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG2,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG3,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG3,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG4,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG4,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG5,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG5,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG6,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG6,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG7,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG7,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG8,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG8,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG9,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REG9,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGA,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGA,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGB,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGB,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5500_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGC,_VAL_,0,0xffffe000) #define SET_RG_DPD_5500_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5500_PHASE_REGC,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG0,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG1,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG1,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG2,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG2,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG3,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG3,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG4,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG4,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG5,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG5,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG6,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG6,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG7,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG7,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG8,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG8,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG9,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REG9,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGA,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGA,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGB,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGB,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGC,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5700_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_GAIN_REGC,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5700_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG0,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG0,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG1,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG1,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG2,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG2,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG3,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG3,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG4,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG4,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG5,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG5,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG6,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG6,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG7,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG7,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG8,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG8,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG9,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REG9,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGA,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGA,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGB,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGB,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5700_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGC,_VAL_,0,0xffffe000) #define SET_RG_DPD_5700_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5700_PHASE_REGC,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG0,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG1,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG1,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG2,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG2,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG3,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG3,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG4,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG4,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG5,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG5,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG6,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG6,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG7,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG7,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG8,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG8,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG9,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REG9,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGA,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGA,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGB,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGB,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGC,_VAL_,0,0xfffffc00) #define SET_RG_DPD_5900_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_GAIN_REGC,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_5900_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG0,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG0,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG1,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG1,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG2,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG2,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG3,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG3,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG4,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG4,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG5,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG5,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG6,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG6,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG7,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG7,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG8,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG8,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG9,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REG9,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGA,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGA,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGB,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGB,_VAL_,16,0xe000ffff) #define SET_RG_DPD_5900_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGC,_VAL_,0,0xffffe000) #define SET_RG_DPD_5900_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_5900_PHASE_REGC,_VAL_,16,0xe000ffff) #define SET_RG_TONE_SEL(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_TONEGEN_REG,_VAL_,0,0xfffffffc) #define SET_RG_TONE_1_RATE(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_TONEGEN_REG,_VAL_,16,0x0000ffff) #define SET_RG_RX_PADPD_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,0,0xfffffffe) #define SET_RG_RX_PADPD_LEAKY_FACTOR(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,4,0xffffff8f) #define SET_RG_RX_PADPD_LATCH(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,8,0xfffffeff) #define SET_RG_RX_PADPD_DATA_SEL(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,12,0xffffefff) #define SET_RG_RX_PADPD_TONE_SEL(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,13,0xffffdfff) #define SET_RG_RX_PADPD_RATE(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_PADPD_REG,_VAL_,16,0x0000ffff) #define SET_RO_RX_PHI(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_RO,_VAL_,0,0xffffe000) #define SET_RO_RX_AMP(_VAL_) SET_REG(ADR_WIFI_PADPD_CAL_RX_RO,_VAL_,16,0xfe00ffff) #define SET_RG_CFR_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_CFR,_VAL_,0,0xfffffc00) #define SET_RG_CFR_PEAK(_VAL_) SET_REG(ADR_WIFI_PADPD_CFR,_VAL_,16,0xfc00ffff) #define SET_RG_CFR_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_CFR,_VAL_,31,0x7fffffff) #define SET_RG_RX_PADPD_DC_RM_LEAKY_FACTOR(_VAL_) SET_REG(ADR_WIFI_PADPD_DC_RM,_VAL_,0,0xfffffff8) #define SET_RG_RX_PADPD_DC_RM_BYP(_VAL_) SET_REG(ADR_WIFI_PADPD_DC_RM,_VAL_,4,0xffffffef) #define SET_RG_TXIQ_CLP_THD_I(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CLIP_REG,_VAL_,0,0xfffffc00) #define SET_RG_TXIQ_CLP_THD_Q(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CLIP_REG,_VAL_,16,0xfc00ffff) #define SET_RG_TX_SCALE(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,0,0xffffff00) #define SET_RG_TX_IQ_SWP(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,16,0xfffeffff) #define SET_RG_TX_BB_SCALE_MANUAL(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,20,0xffefffff) #define SET_RG_TX_IQ_SRC(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_CONTROL_REG,_VAL_,24,0xfcffffff) #define SET_RG_TX_I_DC(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG,_VAL_,0,0xfffffc00) #define SET_RG_TX_Q_DC(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG,_VAL_,16,0xfc00ffff) #define SET_RG_TX_I_OFFSET(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG,_VAL_,16,0xff00ffff) #define SET_RG_TX_Q_OFFSET(_VAL_) SET_REG(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG,_VAL_,24,0x00ffffff) #define SET_RG_DPD_AM_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_CONTROL_REG,_VAL_,0,0xfffffffe) #define SET_RG_DPD_PM_EN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_CONTROL_REG,_VAL_,1,0xfffffffd) #define SET_RG_DPD_PM_AMSEL(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_CONTROL_REG,_VAL_,2,0xfffffffb) #define SET_RG_DPD_020_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG0,_VAL_,0,0xfffffc00) #define SET_RG_DPD_040_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_060_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG1,_VAL_,0,0xfffffc00) #define SET_RG_DPD_080_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG1,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_0A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG2,_VAL_,0,0xfffffc00) #define SET_RG_DPD_0C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG2,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_0D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG3,_VAL_,0,0xfffffc00) #define SET_RG_DPD_0E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG3,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_0F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG4,_VAL_,0,0xfffffc00) #define SET_RG_DPD_100_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG4,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_110_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG5,_VAL_,0,0xfffffc00) #define SET_RG_DPD_120_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG5,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_130_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG6,_VAL_,0,0xfffffc00) #define SET_RG_DPD_140_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG6,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_150_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG7,_VAL_,0,0xfffffc00) #define SET_RG_DPD_160_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG7,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_170_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG8,_VAL_,0,0xfffffc00) #define SET_RG_DPD_180_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG8,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_190_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG9,_VAL_,0,0xfffffc00) #define SET_RG_DPD_1A0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REG9,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_1B0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGA,_VAL_,0,0xfffffc00) #define SET_RG_DPD_1C0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGA,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_1D0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGB,_VAL_,0,0xfffffc00) #define SET_RG_DPD_1E0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGB,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_1F0_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGC,_VAL_,0,0xfffffc00) #define SET_RG_DPD_200_GAIN(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_GAIN_REGC,_VAL_,16,0xfc00ffff) #define SET_RG_DPD_020_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG0,_VAL_,0,0xffffe000) #define SET_RG_DPD_040_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG0,_VAL_,16,0xe000ffff) #define SET_RG_DPD_060_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG1,_VAL_,0,0xffffe000) #define SET_RG_DPD_080_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG1,_VAL_,16,0xe000ffff) #define SET_RG_DPD_0A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG2,_VAL_,0,0xffffe000) #define SET_RG_DPD_0C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG2,_VAL_,16,0xe000ffff) #define SET_RG_DPD_0D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG3,_VAL_,0,0xffffe000) #define SET_RG_DPD_0E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG3,_VAL_,16,0xe000ffff) #define SET_RG_DPD_0F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG4,_VAL_,0,0xffffe000) #define SET_RG_DPD_100_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG4,_VAL_,16,0xe000ffff) #define SET_RG_DPD_110_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG5,_VAL_,0,0xffffe000) #define SET_RG_DPD_120_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG5,_VAL_,16,0xe000ffff) #define SET_RG_DPD_130_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG6,_VAL_,0,0xffffe000) #define SET_RG_DPD_140_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG6,_VAL_,16,0xe000ffff) #define SET_RG_DPD_150_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG7,_VAL_,0,0xffffe000) #define SET_RG_DPD_160_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG7,_VAL_,16,0xe000ffff) #define SET_RG_DPD_170_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG8,_VAL_,0,0xffffe000) #define SET_RG_DPD_180_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG8,_VAL_,16,0xe000ffff) #define SET_RG_DPD_190_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG9,_VAL_,0,0xffffe000) #define SET_RG_DPD_1A0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REG9,_VAL_,16,0xe000ffff) #define SET_RG_DPD_1B0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGA,_VAL_,0,0xffffe000) #define SET_RG_DPD_1C0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGA,_VAL_,16,0xe000ffff) #define SET_RG_DPD_1D0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGB,_VAL_,0,0xffffe000) #define SET_RG_DPD_1E0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGB,_VAL_,16,0xe000ffff) #define SET_RG_DPD_1F0_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGC,_VAL_,0,0xffffe000) #define SET_RG_DPD_200_PH(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_PHASE_REGC,_VAL_,16,0xe000ffff) #define SET_RG_DPD_BB_SCALE_5900(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,0,0xffffff00) #define SET_RG_DPD_BB_SCALE_5700(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,8,0xffff00ff) #define SET_RG_DPD_BB_SCALE_5500(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,16,0xff00ffff) #define SET_RG_DPD_BB_SCALE_5100(_VAL_) SET_REG(ADR_WIFI_PADPD_5G_BB_GAIN_REG,_VAL_,24,0x00ffffff) #define SET_RG_DPD_BB_SCALE_2500(_VAL_) SET_REG(ADR_WIFI_PADPD_2G_BB_GAIN_REG,_VAL_,0,0xffffff00) #define SET_RG_TX_SCALE_11B(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,0,0xffffff00) #define SET_RG_TX_SCALE_11B_P0D5(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,8,0xffff00ff) #define SET_RG_TX_SCALE_11G(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,16,0xff00ffff) #define SET_RG_TX_SCALE_11G_P0D5(_VAL_) SET_REG(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG,_VAL_,24,0x00ffffff) #define SET_RG_HS5W_M_MD_EN(_VAL_) SET_REG(ADR_HS5W_MD_EN,_VAL_,0,0xfffffffe) #define SET_RG_HS5W_M_MAN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,0,0xfffffffe) #define SET_RG_HS5W_M_CMD6_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,25,0xfdffffff) #define SET_RG_HS5W_M_CMD5_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,26,0xfbffffff) #define SET_RG_HS5W_M_CMD4_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,27,0xf7ffffff) #define SET_RG_HS5W_M_CMD3_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,28,0xefffffff) #define SET_RG_HS5W_M_CMD2_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,29,0xdfffffff) #define SET_RG_HS5W_M_CMD1_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,30,0xbfffffff) #define SET_RG_HS5W_M_CMD0_EN(_VAL_) SET_REG(ADR_HS5W_MAN,_VAL_,31,0x7fffffff) #define SET_RG_HS5W_M_RF_PHY_MODE(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD0,_VAL_,0,0xfffffff8) #define SET_RG_HS5W_M_CAL_INDEX(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD1,_VAL_,0,0xffffffe0) #define SET_RG_HS5W_M_PGAGC(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD2,_VAL_,0,0xfffffff0) #define SET_RG_HS5W_M_RFGC(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD2,_VAL_,4,0xffffffcf) #define SET_RG_HS5W_M_TXPWRLVL(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD3,_VAL_,0,0xffffffc0) #define SET_RG_HS5W_M_SX_RFCTRL_CH(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_CH,_VAL_,0,0xfffff800) #define SET_RG_HS5W_M_SX5GB_RFCTRL_CH(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_CH_5GB,_VAL_,0,0xfffff800) #define SET_RG_HS5W_M_SX_RFCTRL_F(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F,_VAL_,0,0xff000000) #define SET_RG_HS5W_M_SX_RFCH_MAP_EN(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F,_VAL_,31,0x7fffffff) #define SET_RG_HS5W_M_SX5GB_RFCTRL_F(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F_5GB,_VAL_,0,0xff000000) #define SET_RG_HS5W_M_SX5GB_RFCH_MAP_EN(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD4_F_5GB,_VAL_,31,0x7fffffff) #define SET_RG_HS5W_M_SX_CHANNEL(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD5,_VAL_,0,0xffffff00) #define SET_RG_HS5W_M_SX5GB_CHANNEL(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD5_5GB,_VAL_,0,0xffffff00) #define SET_RG_HS5W_M_PHY_BW(_VAL_) SET_REG(ADR_HS5W_MAN_SET_ADD6,_VAL_,0,0xfffffffc) #define SET_RG_RESERVED_DPD(_VAL_) SET_REG(ADR_WIFI_PADPD_RESERVED_REG,_VAL_,0,0x00000000) #define SET_RG_XO_LDO_LEVEL(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,0,0xfffffff8) #define SET_RG_EN_LDO_XO_IQUP(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,4,0xffffffef) #define SET_RG_EN_LDO_XO_BYP(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,5,0xffffffdf) #define SET_RG_EN_DLDO_BYP(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,6,0xffffffbf) #define SET_RG_EN_DLDO_HALF_IQ(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,7,0xffffff7f) #define SET_RG_XO_CBANKI(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,8,0xfffe00ff) #define SET_RG_XO_CBANKO(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,17,0xfc01ffff) #define SET_RG_EN_FDB(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,26,0xfbffffff) #define SET_RG_FDB_BYPASS(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,27,0xf7ffffff) #define SET_RG_FDB_DUTY_LTH(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,28,0xcfffffff) #define SET_RG_EN_XOTEST(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,30,0xbfffffff) #define SET_RG_HW_WAKE_XOSC(_VAL_) SET_REG(ADR_PMU_REG_1,_VAL_,31,0x7fffffff) #define SET_RG_EN_FDB_DCC_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,0,0xfffffffe) #define SET_RG_EN_FDB_DELAYC_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,1,0xfffffffd) #define SET_RG_EN_FDB_DELAYF_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,2,0xfffffffb) #define SET_RG_EN_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,3,0xfffffff7) #define SET_RG_FDB_PHASESWAP_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,4,0xffffffef) #define SET_RG_CLOCK_BF_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,5,0xffffffdf) #define SET_RG_FDB_CDELAY_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,8,0xfffff0ff) #define SET_RG_FDB_FDELAY_MUAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,12,0xffff0fff) #define SET_RG_XO_TIMMER(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,16,0xffc0ffff) #define SET_RG_DPL_SETTLING_TIMMER(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,22,0xff3fffff) #define SET_RG_FDB_RDELAYF(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,24,0xfcffffff) #define SET_RG_FDB_RDELAYS(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,26,0xf3ffffff) #define SET_RG_FDB_RECAL_TIMMER(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,28,0xcfffffff) #define SET_RG_EN_FDB_RECAL(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,30,0xbfffffff) #define SET_RG_LOAD_RFTABLE_RDY(_VAL_) SET_REG(ADR_PMU_REG_2,_VAL_,31,0x7fffffff) #define SET_RG_DCDC_MODE(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,0,0xfffffffe) #define SET_RG_DLDO_LEVEL(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,1,0xfffffff1) #define SET_RG_BUCK_LEVEL(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,4,0xffffff0f) #define SET_RG_DLDO_BOOST_IQ(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,8,0xfffffeff) #define SET_RG_BUCK_EN_PSM(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,9,0xfffffdff) #define SET_RG_BUCK_PSM_VTH(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,10,0xfffffbff) #define SET_RG_BUCK_VREF_SEL(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,11,0xfffff7ff) #define SET_RG_LDO_LEVEL_EFUSE(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,12,0xffff8fff) #define SET_RG_EN_LDO_EFUSE(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,16,0xfffeffff) #define SET_RG_DCDC_PULLLOW_CON(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,18,0xfffbffff) #define SET_RG_DCDC_RES2_CON(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,19,0xfff7ffff) #define SET_RG_DCDC_RES_CON(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,20,0xffefffff) #define SET_RG_RTC_RS1(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,21,0xffdfffff) #define SET_RG_RTC_RS2(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,22,0xffbfffff) #define SET_RG_DCDC_CLK(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,24,0xf0ffffff) #define SET_RG_BUCK_RCZERO(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,28,0xefffffff) #define SET_RG_BUCK_SLOP(_VAL_) SET_REG(ADR_PMU_REG_3,_VAL_,29,0x9fffffff) #define SET_RG_RTC_OFFSET(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,0,0xffffff00) #define SET_RG_RTC_CAL_TARGET_COUNT(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,8,0xfff000ff) #define SET_RG_RTC_OSC_RES_SW_MANUAL(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,20,0xc00fffff) #define SET_RG_RTC_CAL_MODE(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,30,0xbfffffff) #define SET_RG_SEL_DPLL_CLK(_VAL_) SET_REG(ADR_PMU_REG_4,_VAL_,31,0x7fffffff) #define SET_RG_RTC_OSC_RES_SW_MANUAL_EN(_VAL_) SET_REG(ADR_PMU_REG_5,_VAL_,0,0xfffffffe) #define SET_RG_EN_RTC_CAL(_VAL_) SET_REG(ADR_PMU_REG_5,_VAL_,1,0xfffffffd) #define SET_RO_FDB_CDELAY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,0,0xfffffff0) #define SET_RO_FDB_FDELAY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,4,0xffffff0f) #define SET_RO_FDB_PHASESWAP(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,8,0xfffffeff) #define SET_RO_XO_RDY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,9,0xfffffdff) #define SET_RO_RTC_OSC_CAL_RES_RDY(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,10,0xfffffbff) #define SET_RO_RTC_OSC_RES_SW(_VAL_) SET_REG(ADR_PMU_REG_6,_VAL_,11,0xffe007ff) #define SET_RG_PMU_ENTER_SLEEP_MODE(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_SLEEP_METHOD(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_1,_VAL_,1,0xfffffffd) #define SET_RG_INT_PMU_MASK(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_1,_VAL_,2,0xfffffffb) #define SET_RG_SLEEP_WAKE_CNT(_VAL_) SET_REG(ADR_PMU_SLEEP_REG_2,_VAL_,0,0x00000000) #define SET_RG_SEC_CNT_VALUE(_VAL_) SET_REG(ADR_PMU_RTC_REG_0,_VAL_,0,0xffff8000) #define SET_RG_RTC_EN(_VAL_) SET_REG(ADR_PMU_RTC_REG_0,_VAL_,15,0xffff7fff) #define SET_RO_RTC_TICK_CNT(_VAL_) SET_REG(ADR_PMU_RTC_REG_0,_VAL_,16,0x8000ffff) #define SET_RG_RTC_INT_SEC_MASK(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_RTC_INT_ALARM_MASK(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,1,0xfffffffd) #define SET_RO_PMU_WAKE_TRIG_EVENT(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,12,0xffff8fff) #define SET_RO_RTC_INT_SEC(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,16,0xfffeffff) #define SET_RO_RTC_INT_ALARM(_VAL_) SET_REG(ADR_PMU_RTC_REG_1,_VAL_,17,0xfffdffff) #define SET_RG_RTC_SEC_START_CNT(_VAL_) SET_REG(ADR_PMU_RTC_REG_2,_VAL_,0,0x00000000) #define SET_RG_RTC_SEC_ALARM_VALUE(_VAL_) SET_REG(ADR_PMU_RTC_REG_3,_VAL_,0,0x00000000) #define SET_RG_FPGA_CLK_REF_40M_EN(_VAL_) SET_REG(ADR_PMU_CTRL_REG,_VAL_,0,0xfffffffe) #define SET_RG_CLK_RTC_SW(_VAL_) SET_REG(ADR_PMU_CTRL_REG,_VAL_,1,0xfffffffd) #define SET_RG_PHY_RST_N(_VAL_) SET_REG(ADR_PMU_CTRL_REG,_VAL_,4,0xffffffef) #define SET_RO_PMU_STATE(_VAL_) SET_REG(ADR_PMU_STATE_REG,_VAL_,0,0xfffffff8) #define SET_RO_AD_VBAT_OK(_VAL_) SET_REG(ADR_PMU_STATE_REG,_VAL_,4,0xffffffef) #define SET_RG_DP_LDO_LEVEL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,0,0xfffffff8) #define SET_RG_EN_LDO_DP_BYP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,3,0xfffffff7) #define SET_RG_DP_AUTOMAP_EN(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,5,0xffffffdf) #define SET_RG_EN_ADC_320M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,7,0xffffff7f) #define SET_RG_EN_IOTADC_160M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,8,0xfffffeff) #define SET_RG_EN_MAC_80M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,9,0xfffffdff) #define SET_RG_EN_MAC_96M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,10,0xfffffbff) #define SET_RG_EN_MAC_120M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,11,0xfffff7ff) #define SET_RG_EN_PHY_80M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,12,0xffffefff) #define SET_RG_EN_PHY_160M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,13,0xffffdfff) #define SET_RG_EN_PHY_320M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,14,0xffffbfff) #define SET_RG_EN_MAC_160M(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,15,0xffff7fff) #define SET_RG_DP_XTAL_FREQ(_VAL_) SET_REG(ADR_PMU_DPLL_REG_0,_VAL_,16,0xfff0ffff) #define SET_RG_DP_BBPLL_PD(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,0,0xfffffffe) #define SET_RG_DP_BBPLL_BP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,1,0xfffffffd) #define SET_RG_EN_DP_MANUAL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,2,0xfffffffb) #define SET_RG_DP_FREF_DOUB(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,3,0xfffffff7) #define SET_RG_DP_DAC320_DIVBY2(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,4,0xffffffef) #define SET_RG_DP_ADC320_DIVBY2_BT(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,5,0xffffffdf) #define SET_RG_DP_ADC320_DIVBY2_WF(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,6,0xffffffbf) #define SET_RG_EN_DPL_MOD(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,8,0xfffffeff) #define SET_RG_DPL_MOD_ORDER(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,9,0xfffff9ff) #define SET_RG_DP_REFDIV(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,11,0xfffc07ff) #define SET_RG_DP_FODIV(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,18,0xfe03ffff) #define SET_RG_EN_LDO_DP_IQUP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,26,0xfbffffff) #define SET_RG_DP_OD_TEST(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,27,0xf7ffffff) #define SET_RG_DP_BBPLL_TESTSEL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_1,_VAL_,28,0x8fffffff) #define SET_RG_DP_BBPLL_ICP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,0,0xfffffffc) #define SET_RG_DP_BBPLL_IDUAL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,2,0xfffffff3) #define SET_RG_DP_CP_IOSTPOL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,4,0xffffffef) #define SET_RG_DP_CP_IOST(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,5,0xffffff9f) #define SET_RG_DP_PFD_PFDSEL(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,7,0xffffff7f) #define SET_RG_DP_BBPLL_PFD_DLY(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,8,0xfffffcff) #define SET_RG_DP_RP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,11,0xffffc7ff) #define SET_RG_DP_RHP(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,14,0xffff3fff) #define SET_RG_EN_DP_VT_MON(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,17,0xfffdffff) #define SET_RG_DP_VT_TH_HI(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,18,0xfff3ffff) #define SET_RG_DP_VT_TH_LO(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,20,0xffcfffff) #define SET_RG_DP_BBPLL_BS(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,23,0xe07fffff) #define SET_RG_DP_BBPLL_SDM_EDGE(_VAL_) SET_REG(ADR_PMU_DPLL_REG_2,_VAL_,31,0x7fffffff) #define SET_RG_DPL_RFCTRL_F(_VAL_) SET_REG(ADR_PMU_DPLL_REG_3,_VAL_,0,0xff000000) #define SET_RG_DPL_RFCTRL_CH(_VAL_) SET_REG(ADR_PMU_DPLL_REG_3,_VAL_,24,0x00ffffff) #define SET_RG_DCDC_MODE_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,0,0xfffffffe) #define SET_RG_DLDO_LEVEL_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,1,0xfffffff1) #define SET_RG_BUCK_LEVEL_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,4,0xffffff0f) #define SET_RG_XO_CBANKI_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,8,0xfffe00ff) #define SET_RG_XO_CBANKO_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,17,0xfc01ffff) #define SET_RG_EN_DLDO_HALF_IQ_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,26,0xfbffffff) #define SET_RG_EN_DLDO_BYP_AUTO(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,27,0xf7ffffff) #define SET_RG_HW_WAKE_XOSC_SLP(_VAL_) SET_REG(ADR_PMU_SLEEP_MODE_REG,_VAL_,31,0x7fffffff) #define SET_RG_RAM_00(_VAL_) SET_REG(ADR_PMU_RAM_00,_VAL_,0,0x00000000) #define SET_RG_RAM_01(_VAL_) SET_REG(ADR_PMU_RAM_01,_VAL_,0,0x00000000) #define SET_RG_RAM_02(_VAL_) SET_REG(ADR_PMU_RAM_02,_VAL_,0,0x00000000) #define SET_RG_RAM_03(_VAL_) SET_REG(ADR_PMU_RAM_03,_VAL_,0,0x00000000) #define SET_RG_RAM_04(_VAL_) SET_REG(ADR_PMU_RAM_04,_VAL_,0,0x00000000) #define SET_RG_RAM_05(_VAL_) SET_REG(ADR_PMU_RAM_05,_VAL_,0,0x00000000) #define SET_RG_RAM_06(_VAL_) SET_REG(ADR_PMU_RAM_06,_VAL_,0,0x00000000) #define SET_RG_RAM_07(_VAL_) SET_REG(ADR_PMU_RAM_07,_VAL_,0,0x00000000) #define SET_RG_RAM_08(_VAL_) SET_REG(ADR_PMU_RAM_08,_VAL_,0,0x00000000) #define SET_RG_RAM_09(_VAL_) SET_REG(ADR_PMU_RAM_09,_VAL_,0,0x00000000) #define SET_RG_RAM_10(_VAL_) SET_REG(ADR_PMU_RAM_10,_VAL_,0,0x00000000) #define SET_RG_RAM_11(_VAL_) SET_REG(ADR_PMU_RAM_11,_VAL_,0,0x00000000) #define SET_RG_RAM_12(_VAL_) SET_REG(ADR_PMU_RAM_12,_VAL_,0,0x00000000) #define SET_RG_RAM_13(_VAL_) SET_REG(ADR_PMU_RAM_13,_VAL_,0,0x00000000) #define SET_RG_RAM_14(_VAL_) SET_REG(ADR_PMU_RAM_14,_VAL_,0,0x00000000) #define SET_RG_RAM_15(_VAL_) SET_REG(ADR_PMU_RAM_15,_VAL_,0,0x00000000) #define SET_RG_PMDLBK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,0,0xfffffffe) #define SET_RG_DAC_LBK_EDGE_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,1,0xfffffffd) #define SET_RG_RSSI_EDGE_SEL_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,2,0xfffffffb) #define SET_RG_SIGN_SWAP_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,4,0xffffffef) #define SET_RG_IQ_SWAP_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,5,0xffffffdf) #define SET_RG_Q_INV_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,6,0xffffffbf) #define SET_RG_I_INV_BB(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,7,0xffffff7f) #define SET_RG_BYPASS_ACI(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,8,0xfffffeff) #define SET_RG_LBK_ANA_PATH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,9,0xfffffdff) #define SET_RG_LBK_DIG_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,10,0xfffffbff) #define SET_RG_RF_5G_BAND(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,11,0xfffff7ff) #define SET_RG_PRIMARY_CH_SIDE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,14,0xffffbfff) #define SET_RG_SYSTEM_BW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,15,0xffff7fff) #define SET_RG_11B_ACI_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,16,0xfffeffff) #define SET_RG_BB_CLK_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_SYS_REG,_VAL_,31,0x7fffffff) #define SET_RG_PHY_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,0,0xfffffffe) #define SET_RG_PHYRX_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,1,0xfffffffd) #define SET_RG_PHYTX_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,2,0xfffffffb) #define SET_RG_PHY11GN_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,3,0xfffffff7) #define SET_RG_PHY11B_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,4,0xffffffef) #define SET_RG_PHYRXFIFO_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,5,0xffffffdf) #define SET_RG_PHYTXFIFO_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,6,0xffffffbf) #define SET_RG_PHY11BGN_MD_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,8,0xfffffeff) #define SET_RG_FORCE_11GN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,12,0xffffefff) #define SET_RG_FORCE_11B_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,13,0xffffdfff) #define SET_RG_PHY_IQ_TRIG_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_ENABLE_REG,_VAL_,16,0xfff0ffff) #define SET_SVN_VERSION(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_VERSION_REG,_VAL_,0,0x00000000) #define SET_RG_LENGTH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,0,0xffff0000) #define SET_RG_PKT_MODE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,16,0xfff8ffff) #define SET_RG_CH_BW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,19,0xffc7ffff) #define SET_RG_PRM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,22,0xffbfffff) #define SET_RG_SHORTGI(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,23,0xff7fffff) #define SET_RG_RATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG0,_VAL_,24,0x80ffffff) #define SET_RG_L_LENGTH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG1,_VAL_,0,0xfffff000) #define SET_RG_L_RATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG1,_VAL_,12,0xffff8fff) #define SET_RG_SERVICE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG1,_VAL_,16,0x0000ffff) #define SET_RG_SMOOTHING(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,0,0xfffffffe) #define SET_RG_NO_SOUND(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,1,0xfffffffd) #define SET_RG_AGGREGATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,2,0xfffffffb) #define SET_RG_STBC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,3,0xffffffe7) #define SET_RG_FEC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,5,0xffffffdf) #define SET_RG_N_ESS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,6,0xffffff3f) #define SET_RG_TXPWRLVL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,8,0xffff80ff) #define SET_RG_BB_SCALE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG2,_VAL_,16,0xff00ffff) #define SET_RG_TX_START(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,0,0xfffffffe) #define SET_RG_IFS_TIME(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,2,0xffffff03) #define SET_RG_CONTINUOUS_DATA(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,8,0xfffffeff) #define SET_RG_DATA_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,9,0xfffff9ff) #define SET_RG_TX_D(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,16,0xff00ffff) #define SET_RG_IFS_TIME_EXT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG3,_VAL_,24,0x00ffffff) #define SET_RG_TX_CNT_TARGET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG4,_VAL_,0,0x00000000) #define SET_RG_TXD_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_CONTROL,_VAL_,10,0xfffff3ff) #define SET_RG_TX_FREQ_OFFSET_DES(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG5,_VAL_,0,0xffff0000) #define SET_RG_DES_RATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG6,_VAL_,0,0xffffff00) #define SET_RG_DES_MAN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_DES_REG6,_VAL_,31,0x7fffffff) #define SET_RG_PGA_REFDB_SAT_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,0,0xffffff80) #define SET_RG_PGA_REFDB_TOP_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,8,0xffff80ff) #define SET_RG_PGA_REF_UND_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_RF_REF_SAT_B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG0,_VAL_,28,0x0fffffff) #define SET_RG_PGA_REFDB_SAT_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,0,0xffffff80) #define SET_RG_PGA_REFDB_TOP_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,8,0xffff80ff) #define SET_RG_PGA_REF_UND_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,16,0xfc00ffff) #define SET_RG_RF_REF_SAT_GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG1,_VAL_,28,0x0fffffff) #define SET_RG_PGAGC_SET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,0,0xfffffff0) #define SET_RG_PGAGC_OW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,4,0xffffffef) #define SET_RG_RFGC_SET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,5,0xffffff9f) #define SET_RG_RFGC_OW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,7,0xffffff7f) #define SET_RG_WAIT_T_RXAGC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,8,0xffffc0ff) #define SET_RG_RXAGC_SET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,14,0xffffbfff) #define SET_RG_RXAGC_OW(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,15,0xffff7fff) #define SET_RG_WAIT_T_FINAL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,16,0xffc0ffff) #define SET_RG_WAIT_T(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG2,_VAL_,24,0xc0ffffff) #define SET_RG_ULG_PGA_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,0,0xfffffff0) #define SET_RG_LG_PGA_UND_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,4,0xffffff0f) #define SET_RG_LG_PGA_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,8,0xfffff0ff) #define SET_RG_LG_RF_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,12,0xffff0fff) #define SET_RG_MG_RF_SAT_PGANOREF_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,16,0xfff0ffff) #define SET_RG_HG_PGA_SAT2_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,20,0xff0fffff) #define SET_RG_HG_PGA_SAT1_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,24,0xf0ffffff) #define SET_RG_HG_RF_SAT_PGA_GAIN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG3,_VAL_,28,0x0fffffff) #define SET_RG_MG_PGA_JB_TH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG4,_VAL_,0,0xfffffff0) #define SET_RG_MA_PGA_LOW_TH_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG4,_VAL_,16,0xffe0ffff) #define SET_RG_MA_PGA_HIGH_TH_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_REG4,_VAL_,24,0xe0ffffff) #define SET_RG_AGC_THRESHOLD(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,0,0xffffc000) #define SET_RG_ACI_POINT_CNT_LMT_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,16,0xff80ffff) #define SET_RG_ACI_DAGC_LEAKY_FACTOR_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,24,0xfcffffff) #define SET_RG_ACI_DAGC_PWR_SEL_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0,_VAL_,28,0xefffffff) #define SET_RG_ACI_DAGC_TARGET_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,0,0xffffff80) #define SET_RG_ACI_GAIN_INI_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,8,0xffff00ff) #define SET_RG_ACI_GAIN_SET_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,16,0xff00ffff) #define SET_RG_ACI_GAIN_OW_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1,_VAL_,31,0x7fffffff) #define SET_RG_ACI_POINT_CNT_LMT_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,0,0xffffff00) #define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,8,0xfffffcff) #define SET_RG_ACI_DAGC_PWR_SEL_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,12,0xffffefff) #define SET_RG_ACI_DAGC_DONE_CNT_LMT_11GN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0,_VAL_,24,0x00ffffff) #define SET_RG_ACI_DAGC_TARGET_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1,_VAL_,0,0xffffff80) #define SET_RG_ACI_GAIN_SET_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1,_VAL_,16,0xfe00ffff) #define SET_RG_ACI_GAIN_OW_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1,_VAL_,31,0x7fffffff) #define SET_RO_CCA_PWR_MA_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,0,0xffffff80) #define SET_RO_CCA_PWR_MA_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,8,0xffff80ff) #define SET_RO_CCA_PWR_MA_11B(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,16,0xff80ffff) #define SET_RO_ED_STATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,24,0xfeffffff) #define SET_RO_2ND_ED_STATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG,_VAL_,25,0xfdffffff) #define SET_RO_PGA_PWR_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,0,0xffffc000) #define SET_RO_RF_PWR_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,16,0xfff0ffff) #define SET_RO_PGAGC_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,24,0xf0ffffff) #define SET_RO_RFGC_FF1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO00,_VAL_,28,0xcfffffff) #define SET_RO_PGA_PWR_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,0,0xffffc000) #define SET_RO_RF_PWR_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,16,0xfff0ffff) #define SET_RO_PGAGC_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,24,0xf0ffffff) #define SET_RO_RFGC_FF2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO01,_VAL_,28,0xcfffffff) #define SET_RO_PGA_PWR_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,0,0xffffc000) #define SET_RO_RF_PWR_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,16,0xfff0ffff) #define SET_RO_PGAGC_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,24,0xf0ffffff) #define SET_RO_RFGC_FF3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RFAGC_RO02,_VAL_,28,0xcfffffff) #define SET_RG_5G_DC_RM_LEAKY_FACTOR_T3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,4,0xffffff8f) #define SET_RG_5G_DC_RM_LEAKY_FACTOR_T2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,8,0xfffff8ff) #define SET_RG_5G_DC_RM_LEAKY_FACTOR_T1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,12,0xffff8fff) #define SET_RG_DC_RM_BYP(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,16,0xfffeffff) #define SET_RG_DC_RM_LEAKY_FACTOR_T3(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,20,0xff8fffff) #define SET_RG_DC_RM_LEAKY_FACTOR_T2(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,24,0xf8ffffff) #define SET_RG_DC_RM_LEAKY_FACTOR_T1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC,_VAL_,28,0x8fffffff) #define SET_RO_Q_DC_OUT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC_RO,_VAL_,0,0xfffffc00) #define SET_RO_I_DC_OUT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RXDC_RO,_VAL_,16,0xfc00ffff) #define SET_RG_TBUS_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG,_VAL_,0,0xfffffff0) #define SET_RG_RSSI_OFFSET(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG,_VAL_,16,0xff00ffff) #define SET_RG_RSSI_INV(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG,_VAL_,24,0xfeffffff) #define SET_RO_MRX_EN_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG,_VAL_,0,0xffff0000) #define SET_RG_MRX_EN_CNT_RST_N(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG,_VAL_,31,0x7fffffff) #define SET_RG_EDCCA_AVG_T(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_0,_VAL_,0,0xfffffff8) #define SET_RG_EDCCA_STAT_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_0,_VAL_,4,0xffffffef) #define SET_RO_EDCCA_PRIMARY_PRD(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_1,_VAL_,0,0xffff0000) #define SET_RO_PRIMARY_EDCCA(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_1,_VAL_,16,0x0000ffff) #define SET_RO_EDCCA_SECONDARY_PRD(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_2,_VAL_,0,0xffff0000) #define SET_RO_SECONDARY_EDCCA(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_EDCCA_2,_VAL_,16,0x0000ffff) #define SET_RG_AGC_RELOCK_PWR_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,0,0xffffc000) #define SET_RG_AGC_RELOCK_CNT_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,16,0xffc0ffff) #define SET_RG_AGC_RELOCK_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,24,0xfcffffff) #define SET_RG_AGC_RELOCK_EN(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,28,0xefffffff) #define SET_RG_AGC_RELOCK_11GN(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,30,0xbfffffff) #define SET_RG_AGC_RELOCK_11B(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_1,_VAL_,31,0x7fffffff) #define SET_RG_AGC_RELOCK_PWR_DIFFDB_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_2,_VAL_,0,0xffffff80) #define SET_RG_AGC_RELOCK_CNT_DIFFDB_TH(_VAL_) SET_REG(ADR_WIFI_PHY_AGC_RELOCK_2,_VAL_,16,0xffc0ffff) #define SET_RG_MTX_LEN_LOWER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0,_VAL_,0,0xffff0000) #define SET_RG_MTX_LEN_UPPER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0,_VAL_,16,0x0000ffff) #define SET_RG_MTX_LEN_LOWER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1,_VAL_,0,0xffff0000) #define SET_RG_MTX_LEN_UPPER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1,_VAL_,16,0x0000ffff) #define SET_RG_MRX_LEN_LOWER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0,_VAL_,0,0xffff0000) #define SET_RG_MRX_LEN_UPPER_TH_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0,_VAL_,16,0x0000ffff) #define SET_RG_MRX_LEN_LOWER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1,_VAL_,0,0xffff0000) #define SET_RG_MRX_LEN_UPPER_TH_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1,_VAL_,16,0x0000ffff) #define SET_RO_MTX_LEN_CNT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO,_VAL_,0,0xffff0000) #define SET_RO_MTX_LEN_CNT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO,_VAL_,16,0x0000ffff) #define SET_RO_MRX_LEN_CNT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO,_VAL_,0,0xffff0000) #define SET_RO_MRX_LEN_CNT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO,_VAL_,16,0x0000ffff) #define SET_RG_MRX_TYPE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,0,0xffffff00) #define SET_RG_MRX_TYPE_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,8,0xffffe0ff) #define SET_RG_MTX_TYPE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,16,0xff00ffff) #define SET_RG_MTX_TYPE_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG,_VAL_,24,0xe0ffffff) #define SET_RO_MRX_TYPE_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO,_VAL_,0,0xffff0000) #define SET_RO_MTX_TYPE_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO,_VAL_,16,0x0000ffff) #define SET_RG_ACI_POINT_CNT_LMT_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0,_VAL_,0,0xffffff00) #define SET_RG_ACI_DAGC_LEAKY_FACTOR_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0,_VAL_,8,0xfffffcff) #define SET_RG_ACI_DAGC_PWR_SEL_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0,_VAL_,12,0xffffefff) #define SET_RG_ACI_DAGC_TARGET_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1,_VAL_,0,0xffffff80) #define SET_RG_ACI_GAIN_SET_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1,_VAL_,16,0xfe00ffff) #define SET_RG_ACI_GAIN_OW_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1,_VAL_,31,0x7fffffff) #define SET_RG_ACI_GAIN_INI_11GN_HT40(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG,_VAL_,0,0xfffffe00) #define SET_RG_ACI_GAIN_INI_11GN_HT20(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG,_VAL_,16,0xfe00ffff) #define SET_RG_MAC_PKT_MODE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,0,0xfffffffe) #define SET_RG_MAC_PKT_AGGREGATE(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,1,0xfffffffd) #define SET_RG_MAC_PKT_ADDR4_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,4,0xffffffef) #define SET_RG_MAC_PKT_SEQ_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,5,0xffffffdf) #define SET_RG_MAC_PKT_ADDR3_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,6,0xffffffbf) #define SET_RG_MAC_PKT_ADDR2_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,7,0xffffff7f) #define SET_RG_MAC_PKT_AGGREGATE_NUM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,8,0xfffff0ff) #define SET_RG_MAC_PKT_PLD_LENGTH(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0,_VAL_,16,0x0000ffff) #define SET_RG_MAC_PKT_DUR(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1,_VAL_,0,0xffff0000) #define SET_RG_MAC_PKT_FC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1,_VAL_,16,0x0000ffff) #define SET_RG_MAC_PKT_ADDR1_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2,_VAL_,0,0x00000000) #define SET_RG_MAC_PKT_ADDR1_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3,_VAL_,0,0xffff0000) #define SET_RG_MAC_PKT_ADDR2_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4,_VAL_,0,0x00000000) #define SET_RG_MAC_PKT_ADDR2_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5,_VAL_,0,0xffff0000) #define SET_RG_MAC_PKT_ADDR3_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6,_VAL_,0,0x00000000) #define SET_RG_MAC_PKT_ADDR3_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7,_VAL_,0,0xffff0000) #define SET_RG_MAC_PKT_SEQ(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8,_VAL_,0,0xffff0000) #define SET_RG_MAC_PKT_ADDR4_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9,_VAL_,0,0x00000000) #define SET_RG_MAC_PKT_ADDR4_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A,_VAL_,0,0xffff0000) #define SET_RG_BB_SCALE_BARKER_CCK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0,_VAL_,0,0xffffff00) #define SET_RG_BB_SCALE_MAN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0,_VAL_,16,0xfffeffff) #define SET_RG_BB_SCALE_LEGACY_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,0,0xffffff00) #define SET_RG_BB_SCALE_LEGACY_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,8,0xffff00ff) #define SET_RG_BB_SCALE_LEGACY_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,16,0xff00ffff) #define SET_RG_BB_SCALE_LEGACY_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1,_VAL_,24,0x00ffffff) #define SET_RG_BB_SCALE_HT20_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,0,0xffffff00) #define SET_RG_BB_SCALE_HT20_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,8,0xffff00ff) #define SET_RG_BB_SCALE_HT20_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,16,0xff00ffff) #define SET_RG_BB_SCALE_HT20_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2,_VAL_,24,0x00ffffff) #define SET_RG_BB_SCALE_HT40_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,0,0xffffff00) #define SET_RG_BB_SCALE_HT40_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,8,0xffff00ff) #define SET_RG_BB_SCALE_HT40_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,16,0xff00ffff) #define SET_RG_BB_SCALE_HT40_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3,_VAL_,24,0x00ffffff) #define SET_RG_RF_PWR_BARKER_CCK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0,_VAL_,0,0xffffff80) #define SET_RG_RF_PWR_MAN_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0,_VAL_,16,0xfffeffff) #define SET_RG_RF_PWR_LEGACY_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,0,0xffffff80) #define SET_RG_RF_PWR_LEGACY_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,8,0xffff80ff) #define SET_RG_RF_PWR_LEGACY_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,16,0xff80ffff) #define SET_RG_RF_PWR_LEGACY_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1,_VAL_,24,0x80ffffff) #define SET_RG_RF_PWR_HT20_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,0,0xffffff80) #define SET_RG_RF_PWR_HT20_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,8,0xffff80ff) #define SET_RG_RF_PWR_HT20_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,16,0xff80ffff) #define SET_RG_RF_PWR_HT20_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2,_VAL_,24,0x80ffffff) #define SET_RG_RF_PWR_HT40_64QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,0,0xffffff80) #define SET_RG_RF_PWR_HT40_16QAM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,8,0xffff80ff) #define SET_RG_RF_PWR_HT40_QPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,16,0xff80ffff) #define SET_RG_RF_PWR_HT40_BPSK(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3,_VAL_,24,0x80ffffff) #define SET_RG_RX_MONITOR_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,0,0xfffffffe) #define SET_RG_RX_PKT_ADDR3_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,1,0xfffffffd) #define SET_RG_RX_PKT_ADDR2_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,2,0xfffffffb) #define SET_RG_RX_PKT_ADDR1_ON(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,3,0xfffffff7) #define SET_RG_RX_BEACON_TU(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,4,0xffffc00f) #define SET_RG_RX_PKT_TIMER_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_0,_VAL_,16,0x0000ffff) #define SET_RG_RX_BEACON_LOSS_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_1,_VAL_,0,0xffffff00) #define SET_RG_RX_BEACON_CRC_BYPASS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_1,_VAL_,8,0xfffffeff) #define SET_RG_RX_BEACON_INTERVAL(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_1,_VAL_,16,0x0000ffff) #define SET_RG_RX_PKT_FC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_2,_VAL_,16,0x0000ffff) #define SET_RG_RX_PKT_ADDR1_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_3,_VAL_,0,0x00000000) #define SET_RG_RX_PKT_ADDR1_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_4,_VAL_,0,0xffff0000) #define SET_RG_RX_PKT_ADDR2_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_5,_VAL_,0,0x00000000) #define SET_RG_RX_PKT_ADDR2_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_6,_VAL_,0,0xffff0000) #define SET_RG_RX_PKT_ADDR3_31_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_7,_VAL_,0,0x00000000) #define SET_RG_RX_PKT_ADDR3_47_32(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_MON_8,_VAL_,0,0xffff0000) #define SET_RO_INTRP_RX_LOSS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO,_VAL_,0,0xfffffffe) #define SET_RO_RX_PKT_TIMER(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO,_VAL_,16,0x0000ffff) #define SET_RO_INTRP_RX_BEACON_LOSS(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO,_VAL_,0,0xfffffffe) #define SET_RO_RX_BEACON_LOSS_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO,_VAL_,8,0xffff00ff) #define SET_RO_RX_BEACON_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO,_VAL_,16,0x0000ffff) #define SET_RG_RX_FIFO_FULL_CNT_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL,_VAL_,0,0xfffffffe) #define SET_RG_TX_FIFO_EMPTY_CNT_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL,_VAL_,4,0xffffffef) #define SET_RO_RX_FIFO_FULL_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO,_VAL_,0,0xffff0000) #define SET_RO_TX_FIFO_EMPTY_CNT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO,_VAL_,16,0x0000ffff) #define SET_RG_BIST_EN_RX_FFT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,0,0xfffffffe) #define SET_RG_BIST_MODE_RX_FFT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,4,0xffffffef) #define SET_RO_BIST_DONE_RX_FFT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,16,0xfffeffff) #define SET_RO_BIST_FAIL_RX_FFT_1(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,17,0xfffdffff) #define SET_RO_BIST_DONE_RX_FFT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,20,0xffefffff) #define SET_RO_BIST_FAIL_RX_FFT_0(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG,_VAL_,21,0xffdfffff) #define SET_RG_AUDIO_CLK_EN(_VAL_) SET_REG(ADR_WIFI_PHY_AUDIO_CLK_CTRL,_VAL_,0,0xfffffffe) #define SET_RG_AUDIO_CLK_SEL(_VAL_) SET_REG(ADR_WIFI_PHY_AUDIO_CLK_CTRL,_VAL_,1,0xfffffffd) #define SET_RO_CSTATE_PKT(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,0,0xfffffffc) #define SET_RO_MRX_RX_EN(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,4,0xffffffef) #define SET_RO_CSTATE_AGC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,8,0xfffffcff) #define SET_RO_AGC_START_80M(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,12,0xffffefff) #define SET_RO_CSTATE_RX(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,16,0xfff0ffff) #define SET_RO_TX_IP(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,20,0xffefffff) #define SET_RO_CSTATE_TX(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,24,0xf0ffffff) #define SET_RO_MAC_PHY_TRX_EN_SYNC(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO,_VAL_,28,0xefffffff) #define SET_RG_RESERVED_CMM(_VAL_) SET_REG(ADR_WIFI_PHY_COMMON_RESERVED_REG,_VAL_,0,0x00000000) #define SET_RG_BB_RISE_TIME_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_BB_RAMP_REG,_VAL_,0,0xffffff00) #define SET_RG_BB_FALL_TIME_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_BB_RAMP_REG,_VAL_,8,0xffff00ff) #define SET_RG_BP_SMB(_VAL_) SET_REG(ADR_WIFI_11B_TX_BB_RAMP_REG,_VAL_,16,0xfffeffff) #define SET_RO_TX_CNT_R_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_PKT_CNT_SENT_REG,_VAL_,0,0x00000000) #define SET_RG_DEBUG_SEL_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_DEBUG_SEL_REG,_VAL_,0,0xfffffff0) #define SET_RG_RESERVED_11B_TX(_VAL_) SET_REG(ADR_WIFI_11B_TX_RESERVED_REG,_VAL_,0,0x00000000) #define SET_RG_POS_DES_L_EXT_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_000,_VAL_,0,0xfffffff0) #define SET_RG_PRE_DES_DLY_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_000,_VAL_,4,0xffffff0f) #define SET_RG_CCA_RE_CHK_BIT_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_000,_VAL_,8,0xfffff0ff) #define SET_RG_CNT_CCA_RE_CHK_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_001,_VAL_,16,0xfff0ffff) #define SET_RG_BYPASS_DESCRAMBLER(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_001,_VAL_,29,0xdfffffff) #define SET_RG_CCA_BIT_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_002,_VAL_,4,0xffffff0f) #define SET_RG_CCA_SCALE_BF(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_002,_VAL_,16,0xff80ffff) #define SET_RG_PEAK_IDX_CNT_SEL(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_002,_VAL_,28,0xcfffffff) #define SET_RG_TR_KI_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,0,0xfffffff8) #define SET_RG_TR_KP_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,4,0xffffff8f) #define SET_RG_TR_KI_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,8,0xfffff8ff) #define SET_RG_TR_KP_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_003,_VAL_,12,0xffff8fff) #define SET_RG_CR_KI_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_004,_VAL_,16,0xfff8ffff) #define SET_RG_CR_KP_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_004,_VAL_,20,0xff8fffff) #define SET_RG_CHIP_CNT_SLICER(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_005,_VAL_,0,0xffffffe0) #define SET_RG_CE_T2_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_005,_VAL_,24,0x00ffffff) #define SET_RG_CE_MU_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_006,_VAL_,0,0xfffffff8) #define SET_RG_CE_DLY_SEL(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_006,_VAL_,16,0xffc0ffff) #define SET_RG_CE_MU_T4(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_007,_VAL_,0,0xfffffff8) #define SET_RG_CE_MU_T3(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_007,_VAL_,16,0xfff8ffff) #define SET_RG_CE_MU_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_007,_VAL_,24,0xf8ffffff) #define SET_RG_EQ_MU_FB_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,0,0xfffffff0) #define SET_RG_EQ_MU_FF_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,4,0xffffff0f) #define SET_RG_EQ_MU_FB_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,16,0xfff0ffff) #define SET_RG_EQ_MU_FF_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_008,_VAL_,20,0xff0fffff) #define SET_RG_EQ_MU_FB_T4(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,0,0xfffffff0) #define SET_RG_EQ_MU_FF_T4(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,4,0xffffff0f) #define SET_RG_EQ_MU_FB_T3(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,16,0xfff0ffff) #define SET_RG_EQ_MU_FF_T3(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_009,_VAL_,20,0xff0fffff) #define SET_RG_EQ_KI_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,8,0xfffff8ff) #define SET_RG_EQ_KP_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,12,0xffff8fff) #define SET_RG_EQ_KI_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,16,0xfff8ffff) #define SET_RG_EQ_KP_T1(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_010,_VAL_,20,0xff8fffff) #define SET_RG_TR_LPF_RATE(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_011,_VAL_,0,0xffc00000) #define SET_RG_CE_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,0,0xffffff80) #define SET_RG_CE_CH_MAIN_SET(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,7,0xffffff7f) #define SET_RG_TC_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,8,0xffff80ff) #define SET_RG_CR_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,16,0xff80ffff) #define SET_RG_TR_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_012,_VAL_,24,0x80ffffff) #define SET_RG_EQ_MAIN_TAP_MAN(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_013,_VAL_,0,0xfffffffe) #define SET_RG_EQ_MAIN_TAP_COEF(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_013,_VAL_,16,0xf800ffff) #define SET_RG_CCK_TR_KI_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_014,_VAL_,0,0xfffffff8) #define SET_RG_CCK_TR_KP_T2(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_014,_VAL_,4,0xffffff8f) #define SET_RG_PWRON_DLY_TH_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_039,_VAL_,0,0xffffff00) #define SET_RG_SFD_BIT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_039,_VAL_,16,0xff00ffff) #define SET_RG_PWR_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_040,_VAL_,0,0xffff0000) #define SET_RG_PWR_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_040,_VAL_,16,0xffe0ffff) #define SET_RG_PWR_BIT_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_040,_VAL_,24,0xf0ffffff) #define SET_RG_PSDU_TIME_OFFSET_11B(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_041,_VAL_,0,0xffff0000) #define SET_RG_RESERVED_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_240,_VAL_,0,0x00000000) #define SET_RG_INTRUP_RX_11B_CLEAR(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,0,0xfffffffe) #define SET_RG_INTRUP_RX_11B_MASK(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,4,0xffffffef) #define SET_RG_INTRUP_RX_11B_TRIG(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,8,0xfffff0ff) #define SET_RO_INTRUP_RX_11B(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_241,_VAL_,16,0xfffeffff) #define SET_RO_11B_FREQ_OS(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_245,_VAL_,0,0xfffff800) #define SET_RO_11B_SNR(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_246,_VAL_,0,0xffffff80) #define SET_RO_11B_RCPI(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_246,_VAL_,16,0xff80ffff) #define SET_RO_11B_CRC_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_249,_VAL_,0,0xffff0000) #define SET_RO_11B_SFD_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_249,_VAL_,16,0x0000ffff) #define SET_RO_11B_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_250,_VAL_,0,0xffff0000) #define SET_RO_11B_PACKET_ERR(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_250,_VAL_,16,0xfffeffff) #define SET_RO_11B_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_251,_VAL_,0,0xffff0000) #define SET_RO_11B_CCA_CNT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_251,_VAL_,16,0x0000ffff) #define SET_RO_11B_LENGTH_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_252,_VAL_,0,0xffff0000) #define SET_RO_11B_SFD_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_252,_VAL_,16,0x0000ffff) #define SET_RO_11B_SIGNAL_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_253,_VAL_,0,0xffffff00) #define SET_RO_11B_SERVICE_FIELD(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_253,_VAL_,8,0xffff00ff) #define SET_RO_11B_CRC_CORRECT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_253,_VAL_,16,0xfffeffff) #define SET_RG_RATE_STAT(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_254,_VAL_,16,0xfff8ffff) #define SET_RG_PACKET_STAT_EN_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_254,_VAL_,20,0xffefffff) #define SET_RG_BIT_REVERSE(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_254,_VAL_,21,0xffdfffff) #define SET_RG_SOFT_RST_N_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,0,0xfffffffe) #define SET_RG_CE_BYPASS_TAP(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,4,0xffffff0f) #define SET_RG_EQ_BYPASS_FBW_TAP(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,8,0xfffff0ff) #define SET_RG_DEBUG_SEL_11B_RX(_VAL_) SET_REG(ADR_WIFI_11B_RX_REG_255,_VAL_,16,0xfff0ffff) #define SET_RG_BIST_EN_TX_FFT(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,0,0xfffffffe) #define SET_RG_BIST_MODE_TX_FFT(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,4,0xffffffef) #define SET_RO_BIST_DONE_TX_FFT_1(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,16,0xfffeffff) #define SET_RO_BIST_FAIL_TX_FFT_1(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,17,0xfffdffff) #define SET_RO_BIST_DONE_TX_FFT_0(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,20,0xffefffff) #define SET_RO_BIST_FAIL_TX_FFT_0(_VAL_) SET_REG(ADR_WIFI_11GN_TX_MEM_BIST_REG,_VAL_,21,0xffdfffff) #define SET_RG_BB_RISE_TIME_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_BB_RAMP_REG,_VAL_,0,0xffffff00) #define SET_RG_BB_FALL_TIME_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_BB_RAMP_REG,_VAL_,8,0xffff00ff) #define SET_RG_TX_CLK_OUTER_EN(_VAL_) SET_REG(ADR_WIFI_11GN_TX_CONTROL_REG,_VAL_,0,0xfffffffe) #define SET_RG_SHORT_GI_EN(_VAL_) SET_REG(ADR_WIFI_11GN_TX_CONTROL_REG,_VAL_,4,0xffffffef) #define SET_RG_STF_SCALE_20(_VAL_) SET_REG(ADR_WIFI_11GN_TX_STS_SCALE_REG,_VAL_,0,0xfffffc00) #define SET_RG_STF_SCALE_40(_VAL_) SET_REG(ADR_WIFI_11GN_TX_STS_SCALE_REG,_VAL_,16,0xfc00ffff) #define SET_RG_FFT_SCALE_104(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG0,_VAL_,0,0xfffffc00) #define SET_RG_FFT_SCALE_114(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG0,_VAL_,16,0xfc00ffff) #define SET_RG_FFT_SCALE_52(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,0,0xfffffc00) #define SET_RG_FFT_SCALE_56(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,12,0xffc00fff) #define SET_RG_SCR_INIT_SEED(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,24,0x80ffffff) #define SET_RG_SCR_SEED_MANUANL(_VAL_) SET_REG(ADR_WIFI_11GN_TX_FFT_SCALE_REG1,_VAL_,31,0x7fffffff) #define SET_RO_TX_CNT_R_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG,_VAL_,0,0x00000000) #define SET_RG_DEBUG_SEL_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_DEBUG_SEL_REG,_VAL_,8,0xfffff0ff) #define SET_RG_RESERVED_11GN_TX(_VAL_) SET_REG(ADR_WIFI_11GN_TX_RESERVED_REG,_VAL_,0,0x00000000) #define SET_RG_POS_DES_L_EXT_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_000,_VAL_,0,0xfffffff0) #define SET_RG_PRE_DES_DLY_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_000,_VAL_,4,0xffffff0f) #define SET_RG_RESERVED_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_001,_VAL_,0,0x00000000) #define SET_RG_HT40_TR_LPF_KI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_002,_VAL_,0,0xfffffff0) #define SET_RG_HT40_TR_LPF_KP(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_002,_VAL_,4,0xffffff0f) #define SET_RG_HT40_SYM_BOUND_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_002,_VAL_,8,0xffff80ff) #define SET_RG_HT20_TR_LPF_KI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_003,_VAL_,0,0xfffffff0) #define SET_RG_HT20_TR_LPF_KP(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_003,_VAL_,4,0xffffff0f) #define SET_RG_TR_LPF_RATE_GN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_003,_VAL_,8,0xc00000ff) #define SET_RG_CR_LPF_KI_GN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,0,0xfffffff8) #define SET_RG_HT20_SYM_BOUND_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,8,0xffff80ff) #define SET_RG_XSCOR32_RATIO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,16,0xff80ffff) #define SET_RG_ATCOR64_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_004_,_VAL_,24,0x80ffffff) #define SET_RG_ATCOR16_CNT_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_005,_VAL_,8,0xffff80ff) #define SET_RG_ATCOR16_CNT_LMT1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_005,_VAL_,16,0xff80ffff) #define SET_RG_ATCOR16_RATIO_SB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_005,_VAL_,24,0x80ffffff) #define SET_RG_XSCOR64_CNT_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_006_,_VAL_,16,0xff80ffff) #define SET_RG_XSCOR64_CNT_LMT1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_006_,_VAL_,24,0x80ffffff) #define SET_RG_HT20_RX_FFT_SCALE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_007_,_VAL_,0,0xfffffc00) #define SET_RG_VITERBI_AB_SWAP(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_007_,_VAL_,16,0xfffeffff) #define SET_RG_ATCOR16_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_007_,_VAL_,24,0xf0ffffff) #define SET_RG_NORMSQUARE_LOW_SNR_7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,0,0xffffff00) #define SET_RG_NORMSQUARE_LOW_SNR_6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,8,0xffff00ff) #define SET_RG_NORMSQUARE_LOW_SNR_5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,16,0xff00ffff) #define SET_RG_NORMSQUARE_LOW_SNR_4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_008,_VAL_,24,0x00ffffff) #define SET_RG_NORMSQUARE_LOW_SNR_8(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_009,_VAL_,24,0x00ffffff) #define SET_RG_NORMSQUARE_SNR_3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,0,0xffffff00) #define SET_RG_NORMSQUARE_SNR_2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,8,0xffff00ff) #define SET_RG_NORMSQUARE_SNR_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,16,0xff00ffff) #define SET_RG_NORMSQUARE_SNR_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_010_,_VAL_,24,0x00ffffff) #define SET_RG_NORMSQUARE_SNR_7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,0,0xffffff00) #define SET_RG_NORMSQUARE_SNR_6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,8,0xffff00ff) #define SET_RG_NORMSQUARE_SNR_5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,16,0xff00ffff) #define SET_RG_NORMSQUARE_SNR_4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_011,_VAL_,24,0x00ffffff) #define SET_RG_NORMSQUARE_SNR_8(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_012,_VAL_,24,0x00ffffff) #define SET_RG_SNR_TH_64QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_013,_VAL_,0,0xffffff80) #define SET_RG_SNR_TH_16QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_013,_VAL_,8,0xffff80ff) #define SET_RG_ATCOR16_CNT_PLUS_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_014,_VAL_,0,0xffffff80) #define SET_RG_ATCOR16_CNT_PLUS_LMT1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_014,_VAL_,8,0xffff80ff) #define SET_RG_SYM_BOUND_METHOD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_014,_VAL_,16,0xfffcffff) #define SET_RG_HT40_RX_FFT_SCALE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_015,_VAL_,0,0xfffffc00) #define SET_RG_ERASE_SC_NUM3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,0,0xffffff80) #define SET_RG_SC_CTRL3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,7,0xffffff7f) #define SET_RG_ERASE_SC_NUM2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,8,0xffff80ff) #define SET_RG_SC_CTRL2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,15,0xffff7fff) #define SET_RG_ERASE_SC_NUM1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,16,0xff80ffff) #define SET_RG_SC_CTRL1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,23,0xff7fffff) #define SET_RG_ERASE_SC_NUM0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,24,0x80ffffff) #define SET_RG_SC_CTRL0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_016,_VAL_,31,0x7fffffff) #define SET_RG_ERASE_SC_NUM7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,0,0xffffff80) #define SET_RG_SC_CTRL7(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,7,0xffffff7f) #define SET_RG_ERASE_SC_NUM6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,8,0xffff80ff) #define SET_RG_SC_CTRL6(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,15,0xffff7fff) #define SET_RG_ERASE_SC_NUM5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,16,0xff80ffff) #define SET_RG_SC_CTRL5(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,23,0xff7fffff) #define SET_RG_ERASE_SC_NUM4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,24,0x80ffffff) #define SET_RG_SC_CTRL4(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_017,_VAL_,31,0x7fffffff) #define SET_RG_BIST_EN_CCFO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,0,0xfffffffe) #define SET_RG_BIST_MODE_CCFO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,4,0xffffffef) #define SET_RO_BIST_DONE_CCFO_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,16,0xfffeffff) #define SET_RO_BIST_FAIL_CCFO_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,17,0xfffdffff) #define SET_RO_BIST_DONE_CCFO_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,20,0xffefffff) #define SET_RO_BIST_FAIL_CCFO_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_032,_VAL_,21,0xffdfffff) #define SET_RG_BIST_EN_VTB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,0,0xfffffffe) #define SET_RG_BIST_MODE_VTB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,4,0xffffffef) #define SET_RO_BIST_DONE_VTB_3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,16,0xfffeffff) #define SET_RO_BIST_FAIL_VTB_3(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,17,0xfffdffff) #define SET_RO_BIST_DONE_VTB_2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,20,0xffefffff) #define SET_RO_BIST_FAIL_VTB_2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,21,0xffdfffff) #define SET_RO_BIST_DONE_VTB_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,24,0xfeffffff) #define SET_RO_BIST_FAIL_VTB_1(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,25,0xfdffffff) #define SET_RO_BIST_DONE_VTB_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,28,0xefffffff) #define SET_RO_BIST_FAIL_VTB_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_033,_VAL_,29,0xdfffffff) #define SET_RG_PWRON_DLY_TH_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_039,_VAL_,0,0xffffff00) #define SET_RG_SB_START_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_039,_VAL_,8,0xffff80ff) #define SET_RG_CCA_POW_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_040,_VAL_,4,0xffffff0f) #define SET_RG_CCA_POW_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_040,_VAL_,8,0xfffff8ff) #define SET_RG_CCA_POW_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_040,_VAL_,16,0x0000ffff) #define SET_RG_POW16_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_048,_VAL_,4,0xffffff0f) #define SET_RG_POW16_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_048,_VAL_,8,0xfffff8ff) #define SET_RG_POW16_TH_L(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_048,_VAL_,24,0x00ffffff) #define SET_RG_XSCOR16_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,0,0xfffffff8) #define SET_RG_XSCOR16_RATIO(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,8,0xffff80ff) #define SET_RG_ATCOR16_SHORT_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,16,0xfff8ffff) #define SET_RG_ATCOR16_RATIO_CCD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_049,_VAL_,24,0x80ffffff) #define SET_RG_ATCOR64_ACC_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_050,_VAL_,0,0xffffff80) #define SET_RG_ATCOR16_SHORT_CNT_LMT2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_050,_VAL_,16,0xfff8ffff) #define SET_RG_CCFO_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,0,0xffffff80) #define SET_RG_BYPASS_COARSE_FREQ(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,8,0xfffffeff) #define SET_RG_CCFO_GAIN_BY2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,9,0xfffffdff) #define SET_RG_XSCOR64_RATIO_SB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_051,_VAL_,16,0xff80ffff) #define SET_RG_5G_CCFO_CNT_LMT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_052,_VAL_,0,0xffffff80) #define SET_RG_5G_BYPASS_COARSE_FREQ(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_052,_VAL_,8,0xfffffeff) #define SET_RG_5G_CCFO_GAIN_BY2(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_052,_VAL_,9,0xfffffdff) #define SET_RG_ACS_INI_PM_ALL0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_076,_VAL_,0,0xfffffffe) #define SET_RG_VITERBI_TB_BITS(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_076,_VAL_,24,0x00ffffff) #define SET_RG_CR_CNT_UPDATE_SGI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_087,_VAL_,0,0xfffffe00) #define SET_RG_TR_CNT_UPDATE_SGI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_087,_VAL_,16,0xfe00ffff) #define SET_RG_CR_CNT_UPDATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_088,_VAL_,0,0xfffffe00) #define SET_RG_TR_CNT_UPDATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_088,_VAL_,16,0xfe00ffff) #define SET_RG_CPE_SEL_64QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,16,0xfffeffff) #define SET_RG_CPE_SEL_16QAM(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,17,0xfffdffff) #define SET_RG_CPE_SEL_QPSK(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,18,0xfffbffff) #define SET_RG_CPE_SEL_BPSK(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_089,_VAL_,19,0xfff7ffff) #define SET_RG_BYPASS_CPE_MA(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_096,_VAL_,4,0xffffffef) #define SET_RG_CHSMTH_COEF(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,16,0xfffcffff) #define SET_RG_CHSMTH_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,18,0xfffbffff) #define SET_RG_CHEST_DD_FACTOR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,24,0xf8ffffff) #define SET_RG_CH_UPDATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_098,_VAL_,31,0x7fffffff) #define SET_RG_FMT_DET_MM_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_100,_VAL_,0,0xffffff00) #define SET_RG_FMT_DET_GF_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_100,_VAL_,8,0xffff00ff) #define SET_RG_DO_NOT_CHECK_L_RATE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_100,_VAL_,25,0xfdffffff) #define SET_RG_NEW_PILOT_AVG(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,0,0xfffffffe) #define SET_RG_NEW_SB(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,4,0xffffffef) #define SET_RG_ATCOR64_FREQ_START(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,8,0xffff80ff) #define SET_RG_L_LENGTH_MAX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,16,0xf000ffff) #define SET_RG_ATCOR16_CCA_GAIN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_101,_VAL_,28,0xcfffffff) #define SET_RG_PSDU_TIME_OFFSET_GF(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_102,_VAL_,0,0xffff0000) #define SET_RG_PSDU_TIME_OFFSET_MF(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_102,_VAL_,16,0x0000ffff) #define SET_RG_PSDU_TIME_OFFSET_LEGACY(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_103,_VAL_,0,0xffff0000) #define SET_RG_INTRUP_RX_11GN_CLEAR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,0,0xfffffffe) #define SET_RG_INTRUP_RX_11GN_MASK(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,4,0xffffffef) #define SET_RG_INTRUP_RX_11GN_TRIG(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,8,0xfffff0ff) #define SET_RO_INTRUP_RX_11GN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_241,_VAL_,16,0xfffeffff) #define SET_RO_STBC_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_245,_VAL_,0,0xffff0000) #define SET_RO_STBC_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_245,_VAL_,16,0x0000ffff) #define SET_RO_11GN_SNR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,0,0xffffff80) #define SET_RO_11GN_NOISE_PWR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,8,0xffff80ff) #define SET_RO_11GN_RCPI(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,16,0xff80ffff) #define SET_RO_11GN_SIGNAL_PWR(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_246,_VAL_,24,0x80ffffff) #define SET_RO_11GN_FREQ_OS_LTS(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_247,_VAL_,0,0xffff8000) #define SET_RO_11GN_HT_SIGNAL_FIELD_47_24(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_248,_VAL_,0,0xff000000) #define SET_RO_11GN_HT_SIGNAL_FIELD_23_0(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_249,_VAL_,0,0xff000000) #define SET_RO_11GN_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_250,_VAL_,0,0xffff0000) #define SET_RO_11GN_SERVICE_FIELD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_250,_VAL_,16,0x0000ffff) #define SET_RO_11GN_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_251,_VAL_,0,0xffff0000) #define SET_RO_11GN_CCA_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_251,_VAL_,16,0x0000ffff) #define SET_RO_11GN_L_SIGNAL_FIELD(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_252,_VAL_,0,0xff000000) #define SET_RO_AMPDU_PACKET_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_253,_VAL_,0,0xffff0000) #define SET_RO_AMPDU_PACKET_ERR_CNT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_253,_VAL_,16,0x0000ffff) #define SET_RG_DAGC_CNT_TH(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_254,_VAL_,0,0xfffffffc) #define SET_RG_RATE_MCS_STAT(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_254,_VAL_,16,0xfff0ffff) #define SET_RG_PACKET_STAT_EN_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_254,_VAL_,20,0xffefffff) #define SET_RG_SOFT_RST_N_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,0,0xfffffffe) #define SET_RG_RIFS_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,1,0xfffffffd) #define SET_RG_STBC_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,2,0xfffffffb) #define SET_RG_COR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,3,0xfffffff7) #define SET_RG_INI_PHASE(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,4,0xffffffcf) #define SET_RG_CCA_PWR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,9,0xfffffdff) #define SET_RG_CCA_XSCOR_PWR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,10,0xfffffbff) #define SET_RG_CCA_XSCOR_AVGPWR_SEL(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,11,0xfffff7ff) #define SET_RG_DEBUG_SEL_11GN_RX(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,12,0xffff0fff) #define SET_RG_POST_CLK_EN(_VAL_) SET_REG(ADR_WIFI_11GN_RX_REG_255,_VAL_,16,0xfffeffff) #define SET_RG_THL_ED(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,0,0xffffffc0) #define SET_RG_THH_ED(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,8,0xffffc0ff) #define SET_RG_THL_RATIO(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,16,0xff00ffff) #define SET_RG_THH_RATIO(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_00,_VAL_,24,0x00ffffff) #define SET_RG_PW_MIN(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_01,_VAL_,0,0xfffff000) #define SET_RG_PW_MAX(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_01,_VAL_,16,0xf000ffff) #define SET_RG_PERIOD_MIN(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_02,_VAL_,0,0xfffff000) #define SET_RG_PERIOD_MAX(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_02,_VAL_,16,0xf000ffff) #define SET_RG_TIME_PERIOD(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,0,0xfffff000) #define SET_RG_PULSE_NUMBER(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,20,0xff8fffff) #define SET_RG_ALPHA_FINE(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,24,0xf8ffffff) #define SET_RG_ALPHA_COARSE(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_03,_VAL_,28,0xcfffffff) #define SET_RG_RADAR_EN(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_04,_VAL_,0,0xfffffffe) #define SET_RG_TOLERANCE_PERIOD(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_04,_VAL_,16,0xffc0ffff) #define SET_RG_TOLERANCE_PW(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_04,_VAL_,24,0xc0ffffff) #define SET_RO_RADAR_DET_NUM(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,0,0xfffffff8) #define SET_RO_RADAR_DET_OUT(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,4,0xffffffef) #define SET_RO_RADAR_VALID(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,8,0xfffffeff) #define SET_RO_PW(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_RO,_VAL_,16,0xf000ffff) #define SET_RO_PW_ARRAY_0(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A0_RO,_VAL_,0,0xfffff000) #define SET_RO_PW_ARRAY_1(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A0_RO,_VAL_,16,0xf000ffff) #define SET_RO_PW_ARRAY_2(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A1_RO,_VAL_,0,0xfffff000) #define SET_RO_PW_ARRAY_3(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A1_RO,_VAL_,16,0xf000ffff) #define SET_RO_PW_ARRAY_4(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A2_RO,_VAL_,0,0xfffff000) #define SET_RO_PW_ARRAY_5(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_A2_RO,_VAL_,16,0xf000ffff) #define SET_RO_PERIOD_ARRAY_0(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P0_RO,_VAL_,0,0xfffff000) #define SET_RO_PERIOD_ARRAY_1(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P0_RO,_VAL_,16,0xf000ffff) #define SET_RO_PERIOD_ARRAY_2(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P1_RO,_VAL_,0,0xfffff000) #define SET_RO_PERIOD_ARRAY_3(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P1_RO,_VAL_,16,0xf000ffff) #define SET_RO_PERIOD_ARRAY_4(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P2_RO,_VAL_,0,0xfffff000) #define SET_RO_PERIOD_ARRAY_5(_VAL_) SET_REG(ADR_WIFI_RADAR_REG_DB_P2_RO,_VAL_,16,0xf000ffff) #define SET_RG_PW_CHIRP_MIN(_VAL_) SET_REG(ADR_WIFI_RADAR_CHIRP_REG,_VAL_,0,0xfffff000) #define SET_RG_PW_CHIRP_MAX(_VAL_) SET_REG(ADR_WIFI_RADAR_CHIRP_REG,_VAL_,16,0xf000ffff) #define SET_CPU_QUE_POP_ALT(_VAL_) SET_REG(ADR_MB_CPU_INT_ALT,_VAL_,0,0xfffffffe) #define SET_CPU_INT_ALT(_VAL_) SET_REG(ADR_MB_CPU_INT_ALT,_VAL_,2,0xfffffffb) #define SET_CPU_QUE_POP(_VAL_) SET_REG(ADR_MB_CPU_INT,_VAL_,0,0xfffffffe) #define SET_CPU_INT(_VAL_) SET_REG(ADR_MB_CPU_INT,_VAL_,2,0xfffffffb) #define SET_CPU_ID_TB0(_VAL_) SET_REG(ADR_CPU_ID_TB0,_VAL_,0,0x00000000) #define SET_CPU_ID_TB1(_VAL_) SET_REG(ADR_CPU_ID_TB1,_VAL_,0,0x00000000) #define SET_HW_PKTID(_VAL_) SET_REG(ADR_CH0_TRIG_1,_VAL_,0,0xfffff800) #define SET_CH0_INT_ADDR(_VAL_) SET_REG(ADR_CH0_TRIG_0,_VAL_,0,0x00000000) #define SET_PRI_HW_PKTID(_VAL_) SET_REG(ADR_CH0_PRI_TRIG,_VAL_,0,0xfffff800) #define SET_CH0_FULL(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,0,0xfffffffe) #define SET_FF0_EMPTY(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,1,0xfffffffd) #define SET_CH2_FULL(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,4,0xffffffef) #define SET_FF2_EMPTY(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,5,0xffffffdf) #define SET_RLS_BUSY(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,9,0xfffffdff) #define SET_RLS_COUNT_CLR(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,10,0xfffffbff) #define SET_RTN_COUNT_CLR(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,11,0xfffff7ff) #define SET_RLS_COUNT(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,16,0xff00ffff) #define SET_RTN_COUNT(_VAL_) SET_REG(ADR_MCU_STATUS,_VAL_,24,0x00ffffff) #define SET_FF0_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,0,0xffffffe0) #define SET_FF1_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,5,0xfffffe1f) #define SET_FF3_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,11,0xffffc7ff) #define SET_FF5_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,17,0xfff1ffff) #define SET_FF6_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,20,0xff8fffff) #define SET_FF7_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,23,0xfc7fffff) #define SET_FF8_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,26,0xe3ffffff) #define SET_FF9_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT1,_VAL_,29,0x1fffffff) #define SET_FF10_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,0,0xfffffff8) #define SET_FF11_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,3,0xffffffc7) #define SET_FF12_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,6,0xfffffe3f) #define SET_FF13_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,9,0xfffff1ff) #define SET_FF14_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,12,0xffff8fff) #define SET_FF15_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,15,0xfffc7fff) #define SET_FF4_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,18,0xff83ffff) #define SET_FF2_CNT(_VAL_) SET_REG(ADR_RD_IN_FFCNT2,_VAL_,23,0xfc7fffff) #define SET_CH0_FULL_ALT(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,0,0xfffffffe) #define SET_CH1_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,1,0xfffffffd) #define SET_CH2_FULL_ALT(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,2,0xfffffffb) #define SET_CH3_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,3,0xfffffff7) #define SET_CH4_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,4,0xffffffef) #define SET_CH5_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,5,0xffffffdf) #define SET_CH6_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,6,0xffffffbf) #define SET_CH7_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,7,0xffffff7f) #define SET_CH8_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,8,0xfffffeff) #define SET_CH9_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,9,0xfffffdff) #define SET_CH10_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,10,0xfffffbff) #define SET_CH11_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,11,0xfffff7ff) #define SET_CH12_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,12,0xffffefff) #define SET_CH13_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,13,0xffffdfff) #define SET_CH14_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,14,0xffffbfff) #define SET_CH15_FULL(_VAL_) SET_REG(ADR_RD_FFIN_FULL,_VAL_,15,0xffff7fff) #define SET_HW_PKTID_ALT(_VAL_) SET_REG(ADR_CH2_TRIG_ALT,_VAL_,0,0xfffff800) #define SET_CH2_INT_ADDR_ALT(_VAL_) SET_REG(ADR_CH2_INT_ADDR_ALT,_VAL_,0,0x00000000) #define SET_HALT_CH1(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,1,0xfffffffd) #define SET_HALT_CH3(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,3,0xfffffff7) #define SET_HALT_CH4(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,4,0xffffffef) #define SET_HALT_CH5(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,5,0xffffffdf) #define SET_HALT_CH6(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,6,0xffffffbf) #define SET_HALT_CH7(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,7,0xffffff7f) #define SET_HALT_CH8(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,8,0xfffffeff) #define SET_HALT_CH9(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,9,0xfffffdff) #define SET_HALT_CH10(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,10,0xfffffbff) #define SET_HALT_CH11(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,11,0xfffff7ff) #define SET_HALT_CH12(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,12,0xffffefff) #define SET_HALT_CH13(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,13,0xffffdfff) #define SET_HALT_CH14(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,14,0xffffbfff) #define SET_STOP_MBOX_OUT(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,16,0xfffeffff) #define SET_STOP_MBOX_IN(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,17,0xfffdffff) #define SET_MB_ERR_AUTO_HALT_EN(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,20,0xffefffff) #define SET_MB_EXCEPT_CLR(_VAL_) SET_REG(ADR_MBOX_HALT_CFG,_VAL_,21,0xffdfffff) #define SET_CH1_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,1,0xfffffffd) #define SET_CH3_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,3,0xfffffff7) #define SET_CH4_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,4,0xffffffef) #define SET_CH5_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,5,0xffffffdf) #define SET_CH6_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,6,0xffffffbf) #define SET_CH7_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,7,0xffffff7f) #define SET_CH8_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,8,0xfffffeff) #define SET_CH9_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,9,0xfffffdff) #define SET_CH10_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,10,0xfffffbff) #define SET_CH11_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,11,0xfffff7ff) #define SET_CH12_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,12,0xffffefff) #define SET_CH13_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,13,0xffffdfff) #define SET_CH14_HALT_STS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,14,0xffffbfff) #define SET_STOP_MBOX_OUT_SUCCESS(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,16,0xfffeffff) #define SET_MB_EXCEPT_CASE(_VAL_) SET_REG(ADR_MBOX_HALT_STS,_VAL_,24,0x00ffffff) #define SET_MB_DBG_TIME_STEP(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,0,0xffff0000) #define SET_DBG_TYPE(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,16,0xfffcffff) #define SET_MB_DBG_CLR(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,18,0xfffbffff) #define SET_DBG_ALC_LOG_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,19,0xfff7ffff) #define SET_MB_DBG_COUNTER_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,24,0xfeffffff) #define SET_MB_DBG_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG1,_VAL_,31,0x7fffffff) #define SET_MB_DBG_RECORD_CNT(_VAL_) SET_REG(ADR_MB_DBG_CFG2,_VAL_,0,0xffff0000) #define SET_MB_DBG_LENGTH(_VAL_) SET_REG(ADR_MB_DBG_CFG2,_VAL_,16,0x0000ffff) #define SET_MB_DBG_CFG_ADDR(_VAL_) SET_REG(ADR_MB_DBG_CFG3,_VAL_,0,0x00000000) #define SET_DBG_HWID0_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,0,0xfffffffe) #define SET_DBG_HWID1_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,1,0xfffffffd) #define SET_DBG_HWID2_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,2,0xfffffffb) #define SET_DBG_HWID3_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,3,0xfffffff7) #define SET_DBG_HWID4_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,4,0xffffffef) #define SET_DBG_HWID5_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,5,0xffffffdf) #define SET_DBG_HWID6_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,6,0xffffffbf) #define SET_DBG_HWID7_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,7,0xffffff7f) #define SET_DBG_HWID8_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,8,0xfffffeff) #define SET_DBG_HWID9_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,9,0xfffffdff) #define SET_DBG_HWID10_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,10,0xfffffbff) #define SET_DBG_HWID11_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,11,0xfffff7ff) #define SET_DBG_HWID12_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,12,0xffffefff) #define SET_DBG_HWID13_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,13,0xffffdfff) #define SET_DBG_HWID14_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,14,0xffffbfff) #define SET_DBG_HWID15_WR_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,15,0xffff7fff) #define SET_DBG_HWID0_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,16,0xfffeffff) #define SET_DBG_HWID1_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,17,0xfffdffff) #define SET_DBG_HWID2_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,18,0xfffbffff) #define SET_DBG_HWID3_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,19,0xfff7ffff) #define SET_DBG_HWID4_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,20,0xffefffff) #define SET_DBG_HWID5_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,21,0xffdfffff) #define SET_DBG_HWID6_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,22,0xffbfffff) #define SET_DBG_HWID7_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,23,0xff7fffff) #define SET_DBG_HWID8_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,24,0xfeffffff) #define SET_DBG_HWID9_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,25,0xfdffffff) #define SET_DBG_HWID10_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,26,0xfbffffff) #define SET_DBG_HWID11_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,27,0xf7ffffff) #define SET_DBG_HWID12_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,28,0xefffffff) #define SET_DBG_HWID13_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,29,0xdfffffff) #define SET_DBG_HWID14_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,30,0xbfffffff) #define SET_DBG_HWID15_RD_EN(_VAL_) SET_REG(ADR_MB_DBG_CFG4,_VAL_,31,0x7fffffff) #define SET_MB_OUT_QUEUE_EN(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_CFG,_VAL_,1,0xfffffffd) #define SET_OUT_QUEUE_FLUSH_ID(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_FLUSH,_VAL_,0,0xffffff80) #define SET_OUT_QUEUE_FLUSH_MODE(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_FLUSH,_VAL_,0,0xfffffffc) #define SET_OUT_QUEUE_FLUSH_SEL(_VAL_) SET_REG(ADR_MB_OUT_QUEUE_FLUSH,_VAL_,8,0xfffff0ff) #define SET_FFO0_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,0,0xffffffe0) #define SET_FFO1_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,5,0xfffffc1f) #define SET_FFO2_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,10,0xffffc3ff) #define SET_FFO3_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,15,0xfff07fff) #define SET_FFO4_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,20,0xffcfffff) #define SET_FFO5_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT1,_VAL_,25,0xf1ffffff) #define SET_FFO6_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,0,0xfffffff0) #define SET_FFO7_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,5,0xfffffc1f) #define SET_FFO8_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,10,0xffff83ff) #define SET_FFO9_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,15,0xfff07fff) #define SET_FFO10_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,20,0xff0fffff) #define SET_FFO11_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT2,_VAL_,25,0xc1ffffff) #define SET_FFO12_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,0,0xfffffff8) #define SET_FFO13_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,5,0xffffff9f) #define SET_FFO14_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,10,0xffff83ff) #define SET_FFO15_CNT(_VAL_) SET_REG(ADR_RD_FFOUT_CNT3,_VAL_,15,0xfff87fff) #define SET_CH0_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,0,0xfffffffe) #define SET_CH1_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,1,0xfffffffd) #define SET_CH2_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,2,0xfffffffb) #define SET_CH3_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,3,0xfffffff7) #define SET_CH4_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,4,0xffffffef) #define SET_CH5_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,5,0xffffffdf) #define SET_CH6_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,6,0xffffffbf) #define SET_CH7_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,7,0xffffff7f) #define SET_CH8_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,8,0xfffffeff) #define SET_CH9_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,9,0xfffffdff) #define SET_CH10_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,10,0xfffffbff) #define SET_CH11_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,11,0xfffff7ff) #define SET_CH12_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,12,0xffffefff) #define SET_CH13_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,13,0xffffdfff) #define SET_CH14_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,14,0xffffbfff) #define SET_CH15_FFO_FULL(_VAL_) SET_REG(ADR_RD_FFOUT_FULL,_VAL_,15,0xffff7fff) #define SET_CH0_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,0,0xfffffffe) #define SET_CH1_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,1,0xfffffffd) #define SET_CH2_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,2,0xfffffffb) #define SET_CH3_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,3,0xfffffff7) #define SET_CH4_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,4,0xffffffef) #define SET_CH5_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,5,0xffffffdf) #define SET_CH6_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,6,0xffffffbf) #define SET_CH7_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,7,0xffffff7f) #define SET_CH8_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,8,0xfffffeff) #define SET_CH9_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,9,0xfffffdff) #define SET_CH10_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,10,0xfffffbff) #define SET_CH11_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,11,0xfffff7ff) #define SET_CH12_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,12,0xffffefff) #define SET_CH13_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,13,0xffffdfff) #define SET_CH14_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,14,0xffffbfff) #define SET_CH15_LOWTHOLD_INT(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,15,0xffff7fff) #define SET_MB_LOW_THOLD_EN(_VAL_) SET_REG(ADR_MB_THRESHOLD6,_VAL_,31,0x7fffffff) #define SET_CH0_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,0,0xffffffe0) #define SET_CH1_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,8,0xffffe0ff) #define SET_CH2_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,16,0xffe0ffff) #define SET_CH3_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD7,_VAL_,24,0xe0ffffff) #define SET_CH4_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,0,0xffffffe0) #define SET_CH5_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,8,0xffffe0ff) #define SET_CH6_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,16,0xffe0ffff) #define SET_CH7_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD8,_VAL_,24,0xe0ffffff) #define SET_CH8_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,0,0xffffffe0) #define SET_CH9_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,8,0xffffe0ff) #define SET_CH10_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,16,0xffe0ffff) #define SET_CH11_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD9,_VAL_,24,0xe0ffffff) #define SET_CH12_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,0,0xffffffe0) #define SET_CH13_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,8,0xffffe0ff) #define SET_CH14_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,16,0xffe0ffff) #define SET_CH15_LOWTHOLD(_VAL_) SET_REG(ADR_MB_THRESHOLD10,_VAL_,24,0xe0ffffff) #define SET_TRASH_TIMEOUT_EN(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,0,0xfffffffe) #define SET_TRASH_CAN_INT(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,1,0xfffffffd) #define SET_TRASH_INT_ID(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,4,0xfffff80f) #define SET_TRASH_TIMEOUT(_VAL_) SET_REG(ADR_MB_TRASH_CFG,_VAL_,16,0xfc00ffff) #define SET_IN_FIFO_FLUSH_ID(_VAL_) SET_REG(ADR_MB_IN_FF_FLUSH,_VAL_,0,0xfffff800) #define SET_IN_FIFO_FLUSH_MODE(_VAL_) SET_REG(ADR_MB_IN_FF_FLUSH,_VAL_,0,0xfffffffc) #define SET_IN_FIFO_FLUSH_SEL(_VAL_) SET_REG(ADR_MB_IN_FF_FLUSH,_VAL_,8,0xfffff0ff) #define SET_CPU_ID_TB2(_VAL_) SET_REG(ADR_CPU_ID_TB2,_VAL_,0,0x00000000) #define SET_CPU_ID_TB3(_VAL_) SET_REG(ADR_CPU_ID_TB3,_VAL_,0,0x00000000) #define SET_IQ_LOG_EN(_VAL_) SET_REG(ADR_PHY_IQ_LOG_CFG0,_VAL_,0,0xfffffffe) #define SET_IQ_LOG_STOP_MODE(_VAL_) SET_REG(ADR_PHY_IQ_LOG_CFG1,_VAL_,0,0xfffffffe) #define SET_IQ_LOG_TIMER(_VAL_) SET_REG(ADR_PHY_IQ_LOG_CFG1,_VAL_,16,0x0000ffff) #define SET_IQ_LOG_LEN(_VAL_) SET_REG(ADR_PHY_IQ_LOG_LEN,_VAL_,0,0xffff0000) #define SET_IQ_LOG_ST_ADR(_VAL_) SET_REG(ADR_PHY_IQ_LOG_LEN,_VAL_,16,0x0000ffff) #define SET_IQ_LOG_TAIL_ADR(_VAL_) SET_REG(ADR_PHY_IQ_LOG_PTR,_VAL_,0,0xffff0000) #define SET_ALC_LENG(_VAL_) SET_REG(ADR_WR_ALC,_VAL_,0,0xfffc0000) #define SET_CH0_DYN_PRI(_VAL_) SET_REG(ADR_WR_ALC,_VAL_,20,0xffcfffff) #define SET_MCU_PKTID(_VAL_) SET_REG(ADR_GETID,_VAL_,0,0x00000000) #define SET_CH0_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,0,0xfffffffc) #define SET_CH1_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,4,0xffffffcf) #define SET_CH2_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,8,0xfffffcff) #define SET_CH3_STA_PRI(_VAL_) SET_REG(ADR_CH_STA_PRI,_VAL_,12,0xffffcfff) #define SET_ID_TB0(_VAL_) SET_REG(ADR_RD_ID0,_VAL_,0,0x00000000) #define SET_ID_TB1(_VAL_) SET_REG(ADR_RD_ID1,_VAL_,0,0x00000000) #define SET_ID_MNG_HALT(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,4,0xffffffef) #define SET_ID_MNG_ERR_HALT_EN(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,5,0xffffffdf) #define SET_ID_EXCEPT_FLG_CLR(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,6,0xffffffbf) #define SET_ID_EXCEPT_FLG(_VAL_) SET_REG(ADR_IMD_CFG,_VAL_,7,0xffffff7f) #define SET_ID_FULL(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,0,0xfffffffe) #define SET_ID_MNG_BUSY(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,1,0xfffffffd) #define SET_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,2,0xfffffffb) #define SET_CH0_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,4,0xffffffef) #define SET_CH1_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,5,0xffffffdf) #define SET_CH2_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,6,0xffffffbf) #define SET_CH3_REQ_LOCK(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,7,0xffffff7f) #define SET_REQ_LOCK_INT_EN(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,8,0xfffffeff) #define SET_REQ_LOCK_INT(_VAL_) SET_REG(ADR_IMD_STA,_VAL_,9,0xfffffdff) #define SET_MCU_ALC_READY(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,0,0xfffffffe) #define SET_ALC_FAIL(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,1,0xfffffffd) #define SET_ALC_BUSY(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,2,0xfffffffb) #define SET_CH0_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,4,0xffffffef) #define SET_CH1_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,5,0xffffffdf) #define SET_CH2_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,6,0xffffffbf) #define SET_CH3_NVLD(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,7,0xffffff7f) #define SET_ALC_INT_ID(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,8,0xffff80ff) #define SET_ALC_TIMEOUT(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,16,0xfc00ffff) #define SET_ALC_TIMEOUT_INT_EN(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,30,0xbfffffff) #define SET_ALC_TIMEOUT_INT(_VAL_) SET_REG(ADR_ALC_STA,_VAL_,31,0x7fffffff) #define SET_TX_ID_COUNT(_VAL_) SET_REG(ADR_TRX_ID_COUNT,_VAL_,0,0xffffff00) #define SET_RX_ID_COUNT(_VAL_) SET_REG(ADR_TRX_ID_COUNT,_VAL_,8,0xffff00ff) #define SET_TX_ID_THOLD(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,0,0xffffff00) #define SET_RX_ID_THOLD(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,8,0xffff00ff) #define SET_ID_THOLD_RX_INT(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,16,0xfffeffff) #define SET_RX_INT_CH(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,17,0xfff1ffff) #define SET_ID_THOLD_TX_INT(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,20,0xffefffff) #define SET_TX_INT_CH(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,21,0xff1fffff) #define SET_ID_THOLD_INT_EN(_VAL_) SET_REG(ADR_TRX_ID_THRESHOLD,_VAL_,24,0xfeffffff) #define SET_TX_ID_TB0(_VAL_) SET_REG(ADR_TX_ID0,_VAL_,0,0x00000000) #define SET_TX_ID_TB1(_VAL_) SET_REG(ADR_TX_ID1,_VAL_,0,0x00000000) #define SET_RX_ID_TB0(_VAL_) SET_REG(ADR_RX_ID0,_VAL_,0,0x00000000) #define SET_RX_ID_TB1(_VAL_) SET_REG(ADR_RX_ID1,_VAL_,0,0x00000000) #define SET_DOUBLE_RLS_INT_EN(_VAL_) SET_REG(ADR_RTN_STA,_VAL_,0,0xfffffffe) #define SET_ID_DOUBLE_RLS_INT(_VAL_) SET_REG(ADR_RTN_STA,_VAL_,1,0xfffffffd) #define SET_DOUBLE_RLS_ID(_VAL_) SET_REG(ADR_RTN_STA,_VAL_,8,0xffff80ff) #define SET_ID_LEN_THOLD_INT_EN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,0,0xfffffffe) #define SET_ALL_ID_LEN_THOLD_INT(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,1,0xfffffffd) #define SET_TX_ID_LEN_THOLD_INT(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,2,0xfffffffb) #define SET_RX_ID_LEN_THOLD_INT(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,3,0xfffffff7) #define SET_ID_TX_LEN_THOLD(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,4,0xffffe00f) #define SET_ID_RX_LEN_THOLD(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,13,0xffc01fff) #define SET_ID_LEN_THOLD(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD1,_VAL_,22,0x803fffff) #define SET_ALL_ID_ALC_LEN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD2,_VAL_,0,0xfffffe00) #define SET_TX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD2,_VAL_,9,0xfffc01ff) #define SET_RX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ID_LEN_THREADSHOLD2,_VAL_,18,0xf803ffff) #define SET_CH_ARB_EN(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,0,0xfffffffe) #define SET_CH_PRI1(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,4,0xffffffcf) #define SET_CH_PRI2(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,8,0xfffffcff) #define SET_CH_PRI3(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,12,0xffffcfff) #define SET_CH_PRI4(_VAL_) SET_REG(ADR_CH_ARB_PRI,_VAL_,16,0xfffcffff) #define SET_TX_ID_REMAIN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS,_VAL_,0,0xffffff80) #define SET_TX_PAGE_REMAIN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS,_VAL_,8,0xfffe00ff) #define SET_ID_PAGE_MAX_SIZE(_VAL_) SET_REG(ADR_ID_INFO_STA,_VAL_,0,0xfffffe00) #define SET_TX_PAGE_LIMIT(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,0,0xfffffe00) #define SET_TX_COUNT_LIMIT(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,16,0xff00ffff) #define SET_TX_LIMIT_INT(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,30,0xbfffffff) #define SET_TX_LIMIT_INT_EN(_VAL_) SET_REG(ADR_TX_LIMIT_INTR,_VAL_,31,0x7fffffff) #define SET_TX_PAGE_USE_7_0(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,0,0xffffff00) #define SET_TX_ID_USE_5_0(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,8,0xffffc0ff) #define SET_EDCA0_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,14,0xfffc3fff) #define SET_EDCA1_FFO_CNT_3_0(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,18,0xffc3ffff) #define SET_EDCA2_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,22,0xf83fffff) #define SET_EDCA3_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO,_VAL_,27,0x07ffffff) #define SET_ID_TB2(_VAL_) SET_REG(ADR_RD_ID2,_VAL_,0,0x00000000) #define SET_ID_TB3(_VAL_) SET_REG(ADR_RD_ID3,_VAL_,0,0x00000000) #define SET_TX_ID_TB2(_VAL_) SET_REG(ADR_TX_ID2,_VAL_,0,0x00000000) #define SET_TX_ID_TB3(_VAL_) SET_REG(ADR_TX_ID3,_VAL_,0,0x00000000) #define SET_RX_ID_TB2(_VAL_) SET_REG(ADR_RX_ID2,_VAL_,0,0x00000000) #define SET_RX_ID_TB3(_VAL_) SET_REG(ADR_RX_ID3,_VAL_,0,0x00000000) #define SET_TX_PAGE_USE2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,0,0xfffffe00) #define SET_TX_ID_USE2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,9,0xfffe01ff) #define SET_EDCA4_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,17,0xffe1ffff) #define SET_EDCA5_FFO_CNT(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO2,_VAL_,21,0xfc1fffff) #define SET_TX_PAGE_USE3(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,0,0xfffffe00) #define SET_TX_ID_USE3(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,9,0xfffe01ff) #define SET_EDCA1_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,17,0xffc1ffff) #define SET_EDCA4_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,23,0xf87fffff) #define SET_EDCA5_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_A,_VAL_,27,0x07ffffff) #define SET_TX_PAGE_USE4(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,0,0xfffffe00) #define SET_TX_ID_USE4(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,9,0xfffe01ff) #define SET_EDCA2_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,17,0xffc1ffff) #define SET_EDCA3_FFO_CNT2(_VAL_) SET_REG(ADR_TX_ID_ALL_INFO_B,_VAL_,22,0xf83fffff) #define SET_TX_ID_IFO_LEN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS2,_VAL_,0,0xfffffe00) #define SET_RX_ID_IFO_LEN(_VAL_) SET_REG(ADR_TX_ID_REMAIN_STATUS2,_VAL_,16,0xfe00ffff) #define SET_MAX_ALL_ALC_ID_CNT(_VAL_) SET_REG(ADR_ALC_ID_INFO,_VAL_,0,0xffffff00) #define SET_MAX_TX_ALC_ID_CNT(_VAL_) SET_REG(ADR_ALC_ID_INFO,_VAL_,8,0xffff00ff) #define SET_MAX_RX_ALC_ID_CNT(_VAL_) SET_REG(ADR_ALC_ID_INFO,_VAL_,16,0xff00ffff) #define SET_MAX_ALL_ID_ALC_LEN(_VAL_) SET_REG(ADR_ALC_ID_INF1,_VAL_,0,0xfffffe00) #define SET_MAX_TX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ALC_ID_INF1,_VAL_,9,0xfffc01ff) #define SET_MAX_RX_ID_ALC_LEN(_VAL_) SET_REG(ADR_ALC_ID_INF1,_VAL_,18,0xf803ffff) #define SET_ALC_ABT_ID(_VAL_) SET_REG(ADR_ALC_ABORT,_VAL_,0,0xffffff80) #define SET_ALC_ABT_STS(_VAL_) SET_REG(ADR_ALC_ABORT,_VAL_,8,0xfffffeff) #define SET_ALC_ABT_CLR(_VAL_) SET_REG(ADR_ALC_ABORT,_VAL_,9,0xfffffdff) #define SET_ALC_ERR_STS(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,0,0xfffffffe) #define SET_RLS_ERR_STS(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,1,0xfffffffd) #define SET_ALC_ERR_CLR(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,2,0xfffffffb) #define SET_RLS_ERR_CLR(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,3,0xfffffff7) #define SET_AL_STATE(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,8,0xfffff8ff) #define SET_RL_STATE(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,12,0xffff8fff) #define SET_ALC_ERR_ID(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,16,0xff80ffff) #define SET_RLS_ERR_ID(_VAL_) SET_REG(ADR_ALC_RLS_STATUS,_VAL_,24,0x80ffffff) #define SET_DMN_NOHIT_STS(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,0,0xfffffffe) #define SET_DMN_NOHIT_CLR(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,1,0xfffffffd) #define SET_DMN_WR(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,2,0xfffffffb) #define SET_DMN_PORT(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,4,0xffffff0f) #define SET_DMN_NHIT_ID(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,8,0xffff80ff) #define SET_DMN_NHIT_ADDR(_VAL_) SET_REG(ADR_DMN_STATUS,_VAL_,16,0xff00ffff) #define SET_AVA_TAG(_VAL_) SET_REG(ADR_TAG_STATUS,_VAL_,0,0xfffffe00) #define SET_PKTBUF_FULL(_VAL_) SET_REG(ADR_TAG_STATUS,_VAL_,16,0xfffeffff) #define SET_PKT_REQ_STATUS(_VAL_) SET_REG(ADR_REQ_STATUS,_VAL_,0,0xffff0000) #define SET_PG_TAG_31_0(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_0,_VAL_,0,0x00000000) #define SET_PG_TAG_63_32(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_1,_VAL_,0,0x00000000) #define SET_PG_TAG_95_64(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_2,_VAL_,0,0x00000000) #define SET_PG_TAG_127_96(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_3,_VAL_,0,0x00000000) #define SET_PG_TAG_159_128(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_4,_VAL_,0,0x00000000) #define SET_PG_TAG_191_160(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_5,_VAL_,0,0x00000000) #define SET_PG_TAG_223_192(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_6,_VAL_,0,0x00000000) #define SET_PG_TAG_255_224(_VAL_) SET_REG(ADR_PAGE_TAG_STATUS_7,_VAL_,0,0x00000000) #define SET_FPGA_TO_GEMINIA_DAC_SIGN_SWAP(_VAL_) SET_REG(ADR_FPGA_GEMINIARF_SWITCH,_VAL_,1,0xfffffffd) #define SET_FPGA_TO_GEMINIA_DAC_EDGE_SEL(_VAL_) SET_REG(ADR_FPGA_GEMINIARF_SWITCH,_VAL_,2,0xfffffffb) #define SET_FPGA_TO_GEMINIA_ADC_EDGE_SEL(_VAL_) SET_REG(ADR_FPGA_GEMINIARF_SWITCH,_VAL_,3,0xfffffff7) #define DEF_FBUS_SAR0() (REG32(ADR_FBUS_SAR0)) = (0x00000000) #define DEF_FBUS_DAR0() (REG32(ADR_FBUS_DAR0)) = (0x00000000) #define DEF_FBUS_CTL0_1() (REG32(ADR_FBUS_CTL0_1)) = (0x00000000) #define DEF_FBUS_CTL0_2() (REG32(ADR_FBUS_CTL0_2)) = (0x00000000) #define DEF_FBUS_CFG0_1() (REG32(ADR_FBUS_CFG0_1)) = (0x00000c00) #define DEF_FBUS_CFG0_2() (REG32(ADR_FBUS_CFG0_2)) = (0x00000000) #define DEF_FBUS_SAR1() (REG32(ADR_FBUS_SAR1)) = (0x00000000) #define DEF_FBUS_DAR1() (REG32(ADR_FBUS_DAR1)) = (0x00000000) #define DEF_FBUS_CTL1_1() (REG32(ADR_FBUS_CTL1_1)) = (0x00000000) #define DEF_FBUS_CTL1_2() (REG32(ADR_FBUS_CTL1_2)) = (0x00000000) #define DEF_FBUS_CFG1_1() (REG32(ADR_FBUS_CFG1_1)) = (0x00000c00) #define DEF_FBUS_CFG1_2() (REG32(ADR_FBUS_CFG1_2)) = (0x00000000) #define DEF_FBUS_RAWTR() (REG32(ADR_FBUS_RAWTR)) = (0x00000000) #define DEF_FBUS_RAWERR() (REG32(ADR_FBUS_RAWERR)) = (0x00000000) #define DEF_FBUS_STATUSTR() (REG32(ADR_FBUS_STATUSTR)) = (0x00000000) #define DEF_FBUS_STATUSERR() (REG32(ADR_FBUS_STATUSERR)) = (0x00000000) #define DEF_FBUS_MASKTR() (REG32(ADR_FBUS_MASKTR)) = (0x00000000) #define DEF_FBUS_MASKERR() (REG32(ADR_FBUS_MASKERR)) = (0x00000000) #define DEF_FBUS_CLRTR() (REG32(ADR_FBUS_CLRTR)) = (0x00000000) #define DEF_FBUS_CLRERR() (REG32(ADR_FBUS_CLRERR)) = (0x00000000) // #define DEF_FBUS_COMBINED_INT_STATUS() (REG32(ADR_FBUS_COMBINED_INT_STATUS)) = (0xxxxxxxxx) #define DEF_FBUS_SHS_SRC_REQ_CFG() (REG32(ADR_FBUS_SHS_SRC_REQ_CFG)) = (0x00000000) #define DEF_FBUS_SHS_DST_REQ_CFG() (REG32(ADR_FBUS_SHS_DST_REQ_CFG)) = (0x00000000) #define DEF_FBUS_SHS_SRC_SREQ_CFG() (REG32(ADR_FBUS_SHS_SRC_SREQ_CFG)) = (0x00000000) #define DEF_FBUS_SHS_DST_SREQ_CFG() (REG32(ADR_FBUS_SHS_DST_SREQ_CFG)) = (0x00000000) #define DEF_FBUS_DMA_EN() (REG32(ADR_FBUS_DMA_EN)) = (0x00000000) #define DEF_FBUS_CH_EN() (REG32(ADR_FBUS_CH_EN)) = (0x00000000) #define DEF_FBUS_DMAC_INFO() (REG32(ADR_FBUS_DMAC_INFO)) = (0x00000000) #define DEF_SBUS_SAR0() (REG32(ADR_SBUS_SAR0)) = (0x00000000) #define DEF_SBUS_DAR0() (REG32(ADR_SBUS_DAR0)) = (0x00000000) #define DEF_SBUS_CTL0_1() (REG32(ADR_SBUS_CTL0_1)) = (0x00000000) #define DEF_SBUS_CTL0_2() (REG32(ADR_SBUS_CTL0_2)) = (0x00000000) #define DEF_SBUS_CFG0_1() (REG32(ADR_SBUS_CFG0_1)) = (0x00000c00) #define DEF_SBUS_CFG0_2() (REG32(ADR_SBUS_CFG0_2)) = (0x00000000) #define DEF_SBUS_SAR1() (REG32(ADR_SBUS_SAR1)) = (0x00000000) #define DEF_SBUS_DAR1() (REG32(ADR_SBUS_DAR1)) = (0x00000000) #define DEF_SBUS_CTL1_1() (REG32(ADR_SBUS_CTL1_1)) = (0x00000000) #define DEF_SBUS_CTL1_2() (REG32(ADR_SBUS_CTL1_2)) = (0x00000000) #define DEF_SBUS_CFG1_1() (REG32(ADR_SBUS_CFG1_1)) = (0x00000c00) #define DEF_SBUS_CFG1_2() (REG32(ADR_SBUS_CFG1_2)) = (0x00000000) #define DEF_SBUS_RAWTR() (REG32(ADR_SBUS_RAWTR)) = (0x00000000) #define DEF_SBUS_RAWERR() (REG32(ADR_SBUS_RAWERR)) = (0x00000000) #define DEF_SBUS_STATUSTR() (REG32(ADR_SBUS_STATUSTR)) = (0x00000000) #define DEF_SBUS_STATUSERR() (REG32(ADR_SBUS_STATUSERR)) = (0x00000000) #define DEF_SBUS_MASKTR() (REG32(ADR_SBUS_MASKTR)) = (0x00000000) #define DEF_SBUS_MASKERR() (REG32(ADR_SBUS_MASKERR)) = (0x00000000) #define DEF_SBUS_CLRTR() (REG32(ADR_SBUS_CLRTR)) = (0x00000000) #define DEF_SBUS_CLRERR() (REG32(ADR_SBUS_CLRERR)) = (0x00000000) // #define DEF_SBUS_COMBINED_INT_STATUS() (REG32(ADR_SBUS_COMBINED_INT_STATUS)) = (0xxxxxxxxx) #define DEF_SBUS_SHS_SRC_REQ_CFG() (REG32(ADR_SBUS_SHS_SRC_REQ_CFG)) = (0x00000000) #define DEF_SBUS_SHS_DST_REQ_CFG() (REG32(ADR_SBUS_SHS_DST_REQ_CFG)) = (0x00000000) #define DEF_SBUS_SHS_SRC_SREQ_CFG() (REG32(ADR_SBUS_SHS_SRC_SREQ_CFG)) = (0x00000000) #define DEF_SBUS_SHS_DST_SREQ_CFG() (REG32(ADR_SBUS_SHS_DST_SREQ_CFG)) = (0x00000000) #define DEF_SBUS_DMA_EN() (REG32(ADR_SBUS_DMA_EN)) = (0x00000000) #define DEF_SBUS_CH_EN() (REG32(ADR_SBUS_CH_EN)) = (0x00000000) #define DEF_SBUS_DMAC_INFO() (REG32(ADR_SBUS_DMAC_INFO)) = (0x00000000) #define DEF_I2S_EN() (REG32(ADR_I2S_EN)) = (0x00000000) #define DEF_I2S_RX_EN() (REG32(ADR_I2S_RX_EN)) = (0x00000000) #define DEF_I2S_TX_EN() (REG32(ADR_I2S_TX_EN)) = (0x00000000) #define DEF_I2S_SCLK_SCR_EN() (REG32(ADR_I2S_SCLK_SCR_EN)) = (0x00000000) #define DEF_I2S_WS_DEF() (REG32(ADR_I2S_WS_DEF)) = (0x00000010) #define DEF_RESET_RX_FIFO() (REG32(ADR_RESET_RX_FIFO)) = (0x00000000) #define DEF_RESET_TX_FIFO() (REG32(ADR_RESET_TX_FIFO)) = (0x00000000) #define DEF_L_TRX_DATA() (REG32(ADR_L_TRX_DATA)) = (0x00000000) #define DEF_R_TRX_DATA() (REG32(ADR_R_TRX_DATA)) = (0x00000000) #define DEF_I2S_RX_CH_EN() (REG32(ADR_I2S_RX_CH_EN)) = (0x00000000) #define DEF_I2S_TX_CH_EN() (REG32(ADR_I2S_TX_CH_EN)) = (0x00000000) #define DEF_I2S_RX_WORD_RES() (REG32(ADR_I2S_RX_WORD_RES)) = (0x00000005) #define DEF_I2S_TX_WORD_RES() (REG32(ADR_I2S_TX_WORD_RES)) = (0x00000005) #define DEF_I2S_INTR() (REG32(ADR_I2S_INTR)) = (0x00000000) #define DEF_I2S_INTR_MASK() (REG32(ADR_I2S_INTR_MASK)) = (0x00000033) #define DEF_I2S_RXFO() (REG32(ADR_I2S_RXFO)) = (0x00000000) #define DEF_I2S_TXFO() (REG32(ADR_I2S_TXFO)) = (0x00000000) #define DEF_I2S_RX_FIFO_TH() (REG32(ADR_I2S_RX_FIFO_TH)) = (0x00000005) #define DEF_I2S_TX_FIFO_TH() (REG32(ADR_I2S_TX_FIFO_TH)) = (0x00000005) #define DEF_I2S_RX_FIFO_FLUSH() (REG32(ADR_I2S_RX_FIFO_FLUSH)) = (0x00000000) #define DEF_I2S_TX_FIFO_FLUSH() (REG32(ADR_I2S_TX_FIFO_FLUSH)) = (0x00000000) #define DEF_I2S_RX_DMA() (REG32(ADR_I2S_RX_DMA)) = (0x00000000) #define DEF_I2S_TX_DMA() (REG32(ADR_I2S_TX_DMA)) = (0x00000000) #define DEF_I2CMST_CFG0() (REG32(ADR_I2CMST_CFG0)) = (0x00000000) #define DEF_I2CMST_TAR() (REG32(ADR_I2CMST_TAR)) = (0x00000000) #define DEF_I2CMST_TRX_CMD_DATA() (REG32(ADR_I2CMST_TRX_CMD_DATA)) = (0x00000000) #define DEF_I2CMST_SCLK_H_WIDTH() (REG32(ADR_I2CMST_SCLK_H_WIDTH)) = (0x00000000) #define DEF_I2CMST_SCLK_L_WIDTH() (REG32(ADR_I2CMST_SCLK_L_WIDTH)) = (0x00000000) #define DEF_I2CMST_INT() (REG32(ADR_I2CMST_INT)) = (0x00000000) #define DEF_I2CMST_INT_MASK() (REG32(ADR_I2CMST_INT_MASK)) = (0x00000000) #define DEF_I2CMST_INT_STA() (REG32(ADR_I2CMST_INT_STA)) = (0x00000000) #define DEF_I2CMST_RX_FIFO_TH() (REG32(ADR_I2CMST_RX_FIFO_TH)) = (0x00000000) #define DEF_I2CMST_TX_FIFO_TH() (REG32(ADR_I2CMST_TX_FIFO_TH)) = (0x00000000) #define DEF_I2CMST_ENABLE() (REG32(ADR_I2CMST_ENABLE)) = (0x00000000) #define DEF_SPIMST_CFG0() (REG32(ADR_SPIMST_CFG0)) = (0x00000007) #define DEF_SPIMST_CFG1() (REG32(ADR_SPIMST_CFG1)) = (0x00000000) #define DEF_SPIMST_EN() (REG32(ADR_SPIMST_EN)) = (0x00000000) #define DEF_SPIMST_CEN() (REG32(ADR_SPIMST_CEN)) = (0x00000000) #define DEF_SPIMST_SCLK_RATE() (REG32(ADR_SPIMST_SCLK_RATE)) = (0x00000000) #define DEF_SPIMST_TXFIFO_TH() (REG32(ADR_SPIMST_TXFIFO_TH)) = (0x00000000) #define DEF_SPIMST_RXFIFO_TH() (REG32(ADR_SPIMST_RXFIFO_TH)) = (0x00000000) #define DEF_SPIMST_STATUS() (REG32(ADR_SPIMST_STATUS)) = (0x00000000) #define DEF_SPIMST_INT_MASK() (REG32(ADR_SPIMST_INT_MASK)) = (0x00000000) #define DEF_SPIMST_INT() (REG32(ADR_SPIMST_INT)) = (0x00000000) #define DEF_SPIMST_TRX_DATA() (REG32(ADR_SPIMST_TRX_DATA)) = (0x00000000) #define DEF_SPIMST_RX_SAMPLE_DLY() (REG32(ADR_SPIMST_RX_SAMPLE_DLY)) = (0x00000000) #define DEF_APPLICATION_CONTROL_REG() (REG32(ADR_APPLICATION_CONTROL_REG)) = (0x00000000) #define DEF_MEMORY_DESTINATION_ADDRESS_REG() (REG32(ADR_MEMORY_DESTINATION_ADDRESS_REG)) = (0x00000000) #define DEF_USB_AND_DEVICE_CONTROL_REG() (REG32(ADR_USB_AND_DEVICE_CONTROL_REG)) = (0x00000000) #define DEF_HANDSHAKE_AND_HALT_BIT_REG() (REG32(ADR_HANDSHAKE_AND_HALT_BIT_REG)) = (0x00000000) #define DEF_SETUP_TRANSACTION_REG_0() (REG32(ADR_SETUP_TRANSACTION_REG_0)) = (0x00000000) #define DEF_SETUP_TRANSACTION_REG_1() (REG32(ADR_SETUP_TRANSACTION_REG_1)) = (0x00000000) #define DEF_TXBUFFER_CONTROL_REG_0() (REG32(ADR_TXBUFFER_CONTROL_REG_0)) = (0x00000000) #define DEF_TXBUFFER_CONTROL_REG_1() (REG32(ADR_TXBUFFER_CONTROL_REG_1)) = (0x00000000) #define DEF_TXBUFFER_CONTROL_REG_2() (REG32(ADR_TXBUFFER_CONTROL_REG_2)) = (0x00000000) #define DEF_TXBUFFER_CONTROL_REG_3() (REG32(ADR_TXBUFFER_CONTROL_REG_3)) = (0x00000000) #define DEF_INTERRUPT_ENABLE_REG() (REG32(ADR_INTERRUPT_ENABLE_REG)) = (0x3f0f0007) #define DEF_INTERRUPT_DISABLE_REG() (REG32(ADR_INTERRUPT_DISABLE_REG)) = (0x00000000) #define DEF_INTERRUPT_STATUS_REG() (REG32(ADR_INTERRUPT_STATUS_REG)) = (0x00000000) #define DEF_PHYSICAL_INTERFACE_REG_0() (REG32(ADR_PHYSICAL_INTERFACE_REG_0)) = (0x00000000) #define DEF_ENDPOINT_DESCRIPTOR_REG_0() (REG32(ADR_ENDPOINT_DESCRIPTOR_REG_0)) = (0x00000000) #define DEF_ENDPOINT_DESCRIPTOR_REG_1() (REG32(ADR_ENDPOINT_DESCRIPTOR_REG_1)) = (0x00000000) #define DEF_ENDPOINT_DESCRIPTOR_REG_2() (REG32(ADR_ENDPOINT_DESCRIPTOR_REG_2)) = (0x00000000) #define DEF_ENDPOINT_DESCRIPTOR_REG_3() (REG32(ADR_ENDPOINT_DESCRIPTOR_REG_3)) = (0x00000000) #define DEF_ENDPOINT_DESCRIPTOR_REG_4() (REG32(ADR_ENDPOINT_DESCRIPTOR_REG_4)) = (0x00000000) #define DEF_USB_PHY_CORECLKIN_POWER_SAVING_REG_0() (REG32(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_0)) = (0x00000000) #define DEF_USB_PHY_CORECLKIN_POWER_SAVING_REG_1() (REG32(ADR_USB_PHY_CORECLKIN_POWER_SAVING_REG_1)) = (0x00000001) #define DEF_USB_EP4_AGGREGATION_REG() (REG32(ADR_USB_EP4_AGGREGATION_REG)) = (0x01000000) #define DEF_USB_ACC_CTRL_REG_0() (REG32(ADR_USB_ACC_CTRL_REG_0)) = (0x0000020f) #define DEF_USB_ACC_EP2_DATA_REG_0() (REG32(ADR_USB_ACC_EP2_DATA_REG_0)) = (0x00000000) #define DEF_USB_ACC_EP2_DATA_REG_1() (REG32(ADR_USB_ACC_EP2_DATA_REG_1)) = (0x00000000) #define DEF_USB_ACC_CTRL_REG_1() (REG32(ADR_USB_ACC_CTRL_REG_1)) = (0x00000000) #define DEF_USB_ACC_STATUS_REG() (REG32(ADR_USB_ACC_STATUS_REG)) = (0x00000000) #define DEF_EP1_DATA_REG_0() (REG32(ADR_EP1_DATA_REG_0)) = (0x00000000) #define DEF_EP1_DATA_REG_1() (REG32(ADR_EP1_DATA_REG_1)) = (0x00000000) #define DEF_EP1_DATA_REG_2() (REG32(ADR_EP1_DATA_REG_2)) = (0x00000000) #define DEF_USB_CONTROLLER_LOW_POWER_STATUS_REG() (REG32(ADR_USB_CONTROLLER_LOW_POWER_STATUS_REG)) = (0x00000002) #define DEF_USB_CONTROLLER_CTRL_STATUS_REG_0() (REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_0)) = (0x00000001) #define DEF_USB_CONTROLLER_CTRL_STATUS_REG_1() (REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_1)) = (0x00000003) #define DEF_USB_CONTROLLER_CTRL_STATUS_REG_2() (REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_2)) = (0x00000824) #define DEF_USB_CONTROLLER_CTRL_STATUS_REG_3() (REG32(ADR_USB_CONTROLLER_CTRL_STATUS_REG_3)) = (0x00000000) #define DEF_USB_PHY_CTRL_STATUS_REG_0() (REG32(ADR_USB_PHY_CTRL_STATUS_REG_0)) = (0x00001009) #define DEF_USB_PHY_CTRL_STATUS_REG_1() (REG32(ADR_USB_PHY_CTRL_STATUS_REG_1)) = (0x00000200) #define DEF_USB_PHY_CTRL_STATUS_REG_2() (REG32(ADR_USB_PHY_CTRL_STATUS_REG_2)) = (0x20000000) #define DEF_USB_PHY_CTRL_STATUS_REG_3() (REG32(ADR_USB_PHY_CTRL_STATUS_REG_3)) = (0x0000000c) #define DEF_OTG_LINK_WRITE_REG() (REG32(ADR_OTG_LINK_WRITE_REG)) = (0x00000000) #define DEF_BRG_SW_RST() (REG32(ADR_BRG_SW_RST)) = (0x00000000) #define DEF_BOOT() (REG32(ADR_BOOT)) = (0x00040000) #define DEF_CHIP_ID_0() (REG32(ADR_CHIP_ID_0)) = (0x20202020) #define DEF_CHIP_ID_1() (REG32(ADR_CHIP_ID_1)) = (0x30202020) #define DEF_CHIP_ID_2() (REG32(ADR_CHIP_ID_2)) = (0x30303642) #define DEF_CHIP_ID_3() (REG32(ADR_CHIP_ID_3)) = (0x53535636) #define DEF_CLOCK_SELECTION() (REG32(ADR_CLOCK_SELECTION)) = (0x00000001) #define DEF_PLATFORM_CLOCK_ENABLE() (REG32(ADR_PLATFORM_CLOCK_ENABLE)) = (0x7effffff) #define DEF_SYS_CSR_CLOCK_ENABLE() (REG32(ADR_SYS_CSR_CLOCK_ENABLE)) = (0x00000407) #define DEF_BOOTSTRAP_SAMPLE() (REG32(ADR_BOOTSTRAP_SAMPLE)) = (0x00000000) #define DEF_N10_DBG1() (REG32(ADR_N10_DBG1)) = (0x00000000) #define DEF_N10_DBG2() (REG32(ADR_N10_DBG2)) = (0x00000000) #define DEF_ROPMUSTATE() (REG32(ADR_ROPMUSTATE)) = (0x00000000) #define DEF_ROM_READ_PROT() (REG32(ADR_ROM_READ_PROT)) = (0x00000001) #define DEF_GPIO_IQ_LOG_STOP() (REG32(ADR_GPIO_IQ_LOG_STOP)) = (0x00000000) #define DEF_TB_ADR_SEL() (REG32(ADR_TB_ADR_SEL)) = (0x00000000) #define DEF_TB_RDATA() (REG32(ADR_TB_RDATA)) = (0x00000000) #define DEF_UART_W2B() (REG32(ADR_UART_W2B)) = (0x00000000) #define DEF_SYSCTRL_COMMAND() (REG32(ADR_SYSCTRL_COMMAND)) = (0x00000000) #define DEF_FBUS_CLK_SEL() (REG32(ADR_FBUS_CLK_SEL)) = (0x00000001) #define DEF_SYSCTRL_STATUS() (REG32(ADR_SYSCTRL_STATUS)) = (0x00000000) #define DEF_I2SMAS_CFG() (REG32(ADR_I2SMAS_CFG)) = (0x80000000) #define DEF_HBUSREQ_LOCK() (REG32(ADR_HBUSREQ_LOCK)) = (0x00001ffd) #define DEF_HBURST_LOCK() (REG32(ADR_HBURST_LOCK)) = (0x00000000) #define DEF_FENCE_CTRL() (REG32(ADR_FENCE_CTRL)) = (0x00000000) #define DEF_FENCE_STATUS() (REG32(ADR_FENCE_STATUS)) = (0x00000000) #define DEF_POWER_SW_INFO() (REG32(ADR_POWER_SW_INFO)) = (0x00000000) #define DEF_VIAROM_EMA() (REG32(ADR_VIAROM_EMA)) = (0x00000002) #define DEF_TEST_MODE() (REG32(ADR_TEST_MODE)) = (0x00000000) #define DEF_MANUAL_RESET_N() (REG32(ADR_MANUAL_RESET_N)) = (0x00000002) #define DEF_DEBUG_FIRMWARE_EVENT_FLAG() (REG32(ADR_DEBUG_FIRMWARE_EVENT_FLAG)) = (0x00000000) #define DEF_DEBUG_HOST_EVENT_FLAG() (REG32(ADR_DEBUG_HOST_EVENT_FLAG)) = (0x00000000) #define DEF_CHIP_INFO_ID_0() (REG32(ADR_CHIP_INFO_ID_0)) = (0x534d4f5f) #define DEF_CHIP_INFO_ID_1() (REG32(ADR_CHIP_INFO_ID_1)) = (0x54555249) #define DEF_CHIP_TYPE_VER() (REG32(ADR_CHIP_TYPE_VER)) = (0x00303030) #define DEF_CHIP_DATE_YYYYMMDD() (REG32(ADR_CHIP_DATE_YYYYMMDD)) = (0x00000000) #define DEF_CHIP_DATE_00HHMMSS() (REG32(ADR_CHIP_DATE_00HHMMSS)) = (0x00000000) #define DEF_CHIP_GITSHA_0() (REG32(ADR_CHIP_GITSHA_0)) = (0x00000000) #define DEF_CHIP_GITSHA_1() (REG32(ADR_CHIP_GITSHA_1)) = (0x00000000) #define DEF_CHIP_GITSHA_2() (REG32(ADR_CHIP_GITSHA_2)) = (0x00000000) #define DEF_CHIP_GITSHA_3() (REG32(ADR_CHIP_GITSHA_3)) = (0x00000000) #define DEF_CHIP_GITSHA_4() (REG32(ADR_CHIP_GITSHA_4)) = (0x00000000) #define DEF_N10CFG_DEF_IVB() (REG32(ADR_N10CFG_DEF_IVB)) = (0x00000000) #define DEF_N10CFG_SETTING() (REG32(ADR_N10CFG_SETTING)) = (0x00000000) #define DEF_USB20_HOST_SEL() (REG32(ADR_USB20_HOST_SEL)) = (0x00000000) #define DEF_CHIP_INFO_FPGATAG() (REG32(ADR_CHIP_INFO_FPGATAG)) = (0x00000000) #define DEF_PMU_MODE_TRAN_INT() (REG32(ADR_PMU_MODE_TRAN_INT)) = (0x00000000) #define DEF_DEBUG_SIM_FINISH() (REG32(ADR_DEBUG_SIM_FINISH)) = (0x00000000) #define DEF_ALWAYS_ON_CFG00() (REG32(ADR_ALWAYS_ON_CFG00)) = (0x00000000) #define DEF_SDIO_RESET_WAKE_CFG() (REG32(ADR_SDIO_RESET_WAKE_CFG)) = (0x00000002) #define DEF_BOOT_INFO() (REG32(ADR_BOOT_INFO)) = (0x00000000) #define DEF_SPARE_UART_INFO() (REG32(ADR_SPARE_UART_INFO)) = (0x00000000) #define DEF_POWER_ON_OFF_CTRL() (REG32(ADR_POWER_ON_OFF_CTRL)) = (0x00007007) #define DEF_HOST_WAKE_WIFI_CTRL() (REG32(ADR_HOST_WAKE_WIFI_CTRL)) = (0x00000000) #define DEF_PRESCALER_USTIMER() (REG32(ADR_PRESCALER_USTIMER)) = (0x00000028) #define DEF_DESIGN_FOR_TEST_ASSERTION() (REG32(ADR_DESIGN_FOR_TEST_ASSERTION)) = (0x00000000) #define DEF_WAKE_PMU_ENABLE() (REG32(ADR_WAKE_PMU_ENABLE)) = (0x00000000) #define DEF_SRAMCFG_SETTING() (REG32(ADR_SRAMCFG_SETTING)) = (0x00000000) #define DEF_ROM_PATCH00_0() (REG32(ADR_ROM_PATCH00_0)) = (0x00000000) #define DEF_ROM_PATCH00_1() (REG32(ADR_ROM_PATCH00_1)) = (0x00000000) #define DEF_ROM_PATCH01_0() (REG32(ADR_ROM_PATCH01_0)) = (0x00000000) #define DEF_ROM_PATCH01_1() (REG32(ADR_ROM_PATCH01_1)) = (0x00000000) #define DEF_DESIGN_FOR_TEST() (REG32(ADR_DESIGN_FOR_TEST)) = (0x00000000) #define DEF_TU0_MICROSECOND_TIMER() (REG32(ADR_TU0_MICROSECOND_TIMER)) = (0x00000000) #define DEF_TU0_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU0_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) #define DEF_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU0_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028) #define DEF_TU1_MICROSECOND_TIMER() (REG32(ADR_TU1_MICROSECOND_TIMER)) = (0x00000000) #define DEF_TU1_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU1_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) #define DEF_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU1_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028) #define DEF_TU2_MICROSECOND_TIMER() (REG32(ADR_TU2_MICROSECOND_TIMER)) = (0x00000000) #define DEF_TU2_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU2_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) #define DEF_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU2_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028) #define DEF_TU3_MICROSECOND_TIMER() (REG32(ADR_TU3_MICROSECOND_TIMER)) = (0x00000000) #define DEF_TU3_CURRENT_MICROSECOND_TIME_VALUE() (REG32(ADR_TU3_CURRENT_MICROSECOND_TIME_VALUE)) = (0x00000000) #define DEF_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE() (REG32(ADR_TU3_MICROSECOND_TIMER_LOCAL_PRESCALE)) = (0x00000028) #define DEF_TM0_MILLISECOND_TIMER() (REG32(ADR_TM0_MILLISECOND_TIMER)) = (0x00000000) #define DEF_TM0_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM0_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000) #define DEF_TM0_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM0_MILLISECOND_TIMER_PRESCALE)) = (0x00000028) #define DEF_TM1_MILLISECOND_TIMER() (REG32(ADR_TM1_MILLISECOND_TIMER)) = (0x00000000) #define DEF_TM1_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM1_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000) #define DEF_TM1_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM1_MILLISECOND_TIMER_PRESCALE)) = (0x00000028) #define DEF_TM2_MILLISECOND_TIMER() (REG32(ADR_TM2_MILLISECOND_TIMER)) = (0x00000000) #define DEF_TM2_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM2_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000) #define DEF_TM2_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM2_MILLISECOND_TIMER_PRESCALE)) = (0x00000028) #define DEF_TM3_MILLISECOND_TIMER() (REG32(ADR_TM3_MILLISECOND_TIMER)) = (0x00000000) #define DEF_TM3_CURRENT_MILLISECOND_TIME_VALUE() (REG32(ADR_TM3_CURRENT_MILLISECOND_TIME_VALUE)) = (0x00000000) #define DEF_TM3_MILLISECOND_TIMER_PRESCALE() (REG32(ADR_TM3_MILLISECOND_TIMER_PRESCALE)) = (0x00000028) #define DEF_MCU_WDOG_REG() (REG32(ADR_MCU_WDOG_REG)) = (0x00010000) #define DEF_SYS_WDOG_REG() (REG32(ADR_SYS_WDOG_REG)) = (0x00010000) #define DEF_PWM_0_CTRL() (REG32(ADR_PWM_0_CTRL)) = (0x40000000) #define DEF_PWM_0_SET() (REG32(ADR_PWM_0_SET)) = (0x00000000) #define DEF_PWM_1_CTRL() (REG32(ADR_PWM_1_CTRL)) = (0x40000000) #define DEF_PWM_1_SET() (REG32(ADR_PWM_1_SET)) = (0x00000000) #define DEF_PWM_2_CTRL() (REG32(ADR_PWM_2_CTRL)) = (0x40000000) #define DEF_PWM_2_SET() (REG32(ADR_PWM_2_SET)) = (0x00000000) #define DEF_PWM_3_CTRL() (REG32(ADR_PWM_3_CTRL)) = (0x40000000) #define DEF_PWM_3_SET() (REG32(ADR_PWM_3_SET)) = (0x00000000) #define DEF_PWM_4_CTRL() (REG32(ADR_PWM_4_CTRL)) = (0x40000000) #define DEF_PWM_4_SET() (REG32(ADR_PWM_4_SET)) = (0x00000000) #define DEF_MANUAL_IO() (REG32(ADR_MANUAL_IO)) = (0x00000000) #define DEF_MANUAL_PU() (REG32(ADR_MANUAL_PU)) = (0x00000000) #define DEF_MANUAL_PD() (REG32(ADR_MANUAL_PD)) = (0x00000000) #define DEF_MANUAL_DS() (REG32(ADR_MANUAL_DS)) = (0x00000000) #define DEF_IO_PO() (REG32(ADR_IO_PO)) = (0x00000000) #define DEF_IO_PI() (REG32(ADR_IO_PI)) = (0x00000000) #define DEF_IO_PIE() (REG32(ADR_IO_PIE)) = (0x007fffff) #define DEF_IO_POEN() (REG32(ADR_IO_POEN)) = (0x007fffff) #define DEF_IO_PUE() (REG32(ADR_IO_PUE)) = (0x00000000) #define DEF_IO_PDE() (REG32(ADR_IO_PDE)) = (0x00000000) #define DEF_IO_DS() (REG32(ADR_IO_DS)) = (0x007fffff) #define DEF_IO_FUNC_SEL() (REG32(ADR_IO_FUNC_SEL)) = (0x00000000) #define DEF_INT_THRU_GPIO() (REG32(ADR_INT_THRU_GPIO)) = (0x00000000) #define DEF_BIST_CTRL() (REG32(ADR_BIST_CTRL)) = (0x00000050) #define DEF_BIST_CTRL1() (REG32(ADR_BIST_CTRL1)) = (0x00000000) #define DEF_BIST_CTRL2() (REG32(ADR_BIST_CTRL2)) = (0x00000000) #define DEF_I2CS_ID_ADDR() (REG32(ADR_I2CS_ID_ADDR)) = (0x000000a0) #define DEF_I2CS_STATUS() (REG32(ADR_I2CS_STATUS)) = (0x00000400) #define DEF_I2CS_TIME_CNT() (REG32(ADR_I2CS_TIME_CNT)) = (0x0000ffff) #define DEF_I2CS_STATE() (REG32(ADR_I2CS_STATE)) = (0x00000000) #define DEF_I2CS_CTRL() (REG32(ADR_I2CS_CTRL)) = (0x00000000) #define DEF_IO_PORT_REG() (REG32(ADR_IO_PORT_REG)) = (0x00010000) #define DEF_INT_MASK_REG() (REG32(ADR_INT_MASK_REG)) = (0x000000ff) #define DEF_INT_STATUS_REG() (REG32(ADR_INT_STATUS_REG)) = (0x00000000) #define DEF_FN1_STATUS_REG() (REG32(ADR_FN1_STATUS_REG)) = (0x00000000) #define DEF_CARD_RCA_REG() (REG32(ADR_CARD_RCA_REG)) = (0x00000000) #define DEF_SDIO_BYTE_MODE_BATCH_SIZE_REG() (REG32(ADR_SDIO_BYTE_MODE_BATCH_SIZE_REG)) = (0x00000000) #define DEF_SDIO_CARD_STATUS_REG() (REG32(ADR_SDIO_CARD_STATUS_REG)) = (0x00000000) #define DEF_R5_RESP_FLAG_OUT_TIMING() (REG32(ADR_R5_RESP_FLAG_OUT_TIMING)) = (0x00040000) #define DEF_SDIO_DELAY_CHAIN_0() (REG32(ADR_SDIO_DELAY_CHAIN_0)) = (0x00000000) #define DEF_SDIO_DELAY_CHAIN_1() (REG32(ADR_SDIO_DELAY_CHAIN_1)) = (0x00000000) #define DEF_FN1_DMA_START_ADDR_REG() (REG32(ADR_FN1_DMA_START_ADDR_REG)) = (0x00000000) #define DEF_FN1_INT_CTRL_RESET() (REG32(ADR_FN1_INT_CTRL_RESET)) = (0x00000000) #define DEF_MCU_NOTIFY_HOST_EVENT() (REG32(ADR_MCU_NOTIFY_HOST_EVENT)) = (0x00000000) #define DEF_FN1_DMA_RD_START_ADDR_REG() (REG32(ADR_FN1_DMA_RD_START_ADDR_REG)) = (0x00000000) #define DEF_CCCR_00H_REG() (REG32(ADR_CCCR_00H_REG)) = (0x00000000) #define DEF_CCCR_04H_REG() (REG32(ADR_CCCR_04H_REG)) = (0x00000000) #define DEF_CCCR_08H_REG() (REG32(ADR_CCCR_08H_REG)) = (0x00000000) #define DEF_CCCR_14H_REG() (REG32(ADR_CCCR_14H_REG)) = (0x00000000) #define DEF_CCCR_13H_REG() (REG32(ADR_CCCR_13H_REG)) = (0x01000000) #define DEF_FBR_100H_REG() (REG32(ADR_FBR_100H_REG)) = (0x00000000) #define DEF_FBR_109H_REG() (REG32(ADR_FBR_109H_REG)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_0() (REG32(ADR_F0_CIS_CONTENT_REG_0)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_1() (REG32(ADR_F0_CIS_CONTENT_REG_1)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_2() (REG32(ADR_F0_CIS_CONTENT_REG_2)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_3() (REG32(ADR_F0_CIS_CONTENT_REG_3)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_4() (REG32(ADR_F0_CIS_CONTENT_REG_4)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_5() (REG32(ADR_F0_CIS_CONTENT_REG_5)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_6() (REG32(ADR_F0_CIS_CONTENT_REG_6)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_7() (REG32(ADR_F0_CIS_CONTENT_REG_7)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_8() (REG32(ADR_F0_CIS_CONTENT_REG_8)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_9() (REG32(ADR_F0_CIS_CONTENT_REG_9)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_10() (REG32(ADR_F0_CIS_CONTENT_REG_10)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_11() (REG32(ADR_F0_CIS_CONTENT_REG_11)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_12() (REG32(ADR_F0_CIS_CONTENT_REG_12)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_13() (REG32(ADR_F0_CIS_CONTENT_REG_13)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_14() (REG32(ADR_F0_CIS_CONTENT_REG_14)) = (0x00000000) #define DEF_F0_CIS_CONTENT_REG_15() (REG32(ADR_F0_CIS_CONTENT_REG_15)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_0() (REG32(ADR_F1_CIS_CONTENT_REG_0)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_1() (REG32(ADR_F1_CIS_CONTENT_REG_1)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_2() (REG32(ADR_F1_CIS_CONTENT_REG_2)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_3() (REG32(ADR_F1_CIS_CONTENT_REG_3)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_4() (REG32(ADR_F1_CIS_CONTENT_REG_4)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_5() (REG32(ADR_F1_CIS_CONTENT_REG_5)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_6() (REG32(ADR_F1_CIS_CONTENT_REG_6)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_7() (REG32(ADR_F1_CIS_CONTENT_REG_7)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_8() (REG32(ADR_F1_CIS_CONTENT_REG_8)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_9() (REG32(ADR_F1_CIS_CONTENT_REG_9)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_10() (REG32(ADR_F1_CIS_CONTENT_REG_10)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_11() (REG32(ADR_F1_CIS_CONTENT_REG_11)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_12() (REG32(ADR_F1_CIS_CONTENT_REG_12)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_13() (REG32(ADR_F1_CIS_CONTENT_REG_13)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_14() (REG32(ADR_F1_CIS_CONTENT_REG_14)) = (0x00000000) #define DEF_F1_CIS_CONTENT_REG_15() (REG32(ADR_F1_CIS_CONTENT_REG_15)) = (0x00000000) #define DEF_SPI_MODE() (REG32(ADR_SPI_MODE)) = (0x00000000) #define DEF_TX_SEG() (REG32(ADR_TX_SEG)) = (0x00000000) #define DEF_SPI_TO_PHY_PARAM1() (REG32(ADR_SPI_TO_PHY_PARAM1)) = (0x000e0006) #define DEF_SPI_TO_PHY_PARAM2() (REG32(ADR_SPI_TO_PHY_PARAM2)) = (0x000e000e) #define DEF_TWIM_EN() (REG32(ADR_TWIM_EN)) = (0x00000000) #define DEF_TWIM_STATUS_SETTING() (REG32(ADR_TWIM_STATUS_SETTING)) = (0x00030002) #define DEF_TWIM_INTERRUPT_EN() (REG32(ADR_TWIM_INTERRUPT_EN)) = (0x00000000) #define DEF_TWIM_INTERRUPT() (REG32(ADR_TWIM_INTERRUPT)) = (0x00000000) #define DEF_TWIM_INTERRUPT_STATUS() (REG32(ADR_TWIM_INTERRUPT_STATUS)) = (0x00000000) #define DEF_TWIM_STATUS_RECORD_0() (REG32(ADR_TWIM_STATUS_RECORD_0)) = (0x00000000) #define DEF_TWIM_STATUS_RECORD_1() (REG32(ADR_TWIM_STATUS_RECORD_1)) = (0x00000000) #define DEF_TWIM_DEV_A() (REG32(ADR_TWIM_DEV_A)) = (0x00000001) #define DEF_TWIM_TXD_DATA() (REG32(ADR_TWIM_TXD_DATA)) = (0x00000000) #define DEF_TWIM_RXD_DATA() (REG32(ADR_TWIM_RXD_DATA)) = (0x00000000) #define DEF_TWIM_PSCL() (REG32(ADR_TWIM_PSCL)) = (0x0014003f) #define DEF_TWIM_TRANS_PSDA() (REG32(ADR_TWIM_TRANS_PSDA)) = (0x00000005) #define DEF_TWIM_DELAY_ACK() (REG32(ADR_TWIM_DELAY_ACK)) = (0x00000000) #define DEF_I2CM_EN() (REG32(ADR_I2CM_EN)) = (0x000003f4) #define DEF_I2CM_DEV_A() (REG32(ADR_I2CM_DEV_A)) = (0x00008000) #define DEF_I2CM_LEN() (REG32(ADR_I2CM_LEN)) = (0x00000000) #define DEF_I2CM_WDAT() (REG32(ADR_I2CM_WDAT)) = (0x00000000) #define DEF_I2CM_RDAT() (REG32(ADR_I2CM_RDAT)) = (0x00000000) #define DEF_I2CM_EN_2() (REG32(ADR_I2CM_EN_2)) = (0x00010000) #define DEF_I2CM_START_STOP_PERIOD() (REG32(ADR_I2CM_START_STOP_PERIOD)) = (0x00000014) #define DEF_UART_DATA() (REG32(ADR_UART_DATA)) = (0x00000000) #define DEF_UART_IER() (REG32(ADR_UART_IER)) = (0x00000000) #define DEF_UART_FCR() (REG32(ADR_UART_FCR)) = (0x00000001) #define DEF_UART_LCR() (REG32(ADR_UART_LCR)) = (0x00000003) #define DEF_UART_MCR() (REG32(ADR_UART_MCR)) = (0x00000000) #define DEF_UART_LSR() (REG32(ADR_UART_LSR)) = (0x00000000) #define DEF_UART_MSR() (REG32(ADR_UART_MSR)) = (0x00000000) #define DEF_UART_SPR() (REG32(ADR_UART_SPR)) = (0x0000015b) #define DEF_UART_RTHR() (REG32(ADR_UART_RTHR)) = (0x000000c8) #define DEF_UART_ISR() (REG32(ADR_UART_ISR)) = (0x000000c1) #define DEF_UART_TTHR() (REG32(ADR_UART_TTHR)) = (0x000000c2) #define DEF_UART_INT_MAP() (REG32(ADR_UART_INT_MAP)) = (0x00000000) #define DEF_UART_POINTER() (REG32(ADR_UART_POINTER)) = (0x00000000) #define DEF_HSUART_TRX_CHAR() (REG32(ADR_HSUART_TRX_CHAR)) = (0x00000000) #define DEF_HSUART_INTRRUPT_ENABLE() (REG32(ADR_HSUART_INTRRUPT_ENABLE)) = (0x00000000) #define DEF_HSUART_FIFO_CTRL() (REG32(ADR_HSUART_FIFO_CTRL)) = (0x00000000) #define DEF_HSUART_LINE_CTRL() (REG32(ADR_HSUART_LINE_CTRL)) = (0x00000000) #define DEF_HSUART_MODEM_CTRL() (REG32(ADR_HSUART_MODEM_CTRL)) = (0x00000000) #define DEF_HSUART_LINE_STATUS() (REG32(ADR_HSUART_LINE_STATUS)) = (0x00000000) #define DEF_HSUART_MODEM_STATUS() (REG32(ADR_HSUART_MODEM_STATUS)) = (0x00000000) #define DEF_HSUART_SCRATCH_BOARD() (REG32(ADR_HSUART_SCRATCH_BOARD)) = (0x00000000) #define DEF_HSUART_FIFO_THRESHOLD() (REG32(ADR_HSUART_FIFO_THRESHOLD)) = (0x18041810) #define DEF_HSUART_INTERRUPT_STATUS() (REG32(ADR_HSUART_INTERRUPT_STATUS)) = (0x00000000) #define DEF_HSUART_DIV_FRAC() (REG32(ADR_HSUART_DIV_FRAC)) = (0x0067002b) #define DEF_HSUART_EXPANSION_INTERRUPT_STATUS() (REG32(ADR_HSUART_EXPANSION_INTERRUPT_STATUS)) = (0x00000000) #define DEF_HSUART_DMA_RX_STR_ADDR() (REG32(ADR_HSUART_DMA_RX_STR_ADDR)) = (0x00000000) #define DEF_HSUART_DMA_RX_END_ADDR() (REG32(ADR_HSUART_DMA_RX_END_ADDR)) = (0x00000000) #define DEF_HSUART_DMA_RX_WPT() (REG32(ADR_HSUART_DMA_RX_WPT)) = (0x00000000) #define DEF_HSUART_DMA_RX_RPT() (REG32(ADR_HSUART_DMA_RX_RPT)) = (0x00000000) #define DEF_HSUART_DMA_TX_STR_ADDR() (REG32(ADR_HSUART_DMA_TX_STR_ADDR)) = (0x00000000) #define DEF_HSUART_DMA_TX_END_ADDR() (REG32(ADR_HSUART_DMA_TX_END_ADDR)) = (0x00000000) #define DEF_HSUART_DMA_TX_WPT() (REG32(ADR_HSUART_DMA_TX_WPT)) = (0x00000000) #define DEF_HSUART_DMA_TX_RPT() (REG32(ADR_HSUART_DMA_TX_RPT)) = (0x00000000) #define DEF_MANUAL_MODE_TX_ADDR() (REG32(ADR_MANUAL_MODE_TX_ADDR)) = (0x00000000) #define DEF_MANUAL_MODE_RX_ADDR() (REG32(ADR_MANUAL_MODE_RX_ADDR)) = (0x00000000) #define DEF_SPI_PARAM() (REG32(ADR_SPI_PARAM)) = (0x00000444) #define DEF_SPI_PARAM2() (REG32(ADR_SPI_PARAM2)) = (0x00000000) #define DEF_SPI_TX_LEN() (REG32(ADR_SPI_TX_LEN)) = (0x00000000) #define DEF_SPI_RX_LEN() (REG32(ADR_SPI_RX_LEN)) = (0x00000000) #define DEF_CMD_SET() (REG32(ADR_CMD_SET)) = (0xebbb0b02) #define DEF_CMD_SET_1() (REG32(ADR_CMD_SET_1)) = (0x00000032) #define DEF_FLASH_IO0_DLY() (REG32(ADR_FLASH_IO0_DLY)) = (0x00000000) #define DEF_FLASH_IO1_DLY() (REG32(ADR_FLASH_IO1_DLY)) = (0x00000100) #define DEF_INS_SPACE_START_ADDR() (REG32(ADR_INS_SPACE_START_ADDR)) = (0x00000000) #define DEF_INS_SPACE_END_ADDR() (REG32(ADR_INS_SPACE_END_ADDR)) = (0x00000000) #define DEF_BUFFER_CLEAR_ERROR_FLAG_CLEAR() (REG32(ADR_BUFFER_CLEAR_ERROR_FLAG_CLEAR)) = (0x00000000) #define DEF_DMA_ADR_SRC() (REG32(ADR_DMA_ADR_SRC)) = (0x00000000) #define DEF_DMA_ADR_DST() (REG32(ADR_DMA_ADR_DST)) = (0x00000000) #define DEF_DMA_CTRL() (REG32(ADR_DMA_CTRL)) = (0x000000aa) #define DEF_DMA_INT() (REG32(ADR_DMA_INT)) = (0x00000001) #define DEF_DMA_FILL_CONST() (REG32(ADR_DMA_FILL_CONST)) = (0x00000000) #define DEF_D2_DMA_ADR_SRC() (REG32(ADR_D2_DMA_ADR_SRC)) = (0x00000000) #define DEF_D2_DMA_ADR_DST() (REG32(ADR_D2_DMA_ADR_DST)) = (0x00000000) #define DEF_D2_DMA_CTRL() (REG32(ADR_D2_DMA_CTRL)) = (0x000000aa) #define DEF_D2_DMA_INT() (REG32(ADR_D2_DMA_INT)) = (0x00000001) #define DEF_D2_DMA_FILL_CONST() (REG32(ADR_D2_DMA_FILL_CONST)) = (0x00000000) #define DEF_MASK_TYPHOST_INT_MAP_02() (REG32(ADR_MASK_TYPHOST_INT_MAP_02)) = (0xffffffff) #define DEF_RAW_TYPHOST_INT_MAP_02() (REG32(ADR_RAW_TYPHOST_INT_MAP_02)) = (0xffffffff) #define DEF_POSTMASK_TYPHOST_INT_MAP_02() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP_02)) = (0xffffffff) #define DEF_MASK_TYPHOST_INT_MAP_15() (REG32(ADR_MASK_TYPHOST_INT_MAP_15)) = (0xffffffff) #define DEF_RAW_TYPHOST_INT_MAP_15() (REG32(ADR_RAW_TYPHOST_INT_MAP_15)) = (0xffffffff) #define DEF_POSTMASK_TYPHOST_INT_MAP_15() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP_15)) = (0xffffffff) #define DEF_MASK_TYPHOST_INT_MAP_31() (REG32(ADR_MASK_TYPHOST_INT_MAP_31)) = (0xffffffff) #define DEF_RAW_TYPHOST_INT_MAP_31() (REG32(ADR_RAW_TYPHOST_INT_MAP_31)) = (0xffffffff) #define DEF_POSTMASK_TYPHOST_INT_MAP_31() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP_31)) = (0xffffffff) #define DEF_MASK_TYPHOST_INT_MAP() (REG32(ADR_MASK_TYPHOST_INT_MAP)) = (0xffffffff) #define DEF_RAW_TYPHOST_INT_MAP() (REG32(ADR_RAW_TYPHOST_INT_MAP)) = (0xffffffff) #define DEF_POSTMASK_TYPHOST_INT_MAP() (REG32(ADR_POSTMASK_TYPHOST_INT_MAP)) = (0xffffffff) #define DEF_SUMMARY_TYPHOST_INT_MAP() (REG32(ADR_SUMMARY_TYPHOST_INT_MAP)) = (0x00000000) #define DEF_MASK_TYPMCU_INT_MAP_02() (REG32(ADR_MASK_TYPMCU_INT_MAP_02)) = (0xffffffff) #define DEF_RAW_TYPMCU_INT_MAP_02() (REG32(ADR_RAW_TYPMCU_INT_MAP_02)) = (0xffffffff) #define DEF_POSTMASK_TYPMCU_INT_MAP_02() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP_02)) = (0xffffffff) #define DEF_MASK_TYPMCU_INT_MAP_15() (REG32(ADR_MASK_TYPMCU_INT_MAP_15)) = (0xffffffff) #define DEF_RAW_TYPMCU_INT_MAP_15() (REG32(ADR_RAW_TYPMCU_INT_MAP_15)) = (0xffffffff) #define DEF_POSTMASK_TYPMCU_INT_MAP_15() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP_15)) = (0xffffffff) #define DEF_MASK_TYPMCU_INT_MAP_31() (REG32(ADR_MASK_TYPMCU_INT_MAP_31)) = (0xffffffff) #define DEF_RAW_TYPMCU_INT_MAP_31() (REG32(ADR_RAW_TYPMCU_INT_MAP_31)) = (0xffffffff) #define DEF_POSTMASK_TYPMCU_INT_MAP_31() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP_31)) = (0xffffffff) #define DEF_MASK_TYPMCU_INT_MAP() (REG32(ADR_MASK_TYPMCU_INT_MAP)) = (0xffffffff) #define DEF_RAW_TYPMCU_INT_MAP() (REG32(ADR_RAW_TYPMCU_INT_MAP)) = (0xffffffff) #define DEF_POSTMASK_TYPMCU_INT_MAP() (REG32(ADR_POSTMASK_TYPMCU_INT_MAP)) = (0xffffffff) #define DEF_SUMMARY_TYPMCU_INT_MAP() (REG32(ADR_SUMMARY_TYPMCU_INT_MAP)) = (0x00000000) #define DEF_GPIO_INTERRUPT_BANK_00_TO_07() (REG32(ADR_GPIO_INTERRUPT_BANK_00_TO_07)) = (0x00000000) #define DEF_GPIO_INTERRUPT_BANK_08_TO_15() (REG32(ADR_GPIO_INTERRUPT_BANK_08_TO_15)) = (0x00000000) #define DEF_GPIO_INTERRUPT_BANK_16_TO_22() (REG32(ADR_GPIO_INTERRUPT_BANK_16_TO_22)) = (0x00000000) #define DEF_GPIO_INTERRUPT_MODE_00_TO_07() (REG32(ADR_GPIO_INTERRUPT_MODE_00_TO_07)) = (0x00000000) #define DEF_GPIO_INTERRUPT_MODE_08_TO_15() (REG32(ADR_GPIO_INTERRUPT_MODE_08_TO_15)) = (0x00000000) #define DEF_GPIO_INTERRUPT_MODE_16_TO_22() (REG32(ADR_GPIO_INTERRUPT_MODE_16_TO_22)) = (0x00000000) #define DEF_IPC_INTERRUPT() (REG32(ADR_IPC_INTERRUPT)) = (0x00000000) #define DEF_CLR_INT_STS2() (REG32(ADR_CLR_INT_STS2)) = (0x00000000) #define DEF_CLR_INT_STS1() (REG32(ADR_CLR_INT_STS1)) = (0x00000000) #define DEF_CLR_INT_STS0() (REG32(ADR_CLR_INT_STS0)) = (0x00000000) #define DEF_ROM_PATCH02_0() (REG32(ADR_ROM_PATCH02_0)) = (0x00000000) #define DEF_ROM_PATCH02_1() (REG32(ADR_ROM_PATCH02_1)) = (0x00000000) #define DEF_ROM_PATCH03_0() (REG32(ADR_ROM_PATCH03_0)) = (0x00000000) #define DEF_ROM_PATCH03_1() (REG32(ADR_ROM_PATCH03_1)) = (0x00000000) #define DEF_ROM_PATCH04_0() (REG32(ADR_ROM_PATCH04_0)) = (0x00000000) #define DEF_ROM_PATCH04_1() (REG32(ADR_ROM_PATCH04_1)) = (0x00000000) #define DEF_ROM_PATCH05_0() (REG32(ADR_ROM_PATCH05_0)) = (0x00000000) #define DEF_ROM_PATCH05_1() (REG32(ADR_ROM_PATCH05_1)) = (0x00000000) #define DEF_ROM_PATCH06_0() (REG32(ADR_ROM_PATCH06_0)) = (0x00000000) #define DEF_ROM_PATCH06_1() (REG32(ADR_ROM_PATCH06_1)) = (0x00000000) #define DEF_ROM_PATCH07_0() (REG32(ADR_ROM_PATCH07_0)) = (0x00000000) #define DEF_ROM_PATCH07_1() (REG32(ADR_ROM_PATCH07_1)) = (0x00000000) #define DEF_ROM_PATCH08_0() (REG32(ADR_ROM_PATCH08_0)) = (0x00000000) #define DEF_ROM_PATCH08_1() (REG32(ADR_ROM_PATCH08_1)) = (0x00000000) #define DEF_ROM_PATCH09_0() (REG32(ADR_ROM_PATCH09_0)) = (0x00000000) #define DEF_ROM_PATCH09_1() (REG32(ADR_ROM_PATCH09_1)) = (0x00000000) #define DEF_ROM_PATCH10_0() (REG32(ADR_ROM_PATCH10_0)) = (0x00000000) #define DEF_ROM_PATCH10_1() (REG32(ADR_ROM_PATCH10_1)) = (0x00000000) #define DEF_ROM_PATCH11_0() (REG32(ADR_ROM_PATCH11_0)) = (0x00000000) #define DEF_ROM_PATCH11_1() (REG32(ADR_ROM_PATCH11_1)) = (0x00000000) #define DEF_ROM_PATCH12_0() (REG32(ADR_ROM_PATCH12_0)) = (0x00000000) #define DEF_ROM_PATCH12_1() (REG32(ADR_ROM_PATCH12_1)) = (0x00000000) #define DEF_ROM_PATCH13_0() (REG32(ADR_ROM_PATCH13_0)) = (0x00000000) #define DEF_ROM_PATCH13_1() (REG32(ADR_ROM_PATCH13_1)) = (0x00000000) #define DEF_ROM_PATCH14_0() (REG32(ADR_ROM_PATCH14_0)) = (0x00000000) #define DEF_ROM_PATCH14_1() (REG32(ADR_ROM_PATCH14_1)) = (0x00000000) #define DEF_ROM_PATCH15_0() (REG32(ADR_ROM_PATCH15_0)) = (0x00000000) #define DEF_ROM_PATCH15_1() (REG32(ADR_ROM_PATCH15_1)) = (0x00000000) #define DEF_BROWNOUT_INT() (REG32(ADR_BROWNOUT_INT)) = (0x00000000) #define DEF_BROWNOUT_SETUP() (REG32(ADR_BROWNOUT_SETUP)) = (0x0000000f) #define DEF_CONTROL() (REG32(ADR_CONTROL)) = (0x00700008) #define DEF_HCI_TRX_MODE() (REG32(ADR_HCI_TRX_MODE)) = (0x00000002) #define DEF_TX_FLOW_0() (REG32(ADR_TX_FLOW_0)) = (0x00000000) #define DEF_TX_FLOW_1() (REG32(ADR_TX_FLOW_1)) = (0x00000000) #define DEF_REMAINING_RX_PACKET_LENGTH() (REG32(ADR_REMAINING_RX_PACKET_LENGTH)) = (0x00000000) #define DEF_RX_PACKET_LENGTH_STATUS() (REG32(ADR_RX_PACKET_LENGTH_STATUS)) = (0x00000000) #define DEF_THRESHOLD() (REG32(ADR_THRESHOLD)) = (0x09000000) #define DEF_TX_ERROR_RECEOVERY() (REG32(ADR_TX_ERROR_RECEOVERY)) = (0x00000002) #define DEF_TXFID_INCREASE() (REG32(ADR_TXFID_INCREASE)) = (0x00000000) #define DEF_GLOBAL_SEQUENCE() (REG32(ADR_GLOBAL_SEQUENCE)) = (0x00000000) #define DEF_HCI_REG_0X2C() (REG32(ADR_HCI_REG_0X2C)) = (0x00000300) #define DEF_HCI_TX_RX_INFO_SIZE() (REG32(ADR_HCI_TX_RX_INFO_SIZE)) = (0x00040450) #define DEF_HCI_TX_INFO_CLEAR() (REG32(ADR_HCI_TX_INFO_CLEAR)) = (0x00000008) #define DEF_HCI_TO_PKTBUF_SETTING() (REG32(ADR_HCI_TO_PKTBUF_SETTING)) = (0x00000410) #define DEF_HCI_MANUAL_ALLOC() (REG32(ADR_HCI_MANUAL_ALLOC)) = (0x00000000) #define DEF_HCI_MANUAL_ALLOC_ACTION() (REG32(ADR_HCI_MANUAL_ALLOC_ACTION)) = (0x00000000) #define DEF_HCI_MANUAL_ALLOC_STATUS() (REG32(ADR_HCI_MANUAL_ALLOC_STATUS)) = (0x00000000) #define DEF_TX_ETHER_TYPE_0() (REG32(ADR_TX_ETHER_TYPE_0)) = (0x00000000) #define DEF_TX_ETHER_TYPE_1() (REG32(ADR_TX_ETHER_TYPE_1)) = (0x00000000) #define DEF_RX_ETHER_TYPE_0() (REG32(ADR_RX_ETHER_TYPE_0)) = (0x00000000) #define DEF_RX_ETHER_TYPE_1() (REG32(ADR_RX_ETHER_TYPE_1)) = (0x00000000) #define DEF_TX_PACKET_LENGTH() (REG32(ADR_TX_PACKET_LENGTH)) = (0x00000000) #define DEF_TX_PACKET_ID() (REG32(ADR_TX_PACKET_ID)) = (0x00000000) #define DEF_RX_RESCUE_HELPER() (REG32(ADR_RX_RESCUE_HELPER)) = (0x00000000) #define DEF_HCI_FORCE_PRE_BULK_IN() (REG32(ADR_HCI_FORCE_PRE_BULK_IN)) = (0x00000000) #define DEF_HCI_BULK_IN_TIME_OUT_VALUE() (REG32(ADR_HCI_BULK_IN_TIME_OUT_VALUE)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_0() (REG32(ADR_HCI_STATE_DEBUG_MODE_0)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_2() (REG32(ADR_HCI_STATE_DEBUG_MODE_2)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_3() (REG32(ADR_HCI_STATE_DEBUG_MODE_3)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_4() (REG32(ADR_HCI_STATE_DEBUG_MODE_4)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_5() (REG32(ADR_HCI_STATE_DEBUG_MODE_5)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_6() (REG32(ADR_HCI_STATE_DEBUG_MODE_6)) = (0x00000000) #define DEF_HCI_STATE_DEBUG_MODE_7() (REG32(ADR_HCI_STATE_DEBUG_MODE_7)) = (0x00000000) #define DEF_HCI_TX_ON_DEMAND_LENGTH() (REG32(ADR_HCI_TX_ON_DEMAND_LENGTH)) = (0x00000000) #define DEF_HCI_TX_ALLOC_SUCCESS_COUNT() (REG32(ADR_HCI_TX_ALLOC_SUCCESS_COUNT)) = (0x00000000) #define DEF_HCI_TX_ALLOC_SPENDING_TIME() (REG32(ADR_HCI_TX_ALLOC_SPENDING_TIME)) = (0x00000000) #define DEF_RX_TRAP_COUNT() (REG32(ADR_RX_TRAP_COUNT)) = (0x00000000) #define DEF_TX_TRAP_COUNT() (REG32(ADR_TX_TRAP_COUNT)) = (0x00000000) #define DEF_RX_DROP_COUNT() (REG32(ADR_RX_DROP_COUNT)) = (0x00000000) #define DEF_TX_DROP_COUNT() (REG32(ADR_TX_DROP_COUNT)) = (0x00000000) #define DEF_RX_HOST_EVENT_COUNT() (REG32(ADR_RX_HOST_EVENT_COUNT)) = (0x00000000) #define DEF_TX_HOST_COMMAND_COUNT() (REG32(ADR_TX_HOST_COMMAND_COUNT)) = (0x00000000) #define DEF_RX_PACKET_COUNTER() (REG32(ADR_RX_PACKET_COUNTER)) = (0x00000000) #define DEF_TX_PACKET_COUNTER() (REG32(ADR_TX_PACKET_COUNTER)) = (0x00000000) #define DEF_SDIO_RX_FAIL_COUNT() (REG32(ADR_SDIO_RX_FAIL_COUNT)) = (0x00000000) #define DEF_SDIO_TX_FAIL_COUNT() (REG32(ADR_SDIO_TX_FAIL_COUNT)) = (0x00000000) #define DEF_CORRECT_RATE_REPORT_LENGTH() (REG32(ADR_CORRECT_RATE_REPORT_LENGTH)) = (0x00000000) #define DEF_TX_PACKET_SEND_TO_RX_DIRECTLY() (REG32(ADR_TX_PACKET_SEND_TO_RX_DIRECTLY)) = (0x00000000) #define DEF_POWER_SAVING_PEER_REJECT_FUNCTION() (REG32(ADR_POWER_SAVING_PEER_REJECT_FUNCTION)) = (0x00000000) #define DEF_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION() (REG32(ADR_TX_RX_TRAP_HW_ID_SELECTION_FUNCTION)) = (0x00000000) #define DEF_RX_HCI_EXP_0_CTRL() (REG32(ADR_RX_HCI_EXP_0_CTRL)) = (0x00000000) #define DEF_RX_HCI_EXP_0_LEN() (REG32(ADR_RX_HCI_EXP_0_LEN)) = (0x400000c8) #define DEF_FORCE_RX_AGGREGATION_MODE() (REG32(ADR_FORCE_RX_AGGREGATION_MODE)) = (0x03200002) #define DEF_CS_START_ADDR() (REG32(ADR_CS_START_ADDR)) = (0x00000000) #define DEF_CS_ADD_LEN() (REG32(ADR_CS_ADD_LEN)) = (0x00000000) #define DEF_CS_CMD() (REG32(ADR_CS_CMD)) = (0x00000000) #define DEF_CS_INI_BUF() (REG32(ADR_CS_INI_BUF)) = (0x00000000) #define DEF_CS_PSEUDO_BUF() (REG32(ADR_CS_PSEUDO_BUF)) = (0x00000000) #define DEF_CS_CHECK_SUM() (REG32(ADR_CS_CHECK_SUM)) = (0x00000000) #define DEF_RAND_EN() (REG32(ADR_RAND_EN)) = (0x00000000) #define DEF_RAND_NUM() (REG32(ADR_RAND_NUM)) = (0x00000000) #define DEF_MUL_OP1() (REG32(ADR_MUL_OP1)) = (0x00000000) #define DEF_MUL_OP2() (REG32(ADR_MUL_OP2)) = (0x00000000) #define DEF_MUL_ANS0() (REG32(ADR_MUL_ANS0)) = (0x00000000) #define DEF_MUL_ANS1() (REG32(ADR_MUL_ANS1)) = (0x00000000) #define DEF_DMA_RDATA() (REG32(ADR_DMA_RDATA)) = (0x00000000) #define DEF_DMA_WDATA() (REG32(ADR_DMA_WDATA)) = (0x00000000) #define DEF_DMA_LEN() (REG32(ADR_DMA_LEN)) = (0x00000000) #define DEF_DMA_CLR() (REG32(ADR_DMA_CLR)) = (0x00000000) #define DEF_NAV_DATA() (REG32(ADR_NAV_DATA)) = (0x00000000) #define DEF_CO_NAV() (REG32(ADR_CO_NAV)) = (0x00000000) #define DEF_SHA_DST_ADDR() (REG32(ADR_SHA_DST_ADDR)) = (0x00000000) #define DEF_SHA_SRC_ADDR() (REG32(ADR_SHA_SRC_ADDR)) = (0x00000000) #define DEF_SHA_SETTING() (REG32(ADR_SHA_SETTING)) = (0x00000002) #define DEF_EFUSE_CLK_FREQ() (REG32(ADR_EFUSE_CLK_FREQ)) = (0x610100d0) #define DEF_EFUSE_LDO_TIME() (REG32(ADR_EFUSE_LDO_TIME)) = (0x00020002) #define DEF_EFUSE_STATUS() (REG32(ADR_EFUSE_STATUS)) = (0x00000000) #define DEF_EFUSE_STATUS2() (REG32(ADR_EFUSE_STATUS2)) = (0x00000000) #define DEF_EFUSE_WR_KICK() (REG32(ADR_EFUSE_WR_KICK)) = (0x00000000) #define DEF_EFUSE_RD_KICK() (REG32(ADR_EFUSE_RD_KICK)) = (0x00000000) #define DEF_EFUSE_VDDQ_EN() (REG32(ADR_EFUSE_VDDQ_EN)) = (0x00000000) #define DEF_EFUSE_WDATA_0_0() (REG32(ADR_EFUSE_WDATA_0_0)) = (0x00000000) #define DEF_EFUSE_WDATA_0_1() (REG32(ADR_EFUSE_WDATA_0_1)) = (0x00000000) #define DEF_EFUSE_WDATA_0_2() (REG32(ADR_EFUSE_WDATA_0_2)) = (0x00000000) #define DEF_EFUSE_WDATA_0_3() (REG32(ADR_EFUSE_WDATA_0_3)) = (0x00000000) #define DEF_EFUSE_WDATA_0_4() (REG32(ADR_EFUSE_WDATA_0_4)) = (0x00000000) #define DEF_EFUSE_WDATA_0_5() (REG32(ADR_EFUSE_WDATA_0_5)) = (0x00000000) #define DEF_EFUSE_WDATA_0_6() (REG32(ADR_EFUSE_WDATA_0_6)) = (0x00000000) #define DEF_EFUSE_WDATA_0_7() (REG32(ADR_EFUSE_WDATA_0_7)) = (0x00000000) #define DEF_SPI_DELAY() (REG32(ADR_SPI_DELAY)) = (0x000f000f) #define DEF_SPI_CLK_DIV() (REG32(ADR_SPI_CLK_DIV)) = (0x00000001) #define DEF_SPI_BUSY() (REG32(ADR_SPI_BUSY)) = (0x00000000) #define DEF_SPI_CLR() (REG32(ADR_SPI_CLR)) = (0x00000000) #define DEF_SPI_MAS_MODE() (REG32(ADR_SPI_MAS_MODE)) = (0x00000000) #define DEF_SPI_M_CFG() (REG32(ADR_SPI_M_CFG)) = (0x00000008) #define DEF_SPI_CFG() (REG32(ADR_SPI_CFG)) = (0x00000001) #define DEF_SPI_MAS_COMMAND_LEN() (REG32(ADR_SPI_MAS_COMMAND_LEN)) = (0x00000000) #define DEF_MRX_MCAST_TB0_0() (REG32(ADR_MRX_MCAST_TB0_0)) = (0x00000000) #define DEF_MRX_MCAST_TB0_1() (REG32(ADR_MRX_MCAST_TB0_1)) = (0x00000000) #define DEF_MRX_MCAST_MK0_0() (REG32(ADR_MRX_MCAST_MK0_0)) = (0x00000000) #define DEF_MRX_MCAST_MK0_1() (REG32(ADR_MRX_MCAST_MK0_1)) = (0x00000000) #define DEF_MRX_MCAST_CTRL0() (REG32(ADR_MRX_MCAST_CTRL0)) = (0x00000000) #define DEF_MRX_MCAST_TB1_0() (REG32(ADR_MRX_MCAST_TB1_0)) = (0x00000000) #define DEF_MRX_MCAST_TB1_1() (REG32(ADR_MRX_MCAST_TB1_1)) = (0x00000000) #define DEF_MRX_MCAST_MK1_0() (REG32(ADR_MRX_MCAST_MK1_0)) = (0x00000000) #define DEF_MRX_MCAST_MK1_1() (REG32(ADR_MRX_MCAST_MK1_1)) = (0x00000000) #define DEF_MRX_MCAST_CTRL1() (REG32(ADR_MRX_MCAST_CTRL1)) = (0x00000000) #define DEF_MRX_MCAST_TB2_0() (REG32(ADR_MRX_MCAST_TB2_0)) = (0x00000000) #define DEF_MRX_MCAST_TB2_1() (REG32(ADR_MRX_MCAST_TB2_1)) = (0x00000000) #define DEF_MRX_MCAST_MK2_0() (REG32(ADR_MRX_MCAST_MK2_0)) = (0x00000000) #define DEF_MRX_MCAST_MK2_1() (REG32(ADR_MRX_MCAST_MK2_1)) = (0x00000000) #define DEF_MRX_MCAST_CTRL2() (REG32(ADR_MRX_MCAST_CTRL2)) = (0x00000000) #define DEF_MRX_MCAST_TB3_0() (REG32(ADR_MRX_MCAST_TB3_0)) = (0x00000000) #define DEF_MRX_MCAST_TB3_1() (REG32(ADR_MRX_MCAST_TB3_1)) = (0x00000000) #define DEF_MRX_MCAST_MK3_0() (REG32(ADR_MRX_MCAST_MK3_0)) = (0x00000000) #define DEF_MRX_MCAST_MK3_1() (REG32(ADR_MRX_MCAST_MK3_1)) = (0x00000000) #define DEF_MRX_MCAST_CTRL3() (REG32(ADR_MRX_MCAST_CTRL3)) = (0x00000000) #define DEF_MRX_PHY_INFO() (REG32(ADR_MRX_PHY_INFO)) = (0x00000000) #define DEF_MRX_BA_DBG() (REG32(ADR_MRX_BA_DBG)) = (0x00000000) #define DEF_MRX_FLT_TB0() (REG32(ADR_MRX_FLT_TB0)) = (0x00003df5) #define DEF_MRX_FLT_TB1() (REG32(ADR_MRX_FLT_TB1)) = (0x000031f6) #define DEF_MRX_FLT_TB2() (REG32(ADR_MRX_FLT_TB2)) = (0x000035f9) #define DEF_MRX_FLT_TB3() (REG32(ADR_MRX_FLT_TB3)) = (0x000021c1) #define DEF_MRX_FLT_TB4() (REG32(ADR_MRX_FLT_TB4)) = (0x00004bf9) #define DEF_MRX_FLT_TB5() (REG32(ADR_MRX_FLT_TB5)) = (0x00004db1) #define DEF_MRX_FLT_TB6() (REG32(ADR_MRX_FLT_TB6)) = (0x000011fe) #define DEF_MRX_FLT_TB7() (REG32(ADR_MRX_FLT_TB7)) = (0x00000bfe) #define DEF_MRX_FLT_TB8() (REG32(ADR_MRX_FLT_TB8)) = (0x00000000) #define DEF_MRX_FLT_TB9() (REG32(ADR_MRX_FLT_TB9)) = (0x00000000) #define DEF_MRX_FLT_TB10() (REG32(ADR_MRX_FLT_TB10)) = (0x00000000) #define DEF_MRX_FLT_TB11() (REG32(ADR_MRX_FLT_TB11)) = (0x00000006) #define DEF_MRX_FLT_TB12() (REG32(ADR_MRX_FLT_TB12)) = (0x00000001) #define DEF_MRX_FLT_TB13() (REG32(ADR_MRX_FLT_TB13)) = (0x00000003) #define DEF_MRX_FLT_TB14() (REG32(ADR_MRX_FLT_TB14)) = (0x00000005) #define DEF_MRX_FLT_TB15() (REG32(ADR_MRX_FLT_TB15)) = (0x00000007) #define DEF_MRX_FLT_EN0() (REG32(ADR_MRX_FLT_EN0)) = (0x00002008) #define DEF_MRX_FLT_EN1() (REG32(ADR_MRX_FLT_EN1)) = (0x00001001) #define DEF_MRX_FLT_EN2() (REG32(ADR_MRX_FLT_EN2)) = (0x00000808) #define DEF_MRX_FLT_EN3() (REG32(ADR_MRX_FLT_EN3)) = (0x00001000) #define DEF_MRX_FLT_EN4() (REG32(ADR_MRX_FLT_EN4)) = (0x00002008) #define DEF_MRX_FLT_EN5() (REG32(ADR_MRX_FLT_EN5)) = (0x0000800e) #define DEF_MRX_FLT_EN6() (REG32(ADR_MRX_FLT_EN6)) = (0x00000838) #define DEF_MRX_FLT_EN7() (REG32(ADR_MRX_FLT_EN7)) = (0x00002008) #define DEF_MRX_FLT_EN8() (REG32(ADR_MRX_FLT_EN8)) = (0x00002008) #define DEF_MRX_LEN_FLT() (REG32(ADR_MRX_LEN_FLT)) = (0x00000000) #define DEF_RX_FLOW_DATA() (REG32(ADR_RX_FLOW_DATA)) = (0x00105034) #define DEF_RX_FLOW_MNG() (REG32(ADR_RX_FLOW_MNG)) = (0x00000004) #define DEF_RX_FLOW_CTRL() (REG32(ADR_RX_FLOW_CTRL)) = (0x00000004) #define DEF_RX_TIME_STAMP_CFG() (REG32(ADR_RX_TIME_STAMP_CFG)) = (0x00001c00) #define DEF_DBG_FF_FULL() (REG32(ADR_DBG_FF_FULL)) = (0x00000000) #define DEF_DBG_WFF_FULL() (REG32(ADR_DBG_WFF_FULL)) = (0x00000000) #define DEF_DBG_MB_FULL() (REG32(ADR_DBG_MB_FULL)) = (0x00000000) #define DEF_BA_CTRL() (REG32(ADR_BA_CTRL)) = (0x00000008) #define DEF_BA_TA_0() (REG32(ADR_BA_TA_0)) = (0x00000000) #define DEF_BA_TA_1() (REG32(ADR_BA_TA_1)) = (0x00000000) #define DEF_BA_TID() (REG32(ADR_BA_TID)) = (0x00000000) #define DEF_BA_ST_SEQ() (REG32(ADR_BA_ST_SEQ)) = (0x00000000) #define DEF_BA_SB0() (REG32(ADR_BA_SB0)) = (0x00000000) #define DEF_BA_SB1() (REG32(ADR_BA_SB1)) = (0x00000000) #define DEF_MRX_WATCH_DOG() (REG32(ADR_MRX_WATCH_DOG)) = (0x0000ffff) #define DEF_ACK_GEN_EN() (REG32(ADR_ACK_GEN_EN)) = (0x00000000) #define DEF_ACK_GEN_PARA() (REG32(ADR_ACK_GEN_PARA)) = (0x00000000) #define DEF_ACK_GEN_RA_0() (REG32(ADR_ACK_GEN_RA_0)) = (0x00000000) #define DEF_ACK_GEN_RA_1() (REG32(ADR_ACK_GEN_RA_1)) = (0x00000000) #define DEF_MIB_LEN_FAIL() (REG32(ADR_MIB_LEN_FAIL)) = (0x00000000) #define DEF_TRAP_HW_ID() (REG32(ADR_TRAP_HW_ID)) = (0x00000000) #define DEF_ID_IN_USE() (REG32(ADR_ID_IN_USE)) = (0x00000000) #define DEF_MRX_ERR() (REG32(ADR_MRX_ERR)) = (0x00000000) #define DEF_GROUP_WSID() (REG32(ADR_GROUP_WSID)) = (0x0000000e) #define DEF_HDR_ADDR_SEL() (REG32(ADR_HDR_ADDR_SEL)) = (0x00003e79) #define DEF_FRAME_TYPE_CNTR_SET() (REG32(ADR_FRAME_TYPE_CNTR_SET)) = (0x00000000) #define DEF_AMPDU_SCOREBOAD_SIZE() (REG32(ADR_AMPDU_SCOREBOAD_SIZE)) = (0x00000040) #define DEF_CHANNEL() (REG32(ADR_CHANNEL)) = (0x00000006) #define DEF_HIGH_PRIORITY_FRM_HW_ID() (REG32(ADR_HIGH_PRIORITY_FRM_HW_ID)) = (0x00000000) #define DEF_DUAL_IDX_EXTEND() (REG32(ADR_DUAL_IDX_EXTEND)) = (0x00000000) #define DEF_MRX_FLT_EN9() (REG32(ADR_MRX_FLT_EN9)) = (0x00000808) #define DEF_MRX_FLT_EN10() (REG32(ADR_MRX_FLT_EN10)) = (0x00000838) #define DEF_PHY_INFO() (REG32(ADR_PHY_INFO)) = (0x00000000) #define DEF_AMPDU_SIG() (REG32(ADR_AMPDU_SIG)) = (0x0000004e) #define DEF_MIB_AMPDU() (REG32(ADR_MIB_AMPDU)) = (0x00000000) #define DEF_LEN_FLT() (REG32(ADR_LEN_FLT)) = (0x00000000) #define DEF_MIB_DELIMITER() (REG32(ADR_MIB_DELIMITER)) = (0x00000000) #define DEF_MTX_INT_STS() (REG32(ADR_MTX_INT_STS)) = (0x00000000) #define DEF_MTX_INT_EN() (REG32(ADR_MTX_INT_EN)) = (0x00000000) #define DEF_MTX_MISC_EN() (REG32(ADR_MTX_MISC_EN)) = (0x00004022) #define DEF_MTX_TX_REPORT_OPTION() (REG32(ADR_MTX_TX_REPORT_OPTION)) = (0x00000095) #define DEF_MTX_STATUS0() (REG32(ADR_MTX_STATUS0)) = (0x00000000) #define DEF_MTX_STATUS4() (REG32(ADR_MTX_STATUS4)) = (0x00000000) #define DEF_MTX_HALT_OPTION() (REG32(ADR_MTX_HALT_OPTION)) = (0x00000000) #define DEF_MTX_PHYTX_DBG1() (REG32(ADR_MTX_PHYTX_DBG1)) = (0x00000000) #define DEF_MTX_MIB_WSID0() (REG32(ADR_MTX_MIB_WSID0)) = (0x00000000) #define DEF_MTX_MIB_WSID1() (REG32(ADR_MTX_MIB_WSID1)) = (0x00000000) #define DEF_MTX_MIB_WSID2() (REG32(ADR_MTX_MIB_WSID2)) = (0x00000000) #define DEF_MTX_MIB_WSID3() (REG32(ADR_MTX_MIB_WSID3)) = (0x00000000) #define DEF_MTX_MIB_WSID4() (REG32(ADR_MTX_MIB_WSID4)) = (0x00000000) #define DEF_MTX_MIB_WSID5() (REG32(ADR_MTX_MIB_WSID5)) = (0x00000000) #define DEF_MTX_MIB_WSID6() (REG32(ADR_MTX_MIB_WSID6)) = (0x00000000) #define DEF_MTX_MIB_WSID7() (REG32(ADR_MTX_MIB_WSID7)) = (0x00000000) #define DEF_STAT_CONF0() (REG32(ADR_STAT_CONF0)) = (0x00000001) #define DEF_STAT_CONF1() (REG32(ADR_STAT_CONF1)) = (0x00000000) #define DEF_MTX_PEER_PS_LOCK() (REG32(ADR_MTX_PEER_PS_LOCK)) = (0x00000200) #define DEF_MTX_PEER_LOCK_STATUS() (REG32(ADR_MTX_PEER_LOCK_STATUS)) = (0x00000000) #define DEF_MTX_RATERPT() (REG32(ADR_MTX_RATERPT)) = (0x00000070) #define DEF_MTX_DBGOPT_FORCE_RATE() (REG32(ADR_MTX_DBGOPT_FORCE_RATE)) = (0x000194c0) #define DEF_MTX_DBGOPT_FORCE_RATE_ENABLE() (REG32(ADR_MTX_DBGOPT_FORCE_RATE_ENABLE)) = (0x00000000) #define DEF_MTX_DBG_PHYTXIPTIMEOUT() (REG32(ADR_MTX_DBG_PHYTXIPTIMEOUT)) = (0x00000000) #define DEF_MTX_DBG_MORE() (REG32(ADR_MTX_DBG_MORE)) = (0x00000000) #define DEF_MTX_DBG_ROIFSAIR1() (REG32(ADR_MTX_DBG_ROIFSAIR1)) = (0x00000000) #define DEF_MTX_DBG_ROIFSAIR2() (REG32(ADR_MTX_DBG_ROIFSAIR2)) = (0x00000000) #define DEF_MTX_BCN_PKT_SET0() (REG32(ADR_MTX_BCN_PKT_SET0)) = (0x00000064) #define DEF_MTX_BCN_PKT_SET1() (REG32(ADR_MTX_BCN_PKT_SET1)) = (0x00000064) #define DEF_MTX_BCN_DTIM_SET0() (REG32(ADR_MTX_BCN_DTIM_SET0)) = (0x00000016) #define DEF_MTX_BCN_DTIM_SET1() (REG32(ADR_MTX_BCN_DTIM_SET1)) = (0x00000016) #define DEF_MTX_BCN_DTIM_CONFG() (REG32(ADR_MTX_BCN_DTIM_CONFG)) = (0x00000000) #define DEF_MTX_BCN_DTIM_INT_W1CLR() (REG32(ADR_MTX_BCN_DTIM_INT_W1CLR)) = (0x00000000) #define DEF_MTX_BCN_INT_STS() (REG32(ADR_MTX_BCN_INT_STS)) = (0x00000000) #define DEF_MTX_BCN_EN_INT() (REG32(ADR_MTX_BCN_EN_INT)) = (0x00000000) #define DEF_MTX_BCN_EN_MISC() (REG32(ADR_MTX_BCN_EN_MISC)) = (0x0000000a) #define DEF_MTX_BCN_MISC() (REG32(ADR_MTX_BCN_MISC)) = (0x00000000) #define DEF_MTX_BCN_PRD() (REG32(ADR_MTX_BCN_PRD)) = (0x00000064) #define DEF_MTX_BCN_TSF_L() (REG32(ADR_MTX_BCN_TSF_L)) = (0x00000000) #define DEF_MTX_BCN_TSF_U() (REG32(ADR_MTX_BCN_TSF_U)) = (0x00000000) #define DEF_MTX_TIME_TOUT() (REG32(ADR_MTX_TIME_TOUT)) = (0x00052c2c) #define DEF_MTX_TIME_IFS() (REG32(ADR_MTX_TIME_IFS)) = (0x000a0962) #define DEF_MTX_TIME_FINETUNE() (REG32(ADR_MTX_TIME_FINETUNE)) = (0x060d0000) #define DEF_MTX_STATUS() (REG32(ADR_MTX_STATUS)) = (0x00000000) #define DEF_MTX_PHYRXIFS_DBG() (REG32(ADR_MTX_PHYRXIFS_DBG)) = (0x00000000) #define DEF_MTX_DBG_IFSAIRRO0() (REG32(ADR_MTX_DBG_IFSAIRRO0)) = (0x00000000) #define DEF_MTX_DBG_IFSAIRRO1() (REG32(ADR_MTX_DBG_IFSAIRRO1)) = (0x00000000) #define DEF_MTX_DBG_IFSAIRRO2() (REG32(ADR_MTX_DBG_IFSAIRRO2)) = (0x00000000) #define DEF_MTX_DBG_IFSAIRRO3() (REG32(ADR_MTX_DBG_IFSAIRRO3)) = (0x00000000) #define DEF_MTX_NAV() (REG32(ADR_MTX_NAV)) = (0x00000000) #define DEF_MTX_DBG_RO_BASE1() (REG32(ADR_MTX_DBG_RO_BASE1)) = (0x00000000) #define DEF_MTX_DBG_RO_BASE2() (REG32(ADR_MTX_DBG_RO_BASE2)) = (0x00000000) #define DEF_MTX_DBG_RO_BASE3() (REG32(ADR_MTX_DBG_RO_BASE3)) = (0x00000000) #define DEF_TXQ0_MTX_Q_MISC_EN() (REG32(ADR_TXQ0_MTX_Q_MISC_EN)) = (0x00000000) #define DEF_TXQ0_MTX_Q_AIFSN() (REG32(ADR_TXQ0_MTX_Q_AIFSN)) = (0x00003202) #define DEF_TXQ0_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ0_MTX_Q_BKF_CNT_DBG)) = (0x00000000) #define DEF_TXQ0_MTX_Q_HWDBG() (REG32(ADR_TXQ0_MTX_Q_HWDBG)) = (0x00000000) #define DEF_TXQ0_MTX_Q_HWDBG2() (REG32(ADR_TXQ0_MTX_Q_HWDBG2)) = (0x00000000) #define DEF_TXQ1_MTX_Q_MISC_EN() (REG32(ADR_TXQ1_MTX_Q_MISC_EN)) = (0x00000000) #define DEF_TXQ1_MTX_Q_AIFSN() (REG32(ADR_TXQ1_MTX_Q_AIFSN)) = (0x00003202) #define DEF_TXQ1_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ1_MTX_Q_BKF_CNT_DBG)) = (0x00000000) #define DEF_TXQ1_MTX_Q_HWDBG() (REG32(ADR_TXQ1_MTX_Q_HWDBG)) = (0x00000000) #define DEF_TXQ1_MTX_Q_HWDBG2() (REG32(ADR_TXQ1_MTX_Q_HWDBG2)) = (0x00000000) #define DEF_TXQ2_MTX_Q_MISC_EN() (REG32(ADR_TXQ2_MTX_Q_MISC_EN)) = (0x00000000) #define DEF_TXQ2_MTX_Q_AIFSN() (REG32(ADR_TXQ2_MTX_Q_AIFSN)) = (0x00003202) #define DEF_TXQ2_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ2_MTX_Q_BKF_CNT_DBG)) = (0x00000000) #define DEF_TXQ2_MTX_Q_HWDBG() (REG32(ADR_TXQ2_MTX_Q_HWDBG)) = (0x00000000) #define DEF_TXQ2_MTX_Q_HWDBG2() (REG32(ADR_TXQ2_MTX_Q_HWDBG2)) = (0x00000000) #define DEF_TXQ3_MTX_Q_MISC_EN() (REG32(ADR_TXQ3_MTX_Q_MISC_EN)) = (0x00000000) #define DEF_TXQ3_MTX_Q_AIFSN() (REG32(ADR_TXQ3_MTX_Q_AIFSN)) = (0x00003202) #define DEF_TXQ3_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ3_MTX_Q_BKF_CNT_DBG)) = (0x00000000) #define DEF_TXQ3_MTX_Q_HWDBG() (REG32(ADR_TXQ3_MTX_Q_HWDBG)) = (0x00000000) #define DEF_TXQ3_MTX_Q_HWDBG2() (REG32(ADR_TXQ3_MTX_Q_HWDBG2)) = (0x00000000) #define DEF_TXQ4_MTX_Q_MISC_EN() (REG32(ADR_TXQ4_MTX_Q_MISC_EN)) = (0x00000000) #define DEF_TXQ4_MTX_Q_AIFSN() (REG32(ADR_TXQ4_MTX_Q_AIFSN)) = (0x00003202) #define DEF_TXQ4_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ4_MTX_Q_BKF_CNT_DBG)) = (0x00000000) #define DEF_TXQ4_MTX_Q_HWDBG() (REG32(ADR_TXQ4_MTX_Q_HWDBG)) = (0x00000000) #define DEF_TXQ4_MTX_Q_HWDBG2() (REG32(ADR_TXQ4_MTX_Q_HWDBG2)) = (0x00000000) #define DEF_TXQ5_MTX_Q_MISC_EN() (REG32(ADR_TXQ5_MTX_Q_MISC_EN)) = (0x00000000) #define DEF_TXQ5_MTX_Q_AIFSN() (REG32(ADR_TXQ5_MTX_Q_AIFSN)) = (0x00003202) #define DEF_TXQ5_MTX_Q_BKF_CNT_DBG() (REG32(ADR_TXQ5_MTX_Q_BKF_CNT_DBG)) = (0x00000000) #define DEF_TXQ5_MTX_Q_HWDBG() (REG32(ADR_TXQ5_MTX_Q_HWDBG)) = (0x00000000) #define DEF_TXQ5_MTX_Q_HWDBG2() (REG32(ADR_TXQ5_MTX_Q_HWDBG2)) = (0x00000000) #define DEF_MTX_RESPFRM_RATE_TABLE_EXCEPTION() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_EXCEPTION)) = (0x00000000) #define DEF_MTX_RESPFRM_RATE_TABLE_00() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_00)) = (0x00000000) #define DEF_MTX_RESPFRM_RATE_TABLE_01() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_01)) = (0x00000001) #define DEF_MTX_RESPFRM_RATE_TABLE_02() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_02)) = (0x00000001) #define DEF_MTX_RESPFRM_RATE_TABLE_03() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_03)) = (0x00000001) #define DEF_MTX_RESPFRM_RATE_TABLE_11() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_11)) = (0x00000011) #define DEF_MTX_RESPFRM_RATE_TABLE_12() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_12)) = (0x00000011) #define DEF_MTX_RESPFRM_RATE_TABLE_13() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_13)) = (0x00000011) #define DEF_MTX_RESPFRM_RATE_TABLE_90_B0() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_90_B0)) = (0x00009090) #define DEF_MTX_RESPFRM_RATE_TABLE_91_B1() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_91_B1)) = (0x00009090) #define DEF_MTX_RESPFRM_RATE_TABLE_92_B2() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_92_B2)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_93_B3() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_93_B3)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_94_B4() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_94_B4)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_95_B5() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_95_B5)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_96_B6() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_96_B6)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_97_B7() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_97_B7)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_C0_E0() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C0_E0)) = (0x00009090) #define DEF_MTX_RESPFRM_RATE_TABLE_C1_E1() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C1_E1)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_C2_E2() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C2_E2)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_C3_E3() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C3_E3)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_C4_E4() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C4_E4)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_C5_E5() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C5_E5)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_C6_E6() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C6_E6)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_C7_E7() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_C7_E7)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_D0_F0() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D0_F0)) = (0x00009090) #define DEF_MTX_RESPFRM_RATE_TABLE_D1_F1() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D1_F1)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_D2_F2() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D2_F2)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_D3_F3() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D3_F3)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_D4_F4() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D4_F4)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_D5_F5() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D5_F5)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_D6_F6() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D6_F6)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_D7_F7() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D7_F7)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_D8_F8() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D8_F8)) = (0x00009090) #define DEF_MTX_RESPFRM_RATE_TABLE_D9_F9() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_D9_F9)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_DA_FA() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DA_FA)) = (0x00009292) #define DEF_MTX_RESPFRM_RATE_TABLE_DB_FB() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DB_FB)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_DC_FC() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DC_FC)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_DD_FD() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DD_FD)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_DE_FE() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DE_FE)) = (0x00009494) #define DEF_MTX_RESPFRM_RATE_TABLE_DF_FF() (REG32(ADR_MTX_RESPFRM_RATE_TABLE_DF_FF)) = (0x00009494) #define DEF_MTX_RESPFRM_INFO_TABLE_EXCEPTION() (REG32(ADR_MTX_RESPFRM_INFO_TABLE_EXCEPTION)) = (0x0013a8f2) #define DEF_MTX_RESPFRM_INFO_00() (REG32(ADR_MTX_RESPFRM_INFO_00)) = (0x0013a8f2) #define DEF_MTX_RESPFRM_INFO_01() (REG32(ADR_MTX_RESPFRM_INFO_01)) = (0x001028f2) #define DEF_MTX_RESPFRM_INFO_02() (REG32(ADR_MTX_RESPFRM_INFO_02)) = (0x000df8f2) #define DEF_MTX_RESPFRM_INFO_03() (REG32(ADR_MTX_RESPFRM_INFO_03)) = (0x000d58f2) #define DEF_MTX_RESPFRM_INFO_11() (REG32(ADR_MTX_RESPFRM_INFO_11)) = (0x000a28f2) #define DEF_MTX_RESPFRM_INFO_12() (REG32(ADR_MTX_RESPFRM_INFO_12)) = (0x0007f8f2) #define DEF_MTX_RESPFRM_INFO_13() (REG32(ADR_MTX_RESPFRM_INFO_13)) = (0x000758f2) #define DEF_MTX_RESPFRM_INFO_90_B0() (REG32(ADR_MTX_RESPFRM_INFO_90_B0)) = (0x0003c8f2) #define DEF_MTX_RESPFRM_INFO_91_B1() (REG32(ADR_MTX_RESPFRM_INFO_91_B1)) = (0x000348f2) #define DEF_MTX_RESPFRM_INFO_92_B2() (REG32(ADR_MTX_RESPFRM_INFO_92_B2)) = (0x000308f2) #define DEF_MTX_RESPFRM_INFO_93_B3() (REG32(ADR_MTX_RESPFRM_INFO_93_B3)) = (0x0002c8f2) #define DEF_MTX_RESPFRM_INFO_94_B4() (REG32(ADR_MTX_RESPFRM_INFO_94_B4)) = (0x0002c8f2) #define DEF_MTX_RESPFRM_INFO_95_B5() (REG32(ADR_MTX_RESPFRM_INFO_95_B5)) = (0x000288f2) #define DEF_MTX_RESPFRM_INFO_96_B6() (REG32(ADR_MTX_RESPFRM_INFO_96_B6)) = (0x000288f2) #define DEF_MTX_RESPFRM_INFO_97_B7() (REG32(ADR_MTX_RESPFRM_INFO_97_B7)) = (0x000288f2) #define DEF_MTX_RESPFRM_INFO_C0() (REG32(ADR_MTX_RESPFRM_INFO_C0)) = (0x0004c8f2) #define DEF_MTX_RESPFRM_INFO_C1() (REG32(ADR_MTX_RESPFRM_INFO_C1)) = (0x000406a3) #define DEF_MTX_RESPFRM_INFO_C2() (REG32(ADR_MTX_RESPFRM_INFO_C2)) = (0x0003c5dd) #define DEF_MTX_RESPFRM_INFO_C3() (REG32(ADR_MTX_RESPFRM_INFO_C3)) = (0x0003c5da) #define DEF_MTX_RESPFRM_INFO_C4() (REG32(ADR_MTX_RESPFRM_INFO_C4)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_C5() (REG32(ADR_MTX_RESPFRM_INFO_C5)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_C6() (REG32(ADR_MTX_RESPFRM_INFO_C6)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_C7() (REG32(ADR_MTX_RESPFRM_INFO_C7)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_D0() (REG32(ADR_MTX_RESPFRM_INFO_D0)) = (0x0004c8ef) #define DEF_MTX_RESPFRM_INFO_D1() (REG32(ADR_MTX_RESPFRM_INFO_D1)) = (0x000406a3) #define DEF_MTX_RESPFRM_INFO_D2() (REG32(ADR_MTX_RESPFRM_INFO_D2)) = (0x0003c5dd) #define DEF_MTX_RESPFRM_INFO_D3() (REG32(ADR_MTX_RESPFRM_INFO_D3)) = (0x0003c5da) #define DEF_MTX_RESPFRM_INFO_D4() (REG32(ADR_MTX_RESPFRM_INFO_D4)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_D5() (REG32(ADR_MTX_RESPFRM_INFO_D5)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_D6() (REG32(ADR_MTX_RESPFRM_INFO_D6)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_D7() (REG32(ADR_MTX_RESPFRM_INFO_D7)) = (0x00038517) #define DEF_MTX_RESPFRM_INFO_D8() (REG32(ADR_MTX_RESPFRM_INFO_D8)) = (0x000408f2) #define DEF_MTX_RESPFRM_INFO_D9() (REG32(ADR_MTX_RESPFRM_INFO_D9)) = (0x000348f2) #define DEF_MTX_RESPFRM_INFO_DA() (REG32(ADR_MTX_RESPFRM_INFO_DA)) = (0x000308f2) #define DEF_MTX_RESPFRM_INFO_DB() (REG32(ADR_MTX_RESPFRM_INFO_DB)) = (0x000308f2) #define DEF_MTX_RESPFRM_INFO_DC() (REG32(ADR_MTX_RESPFRM_INFO_DC)) = (0x0002c8f2) #define DEF_MTX_RESPFRM_INFO_DD() (REG32(ADR_MTX_RESPFRM_INFO_DD)) = (0x0002c8f2) #define DEF_MTX_RESPFRM_INFO_DE() (REG32(ADR_MTX_RESPFRM_INFO_DE)) = (0x0002c8f2) #define DEF_MTX_RESPFRM_INFO_DF() (REG32(ADR_MTX_RESPFRM_INFO_DF)) = (0x0002c8f2) #define DEF_WSID0() (REG32(ADR_WSID0)) = (0x00000000) #define DEF_PEER_MAC0_0() (REG32(ADR_PEER_MAC0_0)) = (0x00000000) #define DEF_PEER_MAC0_1() (REG32(ADR_PEER_MAC0_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_0() (REG32(ADR_TX_ACK_POLICY_0_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_0() (REG32(ADR_TX_SEQ_CTRL_0_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_1() (REG32(ADR_TX_ACK_POLICY_0_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_1() (REG32(ADR_TX_SEQ_CTRL_0_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_2() (REG32(ADR_TX_ACK_POLICY_0_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_2() (REG32(ADR_TX_SEQ_CTRL_0_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_3() (REG32(ADR_TX_ACK_POLICY_0_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_3() (REG32(ADR_TX_SEQ_CTRL_0_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_4() (REG32(ADR_TX_ACK_POLICY_0_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_4() (REG32(ADR_TX_SEQ_CTRL_0_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_5() (REG32(ADR_TX_ACK_POLICY_0_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_5() (REG32(ADR_TX_SEQ_CTRL_0_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_6() (REG32(ADR_TX_ACK_POLICY_0_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_6() (REG32(ADR_TX_SEQ_CTRL_0_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_0_7() (REG32(ADR_TX_ACK_POLICY_0_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_0_7() (REG32(ADR_TX_SEQ_CTRL_0_7)) = (0x00000000) #define DEF_WSID1() (REG32(ADR_WSID1)) = (0x00000000) #define DEF_PEER_MAC1_0() (REG32(ADR_PEER_MAC1_0)) = (0x00000000) #define DEF_PEER_MAC1_1() (REG32(ADR_PEER_MAC1_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_0() (REG32(ADR_TX_ACK_POLICY_1_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_0() (REG32(ADR_TX_SEQ_CTRL_1_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_1() (REG32(ADR_TX_ACK_POLICY_1_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_1() (REG32(ADR_TX_SEQ_CTRL_1_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_2() (REG32(ADR_TX_ACK_POLICY_1_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_2() (REG32(ADR_TX_SEQ_CTRL_1_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_3() (REG32(ADR_TX_ACK_POLICY_1_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_3() (REG32(ADR_TX_SEQ_CTRL_1_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_4() (REG32(ADR_TX_ACK_POLICY_1_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_4() (REG32(ADR_TX_SEQ_CTRL_1_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_5() (REG32(ADR_TX_ACK_POLICY_1_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_5() (REG32(ADR_TX_SEQ_CTRL_1_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_6() (REG32(ADR_TX_ACK_POLICY_1_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_6() (REG32(ADR_TX_SEQ_CTRL_1_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_1_7() (REG32(ADR_TX_ACK_POLICY_1_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_1_7() (REG32(ADR_TX_SEQ_CTRL_1_7)) = (0x00000000) #define DEF_PACKET_ID_ALLOCATION_PRIORITY() (REG32(ADR_PACKET_ID_ALLOCATION_PRIORITY)) = (0x00000000) #define DEF_MAC_MODE() (REG32(ADR_MAC_MODE)) = (0x00000000) #define DEF_ALL_SOFTWARE_RESET() (REG32(ADR_ALL_SOFTWARE_RESET)) = (0x00000000) #define DEF_ENG_SOFTWARE_RESET() (REG32(ADR_ENG_SOFTWARE_RESET)) = (0x00000000) #define DEF_CSR_SOFTWARE_RESET() (REG32(ADR_CSR_SOFTWARE_RESET)) = (0x00000000) #define DEF_MAC_CLOCK_ENABLE() (REG32(ADR_MAC_CLOCK_ENABLE)) = (0x00003efb) #define DEF_MAC_ENGINE_CLOCK_ENABLE() (REG32(ADR_MAC_ENGINE_CLOCK_ENABLE)) = (0x0000f07b) #define DEF_MAC_CSR_CLOCK_ENABLE() (REG32(ADR_MAC_CSR_CLOCK_ENABLE)) = (0x0000ec02) #define DEF_GLBLE_SET() (REG32(ADR_GLBLE_SET)) = (0x000e5000) #define DEF_REASON_TRAP0() (REG32(ADR_REASON_TRAP0)) = (0x00000000) #define DEF_REASON_TRAP1() (REG32(ADR_REASON_TRAP1)) = (0x00000000) #define DEF_BSSID_0() (REG32(ADR_BSSID_0)) = (0x00000000) #define DEF_BSSID_1() (REG32(ADR_BSSID_1)) = (0x00000000) #define DEF_STA_MAC_0() (REG32(ADR_STA_MAC_0)) = (0x00000000) #define DEF_STA_MAC_1() (REG32(ADR_STA_MAC_1)) = (0x00000000) #define DEF_SCRT_SET() (REG32(ADR_SCRT_SET)) = (0x00000000) #define DEF_SCRT_STATE() (REG32(ADR_SCRT_STATE)) = (0x00000000) #define DEF_BSSID1_0() (REG32(ADR_BSSID1_0)) = (0x00000000) #define DEF_BSSID1_1() (REG32(ADR_BSSID1_1)) = (0x00000000) #define DEF_STA_MAC1_0() (REG32(ADR_STA_MAC1_0)) = (0x00000000) #define DEF_STA_MAC1_1() (REG32(ADR_STA_MAC1_1)) = (0x00000000) #define DEF_OP_MODE1() (REG32(ADR_OP_MODE1)) = (0x00000000) #define DEF_BTCX0() (REG32(ADR_BTCX0)) = (0x00000006) #define DEF_BTCX1() (REG32(ADR_BTCX1)) = (0x00000000) #define DEF_SWITCH_CTL() (REG32(ADR_SWITCH_CTL)) = (0x00000000) #define DEF_RANDOM_CTL() (REG32(ADR_RANDOM_CTL)) = (0x00000000) #define DEF_BTCX_MISC_CTL() (REG32(ADR_BTCX_MISC_CTL)) = (0x0000005f) #define DEF_MIB_EN() (REG32(ADR_MIB_EN)) = (0x00000000) #define DEF_MTX_WSID0_SUCC() (REG32(ADR_MTX_WSID0_SUCC)) = (0x00000000) #define DEF_MTX_WSID0_FRM() (REG32(ADR_MTX_WSID0_FRM)) = (0x00000000) #define DEF_MTX_WSID0_RETRY() (REG32(ADR_MTX_WSID0_RETRY)) = (0x00000000) #define DEF_MTX_WSID0_TOTAL() (REG32(ADR_MTX_WSID0_TOTAL)) = (0x00000000) #define DEF_MTX_GROUP() (REG32(ADR_MTX_GROUP)) = (0x00000000) #define DEF_MTX_FAIL() (REG32(ADR_MTX_FAIL)) = (0x00000000) #define DEF_MTX_RETRY() (REG32(ADR_MTX_RETRY)) = (0x00000000) #define DEF_MTX_MULTI_RETRY() (REG32(ADR_MTX_MULTI_RETRY)) = (0x00000000) #define DEF_MTX_RTS_SUCCESS() (REG32(ADR_MTX_RTS_SUCCESS)) = (0x00000000) #define DEF_MTX_RTS_FAIL() (REG32(ADR_MTX_RTS_FAIL)) = (0x00000000) #define DEF_MTX_ACK_FAIL() (REG32(ADR_MTX_ACK_FAIL)) = (0x00000000) #define DEF_MTX_FRM() (REG32(ADR_MTX_FRM)) = (0x00000000) #define DEF_MTX_ACK_TX() (REG32(ADR_MTX_ACK_TX)) = (0x00000000) #define DEF_MTX_CTS_TX() (REG32(ADR_MTX_CTS_TX)) = (0x00000000) #define DEF_MRX_DUP_FRM() (REG32(ADR_MRX_DUP_FRM)) = (0x00000000) #define DEF_MRX_FRG_FRM() (REG32(ADR_MRX_FRG_FRM)) = (0x00000000) #define DEF_MRX_GROUP_FRM() (REG32(ADR_MRX_GROUP_FRM)) = (0x00000000) #define DEF_MRX_FCS_ERR() (REG32(ADR_MRX_FCS_ERR)) = (0x00000000) #define DEF_MRX_FCS_SUCC() (REG32(ADR_MRX_FCS_SUCC)) = (0x00000000) #define DEF_MRX_MISS() (REG32(ADR_MRX_MISS)) = (0x00000000) #define DEF_MRX_ALC_FAIL() (REG32(ADR_MRX_ALC_FAIL)) = (0x00000000) #define DEF_MRX_DAT_NTF() (REG32(ADR_MRX_DAT_NTF)) = (0x00000000) #define DEF_MRX_RTS_NTF() (REG32(ADR_MRX_RTS_NTF)) = (0x00000000) #define DEF_MRX_CTS_NTF() (REG32(ADR_MRX_CTS_NTF)) = (0x00000000) #define DEF_MRX_ACK_NTF() (REG32(ADR_MRX_ACK_NTF)) = (0x00000000) #define DEF_MRX_BA_NTF() (REG32(ADR_MRX_BA_NTF)) = (0x00000000) #define DEF_MRX_DATA_NTF() (REG32(ADR_MRX_DATA_NTF)) = (0x00000000) #define DEF_MRX_MNG_NTF() (REG32(ADR_MRX_MNG_NTF)) = (0x00000000) #define DEF_MRX_DAT_CRC_NTF() (REG32(ADR_MRX_DAT_CRC_NTF)) = (0x00000000) #define DEF_MRX_BAR_NTF() (REG32(ADR_MRX_BAR_NTF)) = (0x00000000) #define DEF_MRX_MB_MISS() (REG32(ADR_MRX_MB_MISS)) = (0x00000000) #define DEF_MRX_NIDLE_MISS() (REG32(ADR_MRX_NIDLE_MISS)) = (0x00000000) #define DEF_MRX_CSR_NTF() (REG32(ADR_MRX_CSR_NTF)) = (0x00000000) #define DEF_DBG_Q0_FRM_SUCCESS() (REG32(ADR_DBG_Q0_FRM_SUCCESS)) = (0x00000000) #define DEF_DBG_Q0_FRM_FAIL() (REG32(ADR_DBG_Q0_FRM_FAIL)) = (0x00000000) #define DEF_DBG_Q0_ACK_SUCCESS() (REG32(ADR_DBG_Q0_ACK_SUCCESS)) = (0x00000000) #define DEF_DBG_Q0_ACK_FAIL() (REG32(ADR_DBG_Q0_ACK_FAIL)) = (0x00000000) #define DEF_DBG_Q1_FRM_SUCCESS() (REG32(ADR_DBG_Q1_FRM_SUCCESS)) = (0x00000000) #define DEF_DBG_Q1_FRM_FAIL() (REG32(ADR_DBG_Q1_FRM_FAIL)) = (0x00000000) #define DEF_DBG_Q1_ACK_SUCCESS() (REG32(ADR_DBG_Q1_ACK_SUCCESS)) = (0x00000000) #define DEF_DBG_Q1_ACK_FAIL() (REG32(ADR_DBG_Q1_ACK_FAIL)) = (0x00000000) #define DEF_DBG_Q2_FRM_SUCCESS() (REG32(ADR_DBG_Q2_FRM_SUCCESS)) = (0x00000000) #define DEF_DBG_Q2_FRM_FAIL() (REG32(ADR_DBG_Q2_FRM_FAIL)) = (0x00000000) #define DEF_DBG_Q2_ACK_SUCCESS() (REG32(ADR_DBG_Q2_ACK_SUCCESS)) = (0x00000000) #define DEF_DBG_Q2_ACK_FAIL() (REG32(ADR_DBG_Q2_ACK_FAIL)) = (0x00000000) #define DEF_DBG_Q3_FRM_SUCCESS() (REG32(ADR_DBG_Q3_FRM_SUCCESS)) = (0x00000000) #define DEF_DBG_Q3_FRM_FAIL() (REG32(ADR_DBG_Q3_FRM_FAIL)) = (0x00000000) #define DEF_DBG_Q3_ACK_SUCCESS() (REG32(ADR_DBG_Q3_ACK_SUCCESS)) = (0x00000000) #define DEF_DBG_Q3_ACK_FAIL() (REG32(ADR_DBG_Q3_ACK_FAIL)) = (0x00000000) #define DEF_MIB_SCRT_TKIP0() (REG32(ADR_MIB_SCRT_TKIP0)) = (0x00000000) #define DEF_MIB_SCRT_TKIP1() (REG32(ADR_MIB_SCRT_TKIP1)) = (0x00000000) #define DEF_MIB_SCRT_TKIP2() (REG32(ADR_MIB_SCRT_TKIP2)) = (0x00000000) #define DEF_MIB_SCRT_CCMP0() (REG32(ADR_MIB_SCRT_CCMP0)) = (0x00000000) #define DEF_MIB_SCRT_CCMP1() (REG32(ADR_MIB_SCRT_CCMP1)) = (0x00000000) #define DEF_DBG_LEN_CRC_FAIL() (REG32(ADR_DBG_LEN_CRC_FAIL)) = (0x00000000) #define DEF_DBG_LEN_ALC_FAIL() (REG32(ADR_DBG_LEN_ALC_FAIL)) = (0x00000000) #define DEF_DBG_AMPDU_PASS() (REG32(ADR_DBG_AMPDU_PASS)) = (0x00000000) #define DEF_DBG_AMPDU_FAIL() (REG32(ADR_DBG_AMPDU_FAIL)) = (0x00000000) #define DEF_ID_ALC_FAIL1() (REG32(ADR_ID_ALC_FAIL1)) = (0x00000000) #define DEF_ID_ALC_FAIL2() (REG32(ADR_ID_ALC_FAIL2)) = (0x00000000) #define DEF_WSID2() (REG32(ADR_WSID2)) = (0x00000000) #define DEF_PEER_MAC2_0() (REG32(ADR_PEER_MAC2_0)) = (0x00000000) #define DEF_PEER_MAC2_1() (REG32(ADR_PEER_MAC2_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_0() (REG32(ADR_TX_ACK_POLICY_2_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_0() (REG32(ADR_TX_SEQ_CTRL_2_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_1() (REG32(ADR_TX_ACK_POLICY_2_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_1() (REG32(ADR_TX_SEQ_CTRL_2_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_2() (REG32(ADR_TX_ACK_POLICY_2_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_2() (REG32(ADR_TX_SEQ_CTRL_2_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_3() (REG32(ADR_TX_ACK_POLICY_2_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_3() (REG32(ADR_TX_SEQ_CTRL_2_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_4() (REG32(ADR_TX_ACK_POLICY_2_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_4() (REG32(ADR_TX_SEQ_CTRL_2_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_5() (REG32(ADR_TX_ACK_POLICY_2_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_5() (REG32(ADR_TX_SEQ_CTRL_2_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_6() (REG32(ADR_TX_ACK_POLICY_2_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_6() (REG32(ADR_TX_SEQ_CTRL_2_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_2_7() (REG32(ADR_TX_ACK_POLICY_2_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_2_7() (REG32(ADR_TX_SEQ_CTRL_2_7)) = (0x00000000) #define DEF_WSID3() (REG32(ADR_WSID3)) = (0x00000000) #define DEF_PEER_MAC3_0() (REG32(ADR_PEER_MAC3_0)) = (0x00000000) #define DEF_PEER_MAC3_1() (REG32(ADR_PEER_MAC3_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_0() (REG32(ADR_TX_ACK_POLICY_3_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_0() (REG32(ADR_TX_SEQ_CTRL_3_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_1() (REG32(ADR_TX_ACK_POLICY_3_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_1() (REG32(ADR_TX_SEQ_CTRL_3_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_2() (REG32(ADR_TX_ACK_POLICY_3_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_2() (REG32(ADR_TX_SEQ_CTRL_3_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_3() (REG32(ADR_TX_ACK_POLICY_3_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_3() (REG32(ADR_TX_SEQ_CTRL_3_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_4() (REG32(ADR_TX_ACK_POLICY_3_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_4() (REG32(ADR_TX_SEQ_CTRL_3_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_5() (REG32(ADR_TX_ACK_POLICY_3_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_5() (REG32(ADR_TX_SEQ_CTRL_3_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_6() (REG32(ADR_TX_ACK_POLICY_3_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_6() (REG32(ADR_TX_SEQ_CTRL_3_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_3_7() (REG32(ADR_TX_ACK_POLICY_3_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_3_7() (REG32(ADR_TX_SEQ_CTRL_3_7)) = (0x00000000) #define DEF_WSID4() (REG32(ADR_WSID4)) = (0x00000000) #define DEF_PEER_MAC4_0() (REG32(ADR_PEER_MAC4_0)) = (0x00000000) #define DEF_PEER_MAC4_1() (REG32(ADR_PEER_MAC4_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_0() (REG32(ADR_TX_ACK_POLICY_4_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_0() (REG32(ADR_TX_SEQ_CTRL_4_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_1() (REG32(ADR_TX_ACK_POLICY_4_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_1() (REG32(ADR_TX_SEQ_CTRL_4_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_2() (REG32(ADR_TX_ACK_POLICY_4_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_2() (REG32(ADR_TX_SEQ_CTRL_4_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_3() (REG32(ADR_TX_ACK_POLICY_4_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_3() (REG32(ADR_TX_SEQ_CTRL_4_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_4() (REG32(ADR_TX_ACK_POLICY_4_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_4() (REG32(ADR_TX_SEQ_CTRL_4_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_5() (REG32(ADR_TX_ACK_POLICY_4_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_5() (REG32(ADR_TX_SEQ_CTRL_4_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_6() (REG32(ADR_TX_ACK_POLICY_4_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_6() (REG32(ADR_TX_SEQ_CTRL_4_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_4_7() (REG32(ADR_TX_ACK_POLICY_4_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_4_7() (REG32(ADR_TX_SEQ_CTRL_4_7)) = (0x00000000) #define DEF_WSID5() (REG32(ADR_WSID5)) = (0x00000000) #define DEF_PEER_MAC5_0() (REG32(ADR_PEER_MAC5_0)) = (0x00000000) #define DEF_PEER_MAC5_1() (REG32(ADR_PEER_MAC5_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_0() (REG32(ADR_TX_ACK_POLICY_5_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_0() (REG32(ADR_TX_SEQ_CTRL_5_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_1() (REG32(ADR_TX_ACK_POLICY_5_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_1() (REG32(ADR_TX_SEQ_CTRL_5_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_2() (REG32(ADR_TX_ACK_POLICY_5_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_2() (REG32(ADR_TX_SEQ_CTRL_5_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_3() (REG32(ADR_TX_ACK_POLICY_5_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_3() (REG32(ADR_TX_SEQ_CTRL_5_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_4() (REG32(ADR_TX_ACK_POLICY_5_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_4() (REG32(ADR_TX_SEQ_CTRL_5_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_5() (REG32(ADR_TX_ACK_POLICY_5_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_5() (REG32(ADR_TX_SEQ_CTRL_5_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_6() (REG32(ADR_TX_ACK_POLICY_5_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_6() (REG32(ADR_TX_SEQ_CTRL_5_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_5_7() (REG32(ADR_TX_ACK_POLICY_5_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_5_7() (REG32(ADR_TX_SEQ_CTRL_5_7)) = (0x00000000) #define DEF_WSID6() (REG32(ADR_WSID6)) = (0x00000000) #define DEF_PEER_MAC6_0() (REG32(ADR_PEER_MAC6_0)) = (0x00000000) #define DEF_PEER_MAC6_1() (REG32(ADR_PEER_MAC6_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_0() (REG32(ADR_TX_ACK_POLICY_6_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_0() (REG32(ADR_TX_SEQ_CTRL_6_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_1() (REG32(ADR_TX_ACK_POLICY_6_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_1() (REG32(ADR_TX_SEQ_CTRL_6_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_2() (REG32(ADR_TX_ACK_POLICY_6_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_2() (REG32(ADR_TX_SEQ_CTRL_6_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_3() (REG32(ADR_TX_ACK_POLICY_6_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_3() (REG32(ADR_TX_SEQ_CTRL_6_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_4() (REG32(ADR_TX_ACK_POLICY_6_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_4() (REG32(ADR_TX_SEQ_CTRL_6_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_5() (REG32(ADR_TX_ACK_POLICY_6_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_5() (REG32(ADR_TX_SEQ_CTRL_6_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_6() (REG32(ADR_TX_ACK_POLICY_6_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_6() (REG32(ADR_TX_SEQ_CTRL_6_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_6_7() (REG32(ADR_TX_ACK_POLICY_6_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_6_7() (REG32(ADR_TX_SEQ_CTRL_6_7)) = (0x00000000) #define DEF_WSID7() (REG32(ADR_WSID7)) = (0x00000000) #define DEF_PEER_MAC7_0() (REG32(ADR_PEER_MAC7_0)) = (0x00000000) #define DEF_PEER_MAC7_1() (REG32(ADR_PEER_MAC7_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_0() (REG32(ADR_TX_ACK_POLICY_7_0)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_0() (REG32(ADR_TX_SEQ_CTRL_7_0)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_1() (REG32(ADR_TX_ACK_POLICY_7_1)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_1() (REG32(ADR_TX_SEQ_CTRL_7_1)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_2() (REG32(ADR_TX_ACK_POLICY_7_2)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_2() (REG32(ADR_TX_SEQ_CTRL_7_2)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_3() (REG32(ADR_TX_ACK_POLICY_7_3)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_3() (REG32(ADR_TX_SEQ_CTRL_7_3)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_4() (REG32(ADR_TX_ACK_POLICY_7_4)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_4() (REG32(ADR_TX_SEQ_CTRL_7_4)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_5() (REG32(ADR_TX_ACK_POLICY_7_5)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_5() (REG32(ADR_TX_SEQ_CTRL_7_5)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_6() (REG32(ADR_TX_ACK_POLICY_7_6)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_6() (REG32(ADR_TX_SEQ_CTRL_7_6)) = (0x00000000) #define DEF_TX_ACK_POLICY_7_7() (REG32(ADR_TX_ACK_POLICY_7_7)) = (0x00000000) #define DEF_TX_SEQ_CTRL_7_7() (REG32(ADR_TX_SEQ_CTRL_7_7)) = (0x00000000) #define DEF_GEMINIA_3_WIRE_REGISTER() (REG32(ADR_GEMINIA_3_WIRE_REGISTER)) = (0x06000120) #define DEF_GEMINIA_MANUAL_ENABLE_REGISTER() (REG32(ADR_GEMINIA_MANUAL_ENABLE_REGISTER)) = (0x2aaaaaaa) #define DEF_GEMINIA_CALIBRATION_TEST_REGISTER() (REG32(ADR_GEMINIA_CALIBRATION_TEST_REGISTER)) = (0x0000aa9f) #define DEF_GEMINIA_LDO_REGISTER() (REG32(ADR_GEMINIA_LDO_REGISTER)) = (0x24824924) #define DEF_GEMINIA_WIFI_RX_FILTER_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FILTER_REGISTER)) = (0x271556db) #define DEF_GEMINIA_BT_RX_FILTER_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FILTER_REGISTER)) = (0x26d556db) #define DEF_GEMINIA_RX_REGISTER() (REG32(ADR_GEMINIA_RX_REGISTER)) = (0x604aea08) #define DEF_GEMINIA_WBT_TX_FE_REGISTER() (REG32(ADR_GEMINIA_WBT_TX_FE_REGISTER)) = (0x00003e7e) #define DEF_GEMINIA_WBT_TX_PA_REGISTER() (REG32(ADR_GEMINIA_WBT_TX_PA_REGISTER)) = (0x37744497) #define DEF_GEMINIA_TX_REGISTER() (REG32(ADR_GEMINIA_TX_REGISTER)) = (0x2600a13f) #define DEF_GEMINIA_WIFI_RX_FE_HG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_HG_REGISTER)) = (0xaf910e93) #define DEF_GEMINIA_WIFI_RX_FE_MG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_MG_REGISTER)) = (0xaf910e92) #define DEF_GEMINIA_WIFI_RX_FE_LG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_LG_REGISTER)) = (0xaf918001) #define DEF_GEMINIA_WIFI_RX_FE_ULG_REGISTER() (REG32(ADR_GEMINIA_WIFI_RX_FE_ULG_REGISTER)) = (0xaf938004) #define DEF_GEMINIA_BT_RX_FE_HG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_HG_REGISTER)) = (0x97910643) #define DEF_GEMINIA_BT_RX_FE_MG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_MG_REGISTER)) = (0x97910642) #define DEF_GEMINIA_BT_RX_FE_LG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_LG_REGISTER)) = (0x97918001) #define DEF_GEMINIA_BT_RX_FE_ULG_REGISTER() (REG32(ADR_GEMINIA_BT_RX_FE_ULG_REGISTER)) = (0x97938004) #define DEF_GEMINIA_RX_ADC_REGISTER() (REG32(ADR_GEMINIA_RX_ADC_REGISTER)) = (0x83050502) #define DEF_GEMINIA_WIFI_TX_DAC_REGISTER() (REG32(ADR_GEMINIA_WIFI_TX_DAC_REGISTER)) = (0x08804355) #define DEF_GEMINIA_BT_TX_DAC_REGISTER() (REG32(ADR_GEMINIA_BT_TX_DAC_REGISTER)) = (0x08800755) #define DEF_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER() (REG32(ADR_GEMINIA_SX_ENABLE_REGISTER_TOP_CONTROLLER)) = (0x802aa2aa) #define DEF_GEMINIA_SX_LDO_REGISTER() (REG32(ADR_GEMINIA_SX_LDO_REGISTER)) = (0x2aa0021e) #define DEF_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_GEMINIA_SYN_FRACTIONAL_AND_INTEGER_8BITS)) = (0x5f800000) #define DEF_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE() (REG32(ADR_GEMINIA_SYN_REGISTER_INT3BIT_CH_TABLE)) = (0x000043c0) #define DEF_GEMINIA_SYN_PFD_CHP_() (REG32(ADR_GEMINIA_SYN_PFD_CHP_)) = (0x01c00606) #define DEF_GEMINIA_SYN_LPF() (REG32(ADR_GEMINIA_SYN_LPF)) = (0x2c4293d6) #define DEF_GEMINIA_SYN_VCO() (REG32(ADR_GEMINIA_SYN_VCO)) = (0x002220a8) #define DEF_GEMINIA_SYN_VCOBF() (REG32(ADR_GEMINIA_SYN_VCOBF)) = (0x04015445) #define DEF_GEMINIA_SYN_DIV_SDM() (REG32(ADR_GEMINIA_SYN_DIV_SDM)) = (0x001e0077) #define DEF_GEMINIA_SYN_SBCAL() (REG32(ADR_GEMINIA_SYN_SBCAL)) = (0x30700400) #define DEF_GEMINIA_SYN_AAC() (REG32(ADR_GEMINIA_SYN_AAC)) = (0x0517cd06) #define DEF_GEMINIA_SYN_TTL() (REG32(ADR_GEMINIA_SYN_TTL)) = (0x00018495) #define DEF_GEMINIA_DPLL_TOP_REGISTER() (REG32(ADR_GEMINIA_DPLL_TOP_REGISTER)) = (0x00180f20) #define DEF_GEMINIA_DPLL_CKT_REGISTER() (REG32(ADR_GEMINIA_DPLL_CKT_REGISTER)) = (0x041c89ac) #define DEF_GEMINIA_DPLL_FB_DIVISION_REGISTERS() (REG32(ADR_GEMINIA_DPLL_FB_DIVISION_REGISTERS)) = (0x24ec2ec5) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER1() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER2() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER3() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER4() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER5() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER6() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER7() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER8() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER9() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER10() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER11() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER12() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER13() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER14() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER15() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER16() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER17() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER17)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER18() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER18)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER19() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER19)) = (0x00002020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER20() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER20)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER21() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER21)) = (0x20202020) #define DEF_GEMINIA_WF_DCOC_IDAC_REGISTER22() (REG32(ADR_GEMINIA_WF_DCOC_IDAC_REGISTER22)) = (0x00002020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER1() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER2() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER3() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER4() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER5() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER6() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER7() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER8() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER9() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER10() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER11() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER12() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER13() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER14() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER15() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_GEMINIA_BT_DCOC_IDAC_REGISTER16() (REG32(ADR_GEMINIA_BT_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_GEMINIA_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_GEMINIA_MODE_DECODER_TIMER_REGISTER1)) = (0x00000008) #define DEF_GEMINIA_WIFI_T2R_TIMER_REGISTER() (REG32(ADR_GEMINIA_WIFI_T2R_TIMER_REGISTER)) = (0x02000100) #define DEF_GEMINIA_WIFI_R2T_TIMER_REGISTER() (REG32(ADR_GEMINIA_WIFI_R2T_TIMER_REGISTER)) = (0x00010101) #define DEF_GEMINIA_CALIBRATION_TIMER_REGISTER() (REG32(ADR_GEMINIA_CALIBRATION_TIMER_REGISTER)) = (0x00222222) #define DEF_GEMINIA_CALIBRATION_GAIN_REGISTER0() (REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER0)) = (0x00000000) #define DEF_GEMINIA_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_GEMINIA_CALIBRATION_GAIN_REGISTER1)) = (0x00000000) #define DEF_GEMINIA_TRX_DUMMY_REGISTER() (REG32(ADR_GEMINIA_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_GEMINIA_SX_DUMMY_REGISTER() (REG32(ADR_GEMINIA_SX_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_GEMINIA_READ_ONLY_FLAGS_ADC() (REG32(ADR_GEMINIA_READ_ONLY_FLAGS_ADC)) = (0x00000000) #define DEF_GEMINIA_READ_ONLY_FLAGS_SX1() (REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX1)) = (0x00000000) #define DEF_GEMINIA_READ_ONLY_FLAGS_SX2() (REG32(ADR_GEMINIA_READ_ONLY_FLAGS_SX2)) = (0x00000000) #define DEF_GEMINIA_DIGITAL_ADD_ON_R0() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R0)) = (0x00000000) #define DEF_GEMINIA_DIGITAL_ADD_ON_R1() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R1)) = (0x000000aa) #define DEF_GEMINIA_DIGITAL_ADD_ON_R2() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R2)) = (0x80000000) #define DEF_GEMINIA_DIGITAL_ADD_ON_R3() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R3)) = (0x00000000) #define DEF_GEMINIA_DIGITAL_ADD_ON_R4() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R4)) = (0x01000000) #define DEF_GEMINIA_DIGITAL_ADD_ON_R5() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R5)) = (0x00000000) #define DEF_GEMINIA_DIGITAL_ADD_ON_R6() (REG32(ADR_GEMINIA_DIGITAL_ADD_ON_R6)) = (0x00000000) #define DEF_GEMINIA_TX_UP8X_COEF_R0() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R0)) = (0x1ff00000) #define DEF_GEMINIA_TX_UP8X_COEF_R1() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R1)) = (0x00290000) #define DEF_GEMINIA_TX_UP8X_COEF_R2() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R2)) = (0x1fa60000) #define DEF_GEMINIA_TX_UP8X_COEF_R3() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R3)) = (0x00b70000) #define DEF_GEMINIA_TX_UP8X_COEF_R4() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R4)) = (0x1e800000) #define DEF_GEMINIA_TX_UP8X_COEF_R5() (REG32(ADR_GEMINIA_TX_UP8X_COEF_R5)) = (0x05060800) #define DEF_GEMINIA_RF_D_CAL_TOP_R0() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R0)) = (0x00000000) #define DEF_GEMINIA_RF_D_CAL_TOP_R1() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R1)) = (0x000000e5) #define DEF_GEMINIA_RF_D_CAL_TOP_R2() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R2)) = (0x08003800) #define DEF_GEMINIA_RF_D_CAL_TOP_R3() (REG32(ADR_GEMINIA_RF_D_CAL_TOP_R3)) = (0x03330333) #define DEF_GEMINIA_PMU_REG_1() (REG32(ADR_GEMINIA_PMU_REG_1)) = (0x01701012) #define DEF_GEMINIA_PMU_REG_2() (REG32(ADR_GEMINIA_PMU_REG_2)) = (0x251a8800) #define DEF_GEMINIA_PMU_REG_3() (REG32(ADR_GEMINIA_PMU_REG_3)) = (0x02604170) #define DEF_GEMINIA_PMU_REG_4() (REG32(ADR_GEMINIA_PMU_REG_4)) = (0x95d98900) #define DEF_GEMINIA_PMU_REG_5() (REG32(ADR_GEMINIA_PMU_REG_5)) = (0x0002aaa8) #define DEF_GEMINIA_PMU_REG_6() (REG32(ADR_GEMINIA_PMU_REG_6)) = (0x00000000) #define DEF_GEMINIA_PMU_BT_CLK() (REG32(ADR_GEMINIA_PMU_BT_CLK)) = (0x00000000) #define DEF_GEMINIA_PMU_SLEEP_REG() (REG32(ADR_GEMINIA_PMU_SLEEP_REG)) = (0x00000040) #define DEF_GEMINIA_PMU_RTC_REG_0() (REG32(ADR_GEMINIA_PMU_RTC_REG_0)) = (0x00000000) #define DEF_GEMINIA_PMU_RTC_REG_1() (REG32(ADR_GEMINIA_PMU_RTC_REG_1)) = (0x00000003) #define DEF_GEMINIA_PMU_RTC_REG_2() (REG32(ADR_GEMINIA_PMU_RTC_REG_2)) = (0x00000000) #define DEF_GEMINIA_PMU_RTC_REG_3() (REG32(ADR_GEMINIA_PMU_RTC_REG_3)) = (0x00000000) #define DEF_GEMINIA_PMU_FDB_REG_0() (REG32(ADR_GEMINIA_PMU_FDB_REG_0)) = (0x00000000) #define DEF_GEMINIA_IO_REG_0() (REG32(ADR_GEMINIA_IO_REG_0)) = (0x20022222) #define DEF_GEMINIA_IO_REG_1() (REG32(ADR_GEMINIA_IO_REG_1)) = (0x22222222) #define DEF_GEMINIA_IO_REG_2() (REG32(ADR_GEMINIA_IO_REG_2)) = (0x22222222) #define DEF_GEMINIA_MCU_REG_0() (REG32(ADR_GEMINIA_MCU_REG_0)) = (0x00003000) #define DEF_GEMINIA_PMU_RAM_00() (REG32(ADR_GEMINIA_PMU_RAM_00)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_01() (REG32(ADR_GEMINIA_PMU_RAM_01)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_02() (REG32(ADR_GEMINIA_PMU_RAM_02)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_03() (REG32(ADR_GEMINIA_PMU_RAM_03)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_04() (REG32(ADR_GEMINIA_PMU_RAM_04)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_05() (REG32(ADR_GEMINIA_PMU_RAM_05)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_06() (REG32(ADR_GEMINIA_PMU_RAM_06)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_07() (REG32(ADR_GEMINIA_PMU_RAM_07)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_08() (REG32(ADR_GEMINIA_PMU_RAM_08)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_09() (REG32(ADR_GEMINIA_PMU_RAM_09)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_10() (REG32(ADR_GEMINIA_PMU_RAM_10)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_11() (REG32(ADR_GEMINIA_PMU_RAM_11)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_12() (REG32(ADR_GEMINIA_PMU_RAM_12)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_13() (REG32(ADR_GEMINIA_PMU_RAM_13)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_14() (REG32(ADR_GEMINIA_PMU_RAM_14)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_15() (REG32(ADR_GEMINIA_PMU_RAM_15)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_16() (REG32(ADR_GEMINIA_PMU_RAM_16)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_17() (REG32(ADR_GEMINIA_PMU_RAM_17)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_18() (REG32(ADR_GEMINIA_PMU_RAM_18)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_19() (REG32(ADR_GEMINIA_PMU_RAM_19)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_20() (REG32(ADR_GEMINIA_PMU_RAM_20)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_21() (REG32(ADR_GEMINIA_PMU_RAM_21)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_22() (REG32(ADR_GEMINIA_PMU_RAM_22)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_23() (REG32(ADR_GEMINIA_PMU_RAM_23)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_24() (REG32(ADR_GEMINIA_PMU_RAM_24)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_25() (REG32(ADR_GEMINIA_PMU_RAM_25)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_26() (REG32(ADR_GEMINIA_PMU_RAM_26)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_27() (REG32(ADR_GEMINIA_PMU_RAM_27)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_28() (REG32(ADR_GEMINIA_PMU_RAM_28)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_29() (REG32(ADR_GEMINIA_PMU_RAM_29)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_30() (REG32(ADR_GEMINIA_PMU_RAM_30)) = (0x00000000) #define DEF_GEMINIA_PMU_RAM_31() (REG32(ADR_GEMINIA_PMU_RAM_31)) = (0x00000000) #define DEF_TURISMO_TRX_MODE_REGISTER() (REG32(ADR_TURISMO_TRX_MODE_REGISTER)) = (0x06000040) #define DEF_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aaaaaaa) #define DEF_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_CALIBRATION__AMP__TEST_REGISTER)) = (0x20001557) #define DEF_TURISMO_TRX_2_4G_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_LDO_REGISTER)) = (0x44444444) #define DEF_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_HT20_RX_FILTER_REGISTER)) = (0x4331551b) #define DEF_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_HT40_RX_FILTER_REGISTER)) = (0x4332550d) #define DEF_TURISMO_TRX_BT_RX_FILTER_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FILTER_REGISTER)) = (0x431d551b) #define DEF_TURISMO_TRX_2_4G_RX_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_REGISTER)) = (0x604aea48) #define DEF_TURISMO_TRX_2_4G_TX_FE_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TX_FE_REGISTER)) = (0x0607e0be) #define DEF_TURISMO_TRX_2_4G_TX_PA_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TX_PA_REGISTER)) = (0x97044497) #define DEF_TURISMO_TRX_2_4G_TX_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TX_REGISTER)) = (0x2a00a13f) #define DEF_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_HG_REGISTER)) = (0x97c10e93) #define DEF_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_MG_REGISTER)) = (0x97c10e92) #define DEF_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_LG_REGISTER)) = (0x97c18001) #define DEF_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_RX_FE_ULG_REGISTER)) = (0x97c38004) #define DEF_TURISMO_TRX_BT_RX_FE_HG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_HG_REGISTER)) = (0x88210643) #define DEF_TURISMO_TRX_BT_RX_FE_MG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_MG_REGISTER)) = (0x88210642) #define DEF_TURISMO_TRX_BT_RX_FE_LG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_LG_REGISTER)) = (0x88212001) #define DEF_TURISMO_TRX_BT_RX_FE_ULG_REGISTER() (REG32(ADR_TURISMO_TRX_BT_RX_FE_ULG_REGISTER)) = (0x88232004) #define DEF_TURISMO_TRX_WBT_RX_ADC_REGISTER() (REG32(ADR_TURISMO_TRX_WBT_RX_ADC_REGISTER)) = (0x83050502) #define DEF_TURISMO_TRX_WIFI_TX_DAC_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_TX_DAC_REGISTER)) = (0x08804355) #define DEF_TURISMO_TRX_BT_TX_DAC_REGISTER() (REG32(ADR_TURISMO_TRX_BT_TX_DAC_REGISTER)) = (0x08800755) #define DEF_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER() (REG32(ADR_TURISMO_TRX_SX_ENABLE_REGISTER_TOP_CONTROLLER)) = (0x802aa2aa) #define DEF_TURISMO_TRX_SX_2_4G_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_SX_2_4G_LDO_REGISTER)) = (0x2aa0021e) #define DEF_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_TURISMO_TRX_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x5f800000) #define DEF_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_TURISMO_TRX_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x000043c0) #define DEF_TURISMO_TRX_SX_2_4GB_PFD_CHP_() (REG32(ADR_TURISMO_TRX_SX_2_4GB_PFD_CHP_)) = (0x05c00606) #define DEF_TURISMO_TRX_SX_2_4GB_LPF() (REG32(ADR_TURISMO_TRX_SX_2_4GB_LPF)) = (0x2c4293d6) #define DEF_TURISMO_TRX_SX_2_4GB_VCO() (REG32(ADR_TURISMO_TRX_SX_2_4GB_VCO)) = (0x002220a8) #define DEF_TURISMO_TRX_SX_2_4GB_VCOBF() (REG32(ADR_TURISMO_TRX_SX_2_4GB_VCOBF)) = (0x04015445) #define DEF_TURISMO_TRX_SX_2_4GB_DIV_SDM() (REG32(ADR_TURISMO_TRX_SX_2_4GB_DIV_SDM)) = (0x001e0077) #define DEF_TURISMO_TRX_SX_2_4GB_SBCAL() (REG32(ADR_TURISMO_TRX_SX_2_4GB_SBCAL)) = (0x30700400) #define DEF_TURISMO_TRX_SX_2_4GB_AAC() (REG32(ADR_TURISMO_TRX_SX_2_4GB_AAC)) = (0x0517cd06) #define DEF_TURISMO_TRX_SX_2_4GB_TTL() (REG32(ADR_TURISMO_TRX_SX_2_4GB_TTL)) = (0x00018495) #define DEF_TURISMO_TRX_DPLL_TOP_REGISTER() (REG32(ADR_TURISMO_TRX_DPLL_TOP_REGISTER)) = (0x00180f20) #define DEF_TURISMO_TRX_DPLL_CKT_REGISTER() (REG32(ADR_TURISMO_TRX_DPLL_CKT_REGISTER)) = (0x021c89ac) #define DEF_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS() (REG32(ADR_TURISMO_TRX_DPLL_FB_DIVISION__REGISTERS)) = (0x24ec4ec5) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER17)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER18)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER19)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER20)) = (0x20202020) #define DEF_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21() (REG32(ADR_TURISMO_TRX_WF_DCOC_IDAC_REGISTER21)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16() (REG32(ADR_TURISMO_TRX_BT_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_TURISMO_TRX_MODE_DECODER_TIMER_REGISTER1)) = (0x00000008) #define DEF_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_T2R_TIMER_REGISTER)) = (0x02000100) #define DEF_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_WIFI_R2T_TIMER_REGISTER)) = (0x00010101) #define DEF_TURISMO_TRX_CALIBRATION_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_CALIBRATION_TIMER_REGISTER)) = (0x02222222) #define DEF_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0() (REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER0)) = (0x00000000) #define DEF_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_TURISMO_TRX_CALIBRATION_GAIN_REGISTER1)) = (0x08520000) #define DEF_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER() (REG32(ADR_TURISMO_TRX_2_4G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_TURISMO_TRX_READ_ONLY_FLAGS_ADC() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_ADC)) = (0x00000000) #define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_1)) = (0x00000000) #define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_2_4GB_2)) = (0x00000000) #define DEF_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aa8aaaa) #define DEF_TURISMO_TRX_5G_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_5G_LDO_REGISTER)) = (0x03044444) #define DEF_TURISMO_TRX_5G_RX_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_RX_REGISTER1)) = (0xa1154600) #define DEF_TURISMO_TRX_5G_RX_REGISTER2() (REG32(ADR_TURISMO_TRX_5G_RX_REGISTER2)) = (0x0005112e) #define DEF_TURISMO_TRX_5G_TX_FE_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TX_FE_REGISTER)) = (0x554489f4) #define DEF_TURISMO_TRX_5G_TX_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TX_REGISTER)) = (0x0060213f) #define DEF_TURISMO_TRX_5G_RX_FE_HG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_HG_REGISTER)) = (0x94490ea3) #define DEF_TURISMO_TRX_5G_RX_FE_MG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_MG_REGISTER)) = (0x94490ea2) #define DEF_TURISMO_TRX_5G_RX_FE_LG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_LG_REGISTER)) = (0x94498001) #define DEF_TURISMO_TRX_5G_RX_FE_ULG_REGISTER() (REG32(ADR_TURISMO_TRX_5G_RX_FE_ULG_REGISTER)) = (0x944b8004) #define DEF_TURISMO_TRX_5G_TX_DAC_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TX_DAC_REGISTER)) = (0x08804355) #define DEF_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_TURISMO_TRX_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x45800000) #define DEF_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_TURISMO_TRX_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x00005000) #define DEF_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER() (REG32(ADR_TURISMO_TRX_SX_5GB_ENABLE_TOP_CONTROLLER)) = (0x802aa2aa) #define DEF_TURISMO_TRX_SX_5GB_LDO_REGISTER() (REG32(ADR_TURISMO_TRX_SX_5GB_LDO_REGISTER)) = (0x2aa0021e) #define DEF_TURISMO_TRX_SX_5GB_PFD_CHP_() (REG32(ADR_TURISMO_TRX_SX_5GB_PFD_CHP_)) = (0x0008700c) #define DEF_TURISMO_TRX_SX_5GB_LPF_TTL() (REG32(ADR_TURISMO_TRX_SX_5GB_LPF_TTL)) = (0x31552c42) #define DEF_TURISMO_TRX_SX_5GB_VCO_LOGEN() (REG32(ADR_TURISMO_TRX_SX_5GB_VCO_LOGEN)) = (0x11120950) #define DEF_TURISMO_TRX_SX_5GB_DIV_SDM() (REG32(ADR_TURISMO_TRX_SX_5GB_DIV_SDM)) = (0x001e0077) #define DEF_TURISMO_TRX_SX_5GB_SBCAL() (REG32(ADR_TURISMO_TRX_SX_5GB_SBCAL)) = (0x23280400) #define DEF_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION() (REG32(ADR_TURISMO_TRX_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) = (0x002947ca) #define DEF_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION() (REG32(ADR_TURISMO_TRX_SX_5GB_LOGEN_CALIBRATION)) = (0x0100a805) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER17)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER18)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER19)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER20)) = (0x20202020) #define DEF_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21() (REG32(ADR_TURISMO_TRX_5G_DCOC_IDAC_REGISTER21)) = (0x20202020) #define DEF_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_MODE_DECODER_TIMER_REGISTER1)) = (0x0000000a) #define DEF_TURISMO_TRX_5G_T2R_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_5G_T2R_TIMER_REGISTER)) = (0x02000100) #define DEF_TURISMO_TRX_5G_R2T_TIMER_REGISTER() (REG32(ADR_TURISMO_TRX_5G_R2T_TIMER_REGISTER)) = (0x00010101) #define DEF_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER() (REG32(ADR_TURISMO_TRX_5G_CALIBRATION_TIMER_GAIN_REGISTER)) = (0x00022202) #define DEF_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_TURISMO_TRX_5G_CALIBRATION_GAIN_REGISTER1)) = (0x00000000) #define DEF_TURISMO_TRX_5G_TRX_DUMMY_REGISTER() (REG32(ADR_TURISMO_TRX_5G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_TURISMO_TRX_SX_5GB_DUMMY_REGISTER() (REG32(ADR_TURISMO_TRX_SX_5GB_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_1)) = (0x00000000) #define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_2)) = (0x00000000) #define DEF_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3() (REG32(ADR_TURISMO_TRX_READ_ONLY_FLAGS_SX_5GB_3)) = (0x00000000) #define DEF_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL() (REG32(ADR_TURISMO_TRX_5G_RX_LNA_MATCHING_SCA_CONTROL)) = (0x03333220) #define DEF_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL() (REG32(ADR_TURISMO_TRX_5G_RX_LNA_LOAD_SCA_CONTROL)) = (0x03333220) #define DEF_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL() (REG32(ADR_TURISMO_TRX_5G_TX_PGA_CAPSW_CONTROL)) = (0x02422220) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_0() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_0)) = (0x00000000) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_1() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_1)) = (0x036b55aa) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_2() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_2)) = (0x80000000) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_3() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_3)) = (0x00100000) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_4() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_4)) = (0x01000000) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_5() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_5)) = (0x00000000) #define DEF_TURISMO_TRX_DIGITAL_ADD_ON_6() (REG32(ADR_TURISMO_TRX_DIGITAL_ADD_ON_6)) = (0x00000000) #define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_00() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_00)) = (0x1ff00000) #define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_01() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_01)) = (0x00290000) #define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_02() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_02)) = (0x1fa60000) #define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_03() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_03)) = (0x00b70000) #define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_04() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_04)) = (0x1e800000) #define DEF_TURISMO_TRX_TX_BW20_FIR_COEF_05() (REG32(ADR_TURISMO_TRX_TX_BW20_FIR_COEF_05)) = (0x05060800) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_0() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_0)) = (0x00000000) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_1() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_1)) = (0x00000000) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_2() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_2)) = (0x08003800) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_3() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_3)) = (0x03330333) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_4() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_4)) = (0x70001000) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_5() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_5)) = (0x00000000) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_6() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_6)) = (0x00e500e5) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_7() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_7)) = (0x00000000) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_8() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_8)) = (0x00000000) #define DEF_TURISMO_TRX_RF_D_CAL_TOP_9() (REG32(ADR_TURISMO_TRX_RF_D_CAL_TOP_9)) = (0x00000044) #define DEF_TURISMO_TRX_HS3W_CTRL1() (REG32(ADR_TURISMO_TRX_HS3W_CTRL1)) = (0x00000000) #define DEF_TURISMO_TRX_HS3W_CTRL2() (REG32(ADR_TURISMO_TRX_HS3W_CTRL2)) = (0x00000000) #define DEF_TURISMO_TRX_HS3W_CTRL3() (REG32(ADR_TURISMO_TRX_HS3W_CTRL3)) = (0x60000000) #define DEF_TURISMO_TRX_RF_D_MODE_CTRL() (REG32(ADR_TURISMO_TRX_RF_D_MODE_CTRL)) = (0x00000000) #define DEF_TURISMO_TRX_RX_DC_CAL_RESULT() (REG32(ADR_TURISMO_TRX_RX_DC_CAL_RESULT)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_REG_1() (REG32(ADR_TURISMO_TRX_PMU_REG_1)) = (0x2d008014) #define DEF_TURISMO_TRX_PMU_REG_2() (REG32(ADR_TURISMO_TRX_PMU_REG_2)) = (0x251a8800) #define DEF_TURISMO_TRX_PMU_REG_3() (REG32(ADR_TURISMO_TRX_PMU_REG_3)) = (0x486041ae) #define DEF_TURISMO_TRX_PMU_REG_4() (REG32(ADR_TURISMO_TRX_PMU_REG_4)) = (0x95d98900) #define DEF_TURISMO_TRX_PMU_REG_5() (REG32(ADR_TURISMO_TRX_PMU_REG_5)) = (0xaaaaaaa8) #define DEF_TURISMO_TRX_PMU_REG_6() (REG32(ADR_TURISMO_TRX_PMU_REG_6)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_SLEEP_REG_1() (REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_1)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_SLEEP_REG_2() (REG32(ADR_TURISMO_TRX_PMU_SLEEP_REG_2)) = (0x00000040) #define DEF_TURISMO_TRX_PMU_RTC_REG_0() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_0)) = (0x00007d00) #define DEF_TURISMO_TRX_PMU_RTC_REG_1() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_1)) = (0x00000003) #define DEF_TURISMO_TRX_PMU_RTC_REG_2() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_2)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RTC_REG_3() (REG32(ADR_TURISMO_TRX_PMU_RTC_REG_3)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_CTRL_REG() (REG32(ADR_TURISMO_TRX_PMU_CTRL_REG)) = (0x00000010) #define DEF_TURISMO_TRX_PMU_STATE_REG() (REG32(ADR_TURISMO_TRX_PMU_STATE_REG)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_BT_CLK() (REG32(ADR_TURISMO_TRX_PMU_BT_CLK)) = (0x00000000) #define DEF_TURISMO_TRX_IO_REG_0() (REG32(ADR_TURISMO_TRX_IO_REG_0)) = (0x20022222) #define DEF_TURISMO_TRX_IO_REG_1() (REG32(ADR_TURISMO_TRX_IO_REG_1)) = (0x22222222) #define DEF_TURISMO_TRX_IO_REG_2() (REG32(ADR_TURISMO_TRX_IO_REG_2)) = (0x22222222) #define DEF_TURISMO_TRX_MCU_REG_0() (REG32(ADR_TURISMO_TRX_MCU_REG_0)) = (0x00003000) #define DEF_TURISMO_TRX_PMU_RAM_00() (REG32(ADR_TURISMO_TRX_PMU_RAM_00)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_01() (REG32(ADR_TURISMO_TRX_PMU_RAM_01)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_02() (REG32(ADR_TURISMO_TRX_PMU_RAM_02)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_03() (REG32(ADR_TURISMO_TRX_PMU_RAM_03)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_04() (REG32(ADR_TURISMO_TRX_PMU_RAM_04)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_05() (REG32(ADR_TURISMO_TRX_PMU_RAM_05)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_06() (REG32(ADR_TURISMO_TRX_PMU_RAM_06)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_07() (REG32(ADR_TURISMO_TRX_PMU_RAM_07)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_08() (REG32(ADR_TURISMO_TRX_PMU_RAM_08)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_09() (REG32(ADR_TURISMO_TRX_PMU_RAM_09)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_10() (REG32(ADR_TURISMO_TRX_PMU_RAM_10)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_11() (REG32(ADR_TURISMO_TRX_PMU_RAM_11)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_12() (REG32(ADR_TURISMO_TRX_PMU_RAM_12)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_13() (REG32(ADR_TURISMO_TRX_PMU_RAM_13)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_14() (REG32(ADR_TURISMO_TRX_PMU_RAM_14)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_15() (REG32(ADR_TURISMO_TRX_PMU_RAM_15)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_16() (REG32(ADR_TURISMO_TRX_PMU_RAM_16)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_17() (REG32(ADR_TURISMO_TRX_PMU_RAM_17)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_18() (REG32(ADR_TURISMO_TRX_PMU_RAM_18)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_19() (REG32(ADR_TURISMO_TRX_PMU_RAM_19)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_20() (REG32(ADR_TURISMO_TRX_PMU_RAM_20)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_21() (REG32(ADR_TURISMO_TRX_PMU_RAM_21)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_22() (REG32(ADR_TURISMO_TRX_PMU_RAM_22)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_23() (REG32(ADR_TURISMO_TRX_PMU_RAM_23)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_24() (REG32(ADR_TURISMO_TRX_PMU_RAM_24)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_25() (REG32(ADR_TURISMO_TRX_PMU_RAM_25)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_26() (REG32(ADR_TURISMO_TRX_PMU_RAM_26)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_27() (REG32(ADR_TURISMO_TRX_PMU_RAM_27)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_28() (REG32(ADR_TURISMO_TRX_PMU_RAM_28)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_29() (REG32(ADR_TURISMO_TRX_PMU_RAM_29)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_30() (REG32(ADR_TURISMO_TRX_PMU_RAM_30)) = (0x00000000) #define DEF_TURISMO_TRX_PMU_RAM_31() (REG32(ADR_TURISMO_TRX_PMU_RAM_31)) = (0x00000000) #define DEF_MODE_REGISTER() (REG32(ADR_MODE_REGISTER)) = (0x06000044) #define DEF_2_4G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_2_4G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aaaaaaa) #define DEF_2_4G_CALIBRATION__AMP__TEST_REGISTER() (REG32(ADR_2_4G_CALIBRATION__AMP__TEST_REGISTER)) = (0x20001557) #define DEF_2_4G_LDO_REGISTER() (REG32(ADR_2_4G_LDO_REGISTER)) = (0x44440044) #define DEF_WIFI_HT20_RX_FILTER_REGISTER() (REG32(ADR_WIFI_HT20_RX_FILTER_REGISTER)) = (0x43b1559b) #define DEF_WIFI_HT40_RX_FILTER_REGISTER() (REG32(ADR_WIFI_HT40_RX_FILTER_REGISTER)) = (0x43b2558d) #define DEF_BT_RX_FILTER_REGISTER() (REG32(ADR_BT_RX_FILTER_REGISTER)) = (0x439d559b) #define DEF_2_4G_RX_REGISTER() (REG32(ADR_2_4G_RX_REGISTER)) = (0x604aea48) #define DEF_2_4G_TX_FE_REGISTER() (REG32(ADR_2_4G_TX_FE_REGISTER)) = (0x0033e73e) #define DEF_2_4G_TX_PA_REGISTER() (REG32(ADR_2_4G_TX_PA_REGISTER)) = (0x57444497) #define DEF_2_4G_TX_REGISTER() (REG32(ADR_2_4G_TX_REGISTER)) = (0x2a00a13f) #define DEF_2_4G_RX_FE_HG_REGISTER() (REG32(ADR_2_4G_RX_FE_HG_REGISTER)) = (0x97c10e93) #define DEF_2_4G_RX_FE_MG_REGISTER() (REG32(ADR_2_4G_RX_FE_MG_REGISTER)) = (0x97c10e92) #define DEF_2_4G_RX_FE_LG_REGISTER() (REG32(ADR_2_4G_RX_FE_LG_REGISTER)) = (0x97c18001) #define DEF_2_4G_RX_FE_ULG_REGISTER() (REG32(ADR_2_4G_RX_FE_ULG_REGISTER)) = (0x97c38004) #define DEF_BT_RX_FE_HG_REGISTER() (REG32(ADR_BT_RX_FE_HG_REGISTER)) = (0x88210863) #define DEF_BT_RX_FE_MG_REGISTER() (REG32(ADR_BT_RX_FE_MG_REGISTER)) = (0x88210862) #define DEF_BT_RX_FE_LG_REGISTER() (REG32(ADR_BT_RX_FE_LG_REGISTER)) = (0x88216001) #define DEF_BT_RX_FE_ULG_REGISTER() (REG32(ADR_BT_RX_FE_ULG_REGISTER)) = (0x88036000) #define DEF_WBT_RX_ADC_REGISTER() (REG32(ADR_WBT_RX_ADC_REGISTER)) = (0x83050502) #define DEF_WIFI_TX_DAC_REGISTER() (REG32(ADR_WIFI_TX_DAC_REGISTER)) = (0x08804355) #define DEF_BT_TX_DAC_REGISTER() (REG32(ADR_BT_TX_DAC_REGISTER)) = (0x08800755) #define DEF_SX_ENABLE_REGISTER_TOP_CONTROLLER() (REG32(ADR_SX_ENABLE_REGISTER_TOP_CONTROLLER)) = (0x802aa2aa) #define DEF_SX_2_4G_LDO_REGISTER() (REG32(ADR_SX_2_4G_LDO_REGISTER)) = (0x2aa0021e) #define DEF_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_SX_2_4GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x5f800000) #define DEF_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_SX_2_4GB_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x00204280) #define DEF_SX_2_4GB_PFD_CHP_() (REG32(ADR_SX_2_4GB_PFD_CHP_)) = (0x05c30606) #define DEF_SX_2_4GB_LPF() (REG32(ADR_SX_2_4GB_LPF)) = (0x2c4293d6) #define DEF_SX_2_4GB_VCO() (REG32(ADR_SX_2_4GB_VCO)) = (0x002220a8) #define DEF_SX_2_4GB_VCOBF() (REG32(ADR_SX_2_4GB_VCOBF)) = (0x04015445) #define DEF_SX_2_4GB_DIV_SDM() (REG32(ADR_SX_2_4GB_DIV_SDM)) = (0x001e0077) #define DEF_SX_2_4GB_SBCAL() (REG32(ADR_SX_2_4GB_SBCAL)) = (0x30700400) #define DEF_SX_2_4GB_AAC() (REG32(ADR_SX_2_4GB_AAC)) = (0x0517cd06) #define DEF_SX_2_4GB_TTL() (REG32(ADR_SX_2_4GB_TTL)) = (0x00018495) // #define DEF_DPLL_TOP_REGISTER() (REG32(ADR_DPLL_TOP_REGISTER)) = (0xxxxxxxxx) // #define DEF_DPLL_CKT_REGISTER() (REG32(ADR_DPLL_CKT_REGISTER)) = (0xxxxxxxxx) // #define DEF_DPLL_FB_DIVISION__REGISTERS() (REG32(ADR_DPLL_FB_DIVISION__REGISTERS)) = (0xxxxxxxxx) #define DEF_WF_DCOC_IDAC_REGISTER1() (REG32(ADR_WF_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER2() (REG32(ADR_WF_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER3() (REG32(ADR_WF_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER4() (REG32(ADR_WF_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER5() (REG32(ADR_WF_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER6() (REG32(ADR_WF_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER7() (REG32(ADR_WF_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER8() (REG32(ADR_WF_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER9() (REG32(ADR_WF_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER10() (REG32(ADR_WF_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER11() (REG32(ADR_WF_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER12() (REG32(ADR_WF_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER13() (REG32(ADR_WF_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER14() (REG32(ADR_WF_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER15() (REG32(ADR_WF_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER16() (REG32(ADR_WF_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER17() (REG32(ADR_WF_DCOC_IDAC_REGISTER17)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER18() (REG32(ADR_WF_DCOC_IDAC_REGISTER18)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER19() (REG32(ADR_WF_DCOC_IDAC_REGISTER19)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER20() (REG32(ADR_WF_DCOC_IDAC_REGISTER20)) = (0x20202020) #define DEF_WF_DCOC_IDAC_REGISTER21() (REG32(ADR_WF_DCOC_IDAC_REGISTER21)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER1() (REG32(ADR_BT_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER2() (REG32(ADR_BT_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER3() (REG32(ADR_BT_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER4() (REG32(ADR_BT_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER5() (REG32(ADR_BT_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER6() (REG32(ADR_BT_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER7() (REG32(ADR_BT_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER8() (REG32(ADR_BT_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER9() (REG32(ADR_BT_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER10() (REG32(ADR_BT_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER11() (REG32(ADR_BT_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER12() (REG32(ADR_BT_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER13() (REG32(ADR_BT_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER14() (REG32(ADR_BT_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER15() (REG32(ADR_BT_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_BT_DCOC_IDAC_REGISTER16() (REG32(ADR_BT_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_MODE_DECODER_TIMER_REGISTER1)) = (0x00000008) #define DEF_WIFI_T2R_TIMER_REGISTER() (REG32(ADR_WIFI_T2R_TIMER_REGISTER)) = (0x02000100) #define DEF_WIFI_R2T_TIMER_REGISTER() (REG32(ADR_WIFI_R2T_TIMER_REGISTER)) = (0x00010101) #define DEF_CALIBRATION_TIMER_REGISTER() (REG32(ADR_CALIBRATION_TIMER_REGISTER)) = (0x02222222) #define DEF_CALIBRATION_GAIN_REGISTER0() (REG32(ADR_CALIBRATION_GAIN_REGISTER0)) = (0x00000000) #define DEF_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_CALIBRATION_GAIN_REGISTER1)) = (0x04520000) #define DEF_2_4G_TRX_DUMMY_REGISTER() (REG32(ADR_2_4G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_READ_ONLY_FLAGS_ADC() (REG32(ADR_READ_ONLY_FLAGS_ADC)) = (0x00000000) #define DEF_READ_ONLY_FLAGS_SX_2_4GB_1() (REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_1)) = (0x00000000) #define DEF_READ_ONLY_FLAGS_SX_2_4GB_2() (REG32(ADR_READ_ONLY_FLAGS_SX_2_4GB_2)) = (0x00000000) #define DEF_5G_TRX_MANUAL_ENABLE_REGISTER() (REG32(ADR_5G_TRX_MANUAL_ENABLE_REGISTER)) = (0x2aa8aaaa) #define DEF_5G_LDO_REGISTER() (REG32(ADR_5G_LDO_REGISTER)) = (0x03044444) #define DEF_5G_RX_REGISTER1() (REG32(ADR_5G_RX_REGISTER1)) = (0xa1152600) #define DEF_5G_RX_REGISTER2() (REG32(ADR_5G_RX_REGISTER2)) = (0x0505112e) #define DEF_5G_TX_FE_REGISTER() (REG32(ADR_5G_TX_FE_REGISTER)) = (0x554489e4) #define DEF_5G_TX_REGISTER() (REG32(ADR_5G_TX_REGISTER)) = (0x9060a13f) #define DEF_5G_RX_FE_HG_REGISTER() (REG32(ADR_5G_RX_FE_HG_REGISTER)) = (0x94490ea3) #define DEF_5G_RX_FE_MG_REGISTER() (REG32(ADR_5G_RX_FE_MG_REGISTER)) = (0x94490ea2) #define DEF_5G_RX_FE_LG_REGISTER() (REG32(ADR_5G_RX_FE_LG_REGISTER)) = (0x94498001) #define DEF_5G_RX_FE_ULG_REGISTER() (REG32(ADR_5G_RX_FE_ULG_REGISTER)) = (0x944b8004) #define DEF_5G_TX_DAC_REGISTER() (REG32(ADR_5G_TX_DAC_REGISTER)) = (0x08804355) #define DEF_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS() (REG32(ADR_SX_5GB_FRACTIONAL_AND_INTEGER_8BITS)) = (0x45800000) #define DEF_SX_5GB_REGISTER_INT3BIT___CH_TABLE() (REG32(ADR_SX_5GB_REGISTER_INT3BIT___CH_TABLE)) = (0x00005000) #define DEF_SX_5GB_ENABLE_TOP_CONTROLLER() (REG32(ADR_SX_5GB_ENABLE_TOP_CONTROLLER)) = (0x802aa2aa) #define DEF_SX_5GB_LDO_REGISTER() (REG32(ADR_SX_5GB_LDO_REGISTER)) = (0x2aa0029e) #define DEF_SX_5GB_PFD_CHP_() (REG32(ADR_SX_5GB_PFD_CHP_)) = (0x0008730c) #define DEF_SX_5GB_LPF_TTL() (REG32(ADR_SX_5GB_LPF_TTL)) = (0x31552cc3) #define DEF_SX_5GB_VCO_LOGEN() (REG32(ADR_SX_5GB_VCO_LOGEN)) = (0x11120950) #define DEF_SX_5GB_DIV_SDM() (REG32(ADR_SX_5GB_DIV_SDM)) = (0x0f1e003f) #define DEF_SX_5GB_SBCAL() (REG32(ADR_SX_5GB_SBCAL)) = (0x23280400) #define DEF_SX_5GB_VCO_AAC_LOGEN_CALIBRATION() (REG32(ADR_SX_5GB_VCO_AAC_LOGEN_CALIBRATION)) = (0x002947ca) #define DEF_SX_5GB_LOGEN_CALIBRATION() (REG32(ADR_SX_5GB_LOGEN_CALIBRATION)) = (0x0100a805) #define DEF_5G_DCOC_IDAC_REGISTER1() (REG32(ADR_5G_DCOC_IDAC_REGISTER1)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER2() (REG32(ADR_5G_DCOC_IDAC_REGISTER2)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER3() (REG32(ADR_5G_DCOC_IDAC_REGISTER3)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER4() (REG32(ADR_5G_DCOC_IDAC_REGISTER4)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER5() (REG32(ADR_5G_DCOC_IDAC_REGISTER5)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER6() (REG32(ADR_5G_DCOC_IDAC_REGISTER6)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER7() (REG32(ADR_5G_DCOC_IDAC_REGISTER7)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER8() (REG32(ADR_5G_DCOC_IDAC_REGISTER8)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER9() (REG32(ADR_5G_DCOC_IDAC_REGISTER9)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER10() (REG32(ADR_5G_DCOC_IDAC_REGISTER10)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER11() (REG32(ADR_5G_DCOC_IDAC_REGISTER11)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER12() (REG32(ADR_5G_DCOC_IDAC_REGISTER12)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER13() (REG32(ADR_5G_DCOC_IDAC_REGISTER13)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER14() (REG32(ADR_5G_DCOC_IDAC_REGISTER14)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER15() (REG32(ADR_5G_DCOC_IDAC_REGISTER15)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER16() (REG32(ADR_5G_DCOC_IDAC_REGISTER16)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER17() (REG32(ADR_5G_DCOC_IDAC_REGISTER17)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER18() (REG32(ADR_5G_DCOC_IDAC_REGISTER18)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER19() (REG32(ADR_5G_DCOC_IDAC_REGISTER19)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER20() (REG32(ADR_5G_DCOC_IDAC_REGISTER20)) = (0x20202020) #define DEF_5G_DCOC_IDAC_REGISTER21() (REG32(ADR_5G_DCOC_IDAC_REGISTER21)) = (0x20202020) #define DEF_5G_MODE_DECODER_TIMER_REGISTER1() (REG32(ADR_5G_MODE_DECODER_TIMER_REGISTER1)) = (0x0000000a) #define DEF_5G_T2R_TIMER_REGISTER() (REG32(ADR_5G_T2R_TIMER_REGISTER)) = (0x02000100) #define DEF_5G_R2T_TIMER_REGISTER() (REG32(ADR_5G_R2T_TIMER_REGISTER)) = (0x00010101) #define DEF_5G_CALIBRATION_TIMER_GAIN_REGISTER() (REG32(ADR_5G_CALIBRATION_TIMER_GAIN_REGISTER)) = (0x00022202) #define DEF_5G_CALIBRATION_GAIN_REGISTER1() (REG32(ADR_5G_CALIBRATION_GAIN_REGISTER1)) = (0x00000000) #define DEF_5G_TRX_DUMMY_REGISTER() (REG32(ADR_5G_TRX_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_SX_5GB_DUMMY_REGISTER() (REG32(ADR_SX_5GB_DUMMY_REGISTER)) = (0xaaaaaaaa) #define DEF_READ_ONLY_FLAGS_SX_5GB_1() (REG32(ADR_READ_ONLY_FLAGS_SX_5GB_1)) = (0x00000000) #define DEF_READ_ONLY_FLAGS_SX_5GB_2() (REG32(ADR_READ_ONLY_FLAGS_SX_5GB_2)) = (0x00000000) #define DEF_READ_ONLY_FLAGS_SX_5GB_3() (REG32(ADR_READ_ONLY_FLAGS_SX_5GB_3)) = (0x00000000) #define DEF_5G_RX_LNA_MATCHING_SCA_CONTROL() (REG32(ADR_5G_RX_LNA_MATCHING_SCA_CONTROL)) = (0x02000000) #define DEF_5G_RX_LNA_LOAD_SCA_CONTROL() (REG32(ADR_5G_RX_LNA_LOAD_SCA_CONTROL)) = (0x06665200) #define DEF_5G_TX_PGA_CAPSW_CONTROL_I() (REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_I)) = (0x924a924a) #define DEF_5G_TX_PGA_CAPSW_CONTROL_II() (REG32(ADR_5G_TX_PGA_CAPSW_CONTROL_II)) = (0x924a924a) #define DEF_5G_TX_GAIN_PAFB_CONTROL() (REG32(ADR_5G_TX_GAIN_PAFB_CONTROL)) = (0x0000000f) #define DEF_DIGITAL_ADD_ON_0() (REG32(ADR_DIGITAL_ADD_ON_0)) = (0x00000000) #define DEF_DIGITAL_ADD_ON_1() (REG32(ADR_DIGITAL_ADD_ON_1)) = (0x036b55aa) #define DEF_DIGITAL_ADD_ON_2() (REG32(ADR_DIGITAL_ADD_ON_2)) = (0x80000000) #define DEF_DIGITAL_ADD_ON_3() (REG32(ADR_DIGITAL_ADD_ON_3)) = (0x00100000) #define DEF_DIGITAL_ADD_ON_4() (REG32(ADR_DIGITAL_ADD_ON_4)) = (0x01000000) #define DEF_DIGITAL_ADD_ON_5() (REG32(ADR_DIGITAL_ADD_ON_5)) = (0x00000000) #define DEF_DIGITAL_ADD_ON_6() (REG32(ADR_DIGITAL_ADD_ON_6)) = (0x00000000) #define DEF_RX_RC_VALUE_TUNE() (REG32(ADR_RX_RC_VALUE_TUNE)) = (0x00000000) #define DEF_TRX_IQ_COMP_2G() (REG32(ADR_TRX_IQ_COMP_2G)) = (0x00000000) #define DEF_TRX_IQ_COMP_5G_0() (REG32(ADR_TRX_IQ_COMP_5G_0)) = (0x00000000) #define DEF_TRX_IQ_COMP_5G_1() (REG32(ADR_TRX_IQ_COMP_5G_1)) = (0x00000000) #define DEF_TRX_IQ_COMP_5G_2() (REG32(ADR_TRX_IQ_COMP_5G_2)) = (0x00000000) #define DEF_TRX_IQ_COMP_5G_3() (REG32(ADR_TRX_IQ_COMP_5G_3)) = (0x00000000) #define DEF_RF_D_CAL_TOP_0() (REG32(ADR_RF_D_CAL_TOP_0)) = (0x00000000) #define DEF_RF_D_CAL_TOP_1() (REG32(ADR_RF_D_CAL_TOP_1)) = (0x00000000) #define DEF_RF_D_CAL_TOP_2() (REG32(ADR_RF_D_CAL_TOP_2)) = (0x08003800) #define DEF_RF_D_CAL_TOP_3() (REG32(ADR_RF_D_CAL_TOP_3)) = (0x03330333) #define DEF_RF_D_CAL_TOP_4() (REG32(ADR_RF_D_CAL_TOP_4)) = (0x70000000) #define DEF_RF_D_CAL_TOP_5() (REG32(ADR_RF_D_CAL_TOP_5)) = (0x00000000) #define DEF_RF_D_CAL_TOP_6() (REG32(ADR_RF_D_CAL_TOP_6)) = (0x00e500e5) #define DEF_RF_D_CAL_TOP_7() (REG32(ADR_RF_D_CAL_TOP_7)) = (0x00000000) #define DEF_RF_D_CAL_TOP_8() (REG32(ADR_RF_D_CAL_TOP_8)) = (0x00000000) #define DEF_RF_D_CAL_TOP_9() (REG32(ADR_RF_D_CAL_TOP_9)) = (0x00000044) #define DEF_HS3W_CTRL1() (REG32(ADR_HS3W_CTRL1)) = (0x00000000) #define DEF_HS3W_CTRL2() (REG32(ADR_HS3W_CTRL2)) = (0x00000000) #define DEF_HS3W_CTRL3() (REG32(ADR_HS3W_CTRL3)) = (0x60000000) #define DEF_RF_D_MODE_CTRL() (REG32(ADR_RF_D_MODE_CTRL)) = (0x00000000) #define DEF_HS3W_READ_OUT_1() (REG32(ADR_HS3W_READ_OUT_1)) = (0x00000000) #define DEF_HS3W_READ_OUT_2_() (REG32(ADR_HS3W_READ_OUT_2_)) = (0x00000000) #define DEF_HS3W_READ_OUT_3() (REG32(ADR_HS3W_READ_OUT_3)) = (0x00000000) #define DEF_SX_LOCK_FREQ_1() (REG32(ADR_SX_LOCK_FREQ_1)) = (0x00000000) #define DEF_SX_LOCK_FREQ_2() (REG32(ADR_SX_LOCK_FREQ_2)) = (0x00000000) #define DEF_RX_DC_CAL_RESULT() (REG32(ADR_RX_DC_CAL_RESULT)) = (0x00000000) #define DEF_AUDIO_CTRL_REG() (REG32(ADR_AUDIO_CTRL_REG)) = (0x00000000) #define DEF_AUDIO_PDM_REG() (REG32(ADR_AUDIO_PDM_REG)) = (0x08003800) #define DEF_RF_5G_TX_PARTITION_BAND1() (REG32(ADR_RF_5G_TX_PARTITION_BAND1)) = (0x13ec157c) #define DEF_RF_5G_TX_PARTITION_BAND2() (REG32(ADR_RF_5G_TX_PARTITION_BAND2)) = (0x00001644) #define DEF_WIFI_PADPD_5100_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG0)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG1)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG2)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG3)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG4)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG5)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG6)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG7)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG8)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5100_GAIN_REG9)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5100_GAIN_REGA)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5100_GAIN_REGB)) = (0x02000200) #define DEF_WIFI_PADPD_5100_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5100_GAIN_REGC)) = (0x02000200) #define DEF_WIFI_PADPD_5100_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG0)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG1)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG2)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG3)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG4)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG5)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG6)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG7)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG8)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5100_PHASE_REG9)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5100_PHASE_REGA)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5100_PHASE_REGB)) = (0x00000000) #define DEF_WIFI_PADPD_5100_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5100_PHASE_REGC)) = (0x00000000) #define DEF_WIFI_PADPD_5500_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG0)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG1)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG2)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG3)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG4)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG5)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG6)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG7)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG8)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5500_GAIN_REG9)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5500_GAIN_REGA)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5500_GAIN_REGB)) = (0x02000200) #define DEF_WIFI_PADPD_5500_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5500_GAIN_REGC)) = (0x02000200) #define DEF_WIFI_PADPD_5500_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG0)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG1)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG2)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG3)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG4)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG5)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG6)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG7)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG8)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5500_PHASE_REG9)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5500_PHASE_REGA)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5500_PHASE_REGB)) = (0x00000000) #define DEF_WIFI_PADPD_5500_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5500_PHASE_REGC)) = (0x00000000) #define DEF_WIFI_PADPD_5700_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG0)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG1)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG2)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG3)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG4)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG5)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG6)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG7)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG8)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5700_GAIN_REG9)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5700_GAIN_REGA)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5700_GAIN_REGB)) = (0x02000200) #define DEF_WIFI_PADPD_5700_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5700_GAIN_REGC)) = (0x02000200) #define DEF_WIFI_PADPD_5700_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG0)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG1)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG2)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG3)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG4)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG5)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG6)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG7)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG8)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5700_PHASE_REG9)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5700_PHASE_REGA)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5700_PHASE_REGB)) = (0x00000000) #define DEF_WIFI_PADPD_5700_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5700_PHASE_REGC)) = (0x00000000) #define DEF_WIFI_PADPD_5900_GAIN_REG0() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG0)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG1() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG1)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG2() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG2)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG3() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG3)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG4() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG4)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG5() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG5)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG6() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG6)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG7() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG7)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG8() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG8)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REG9() (REG32(ADR_WIFI_PADPD_5900_GAIN_REG9)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REGA() (REG32(ADR_WIFI_PADPD_5900_GAIN_REGA)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REGB() (REG32(ADR_WIFI_PADPD_5900_GAIN_REGB)) = (0x02000200) #define DEF_WIFI_PADPD_5900_GAIN_REGC() (REG32(ADR_WIFI_PADPD_5900_GAIN_REGC)) = (0x02000200) #define DEF_WIFI_PADPD_5900_PHASE_REG0() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG0)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG1() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG1)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG2() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG2)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG3() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG3)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG4() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG4)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG5() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG5)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG6() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG6)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG7() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG7)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG8() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG8)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REG9() (REG32(ADR_WIFI_PADPD_5900_PHASE_REG9)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REGA() (REG32(ADR_WIFI_PADPD_5900_PHASE_REGA)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REGB() (REG32(ADR_WIFI_PADPD_5900_PHASE_REGB)) = (0x00000000) #define DEF_WIFI_PADPD_5900_PHASE_REGC() (REG32(ADR_WIFI_PADPD_5900_PHASE_REGC)) = (0x00000000) #define DEF_WIFI_PADPD_CAL_TONEGEN_REG() (REG32(ADR_WIFI_PADPD_CAL_TONEGEN_REG)) = (0x00000000) #define DEF_WIFI_PADPD_CAL_RX_PADPD_REG() (REG32(ADR_WIFI_PADPD_CAL_RX_PADPD_REG)) = (0x00000000) #define DEF_WIFI_PADPD_CAL_RX_RO() (REG32(ADR_WIFI_PADPD_CAL_RX_RO)) = (0x00000000) #define DEF_WIFI_PADPD_CFR() (REG32(ADR_WIFI_PADPD_CFR)) = (0x02000200) #define DEF_WIFI_PADPD_DC_RM() (REG32(ADR_WIFI_PADPD_DC_RM)) = (0x00000000) #define DEF_WIFI_PADPD_TXIQ_CLIP_REG() (REG32(ADR_WIFI_PADPD_TXIQ_CLIP_REG)) = (0x02000200) #define DEF_WIFI_PADPD_TXIQ_CONTROL_REG() (REG32(ADR_WIFI_PADPD_TXIQ_CONTROL_REG)) = (0x00000080) #define DEF_WIFI_PADPD_TXIQ_DPD_DC_REG() (REG32(ADR_WIFI_PADPD_TXIQ_DPD_DC_REG)) = (0x00000000) #define DEF_WIFI_PADPD_TXIQ_DC_OFFSET_REG() (REG32(ADR_WIFI_PADPD_TXIQ_DC_OFFSET_REG)) = (0x00000000) #define DEF_WIFI_PADPD_2G_CONTROL_REG() (REG32(ADR_WIFI_PADPD_2G_CONTROL_REG)) = (0x00000000) #define DEF_WIFI_PADPD_2G_GAIN_REG0() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG0)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG1() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG1)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG2() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG2)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG3() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG3)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG4() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG4)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG5() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG5)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG6() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG6)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG7() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG7)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG8() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG8)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REG9() (REG32(ADR_WIFI_PADPD_2G_GAIN_REG9)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REGA() (REG32(ADR_WIFI_PADPD_2G_GAIN_REGA)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REGB() (REG32(ADR_WIFI_PADPD_2G_GAIN_REGB)) = (0x02000200) #define DEF_WIFI_PADPD_2G_GAIN_REGC() (REG32(ADR_WIFI_PADPD_2G_GAIN_REGC)) = (0x02000200) #define DEF_WIFI_PADPD_2G_PHASE_REG0() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG0)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG1() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG1)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG2() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG2)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG3() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG3)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG4() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG4)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG5() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG5)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG6() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG6)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG7() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG7)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG8() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG8)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REG9() (REG32(ADR_WIFI_PADPD_2G_PHASE_REG9)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REGA() (REG32(ADR_WIFI_PADPD_2G_PHASE_REGA)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REGB() (REG32(ADR_WIFI_PADPD_2G_PHASE_REGB)) = (0x00000000) #define DEF_WIFI_PADPD_2G_PHASE_REGC() (REG32(ADR_WIFI_PADPD_2G_PHASE_REGC)) = (0x00000000) #define DEF_WIFI_PADPD_5G_BB_GAIN_REG() (REG32(ADR_WIFI_PADPD_5G_BB_GAIN_REG)) = (0x80808080) #define DEF_WIFI_PADPD_2G_BB_GAIN_REG() (REG32(ADR_WIFI_PADPD_2G_BB_GAIN_REG)) = (0x00000080) #define DEF_WIFI_PADPD_TX_GAIN_0P5DB_REG() (REG32(ADR_WIFI_PADPD_TX_GAIN_0P5DB_REG)) = (0x79807980) #define DEF_HS5W_MD_EN() (REG32(ADR_HS5W_MD_EN)) = (0x00000001) #define DEF_HS5W_MAN() (REG32(ADR_HS5W_MAN)) = (0xfe000000) #define DEF_HS5W_MAN_SET_ADD0() (REG32(ADR_HS5W_MAN_SET_ADD0)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD1() (REG32(ADR_HS5W_MAN_SET_ADD1)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD2() (REG32(ADR_HS5W_MAN_SET_ADD2)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD3() (REG32(ADR_HS5W_MAN_SET_ADD3)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD4_CH() (REG32(ADR_HS5W_MAN_SET_ADD4_CH)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD4_CH_5GB() (REG32(ADR_HS5W_MAN_SET_ADD4_CH_5GB)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD4_F() (REG32(ADR_HS5W_MAN_SET_ADD4_F)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD4_F_5GB() (REG32(ADR_HS5W_MAN_SET_ADD4_F_5GB)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD5() (REG32(ADR_HS5W_MAN_SET_ADD5)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD5_5GB() (REG32(ADR_HS5W_MAN_SET_ADD5_5GB)) = (0x00000000) #define DEF_HS5W_MAN_SET_ADD6() (REG32(ADR_HS5W_MAN_SET_ADD6)) = (0x00000000) #define DEF_WIFI_PADPD_RESERVED_REG() (REG32(ADR_WIFI_PADPD_RESERVED_REG)) = (0x00000000) #define DEF_PMU_REG_1() (REG32(ADR_PMU_REG_1)) = (0x25008014) #define DEF_PMU_REG_2() (REG32(ADR_PMU_REG_2)) = (0x251a8820) #define DEF_PMU_REG_3() (REG32(ADR_PMU_REG_3)) = (0x486041be) #define DEF_PMU_REG_4() (REG32(ADR_PMU_REG_4)) = (0x95d98900) #define DEF_PMU_REG_5() (REG32(ADR_PMU_REG_5)) = (0xaaaaaaa8) #define DEF_PMU_REG_6() (REG32(ADR_PMU_REG_6)) = (0x00000000) #define DEF_PMU_SLEEP_REG_1() (REG32(ADR_PMU_SLEEP_REG_1)) = (0x00000000) #define DEF_PMU_SLEEP_REG_2() (REG32(ADR_PMU_SLEEP_REG_2)) = (0x00000040) #define DEF_PMU_RTC_REG_0() (REG32(ADR_PMU_RTC_REG_0)) = (0x00007d00) #define DEF_PMU_RTC_REG_1() (REG32(ADR_PMU_RTC_REG_1)) = (0x00000003) #define DEF_PMU_RTC_REG_2() (REG32(ADR_PMU_RTC_REG_2)) = (0x00000000) #define DEF_PMU_RTC_REG_3() (REG32(ADR_PMU_RTC_REG_3)) = (0x00000000) #define DEF_PMU_CTRL_REG() (REG32(ADR_PMU_CTRL_REG)) = (0x00000010) #define DEF_PMU_STATE_REG() (REG32(ADR_PMU_STATE_REG)) = (0x00000000) #define DEF_PMU_DPLL_REG_0() (REG32(ADR_PMU_DPLL_REG_0)) = (0x0002ffa4) #define DEF_PMU_DPLL_REG_1() (REG32(ADR_PMU_DPLL_REG_1)) = (0x00180f20) #define DEF_PMU_DPLL_REG_2() (REG32(ADR_PMU_DPLL_REG_2)) = (0x021c89ac) #define DEF_PMU_DPLL_REG_3() (REG32(ADR_PMU_DPLL_REG_3)) = (0x24ec4ec5) #define DEF_PMU_SLEEP_MODE_REG() (REG32(ADR_PMU_SLEEP_MODE_REG)) = (0x010080be) #define DEF_PMU_RAM_00() (REG32(ADR_PMU_RAM_00)) = (0x00000000) #define DEF_PMU_RAM_01() (REG32(ADR_PMU_RAM_01)) = (0x00000000) #define DEF_PMU_RAM_02() (REG32(ADR_PMU_RAM_02)) = (0x00000000) #define DEF_PMU_RAM_03() (REG32(ADR_PMU_RAM_03)) = (0x00000000) #define DEF_PMU_RAM_04() (REG32(ADR_PMU_RAM_04)) = (0x00000000) #define DEF_PMU_RAM_05() (REG32(ADR_PMU_RAM_05)) = (0x00000000) #define DEF_PMU_RAM_06() (REG32(ADR_PMU_RAM_06)) = (0x00000000) #define DEF_PMU_RAM_07() (REG32(ADR_PMU_RAM_07)) = (0x00000000) #define DEF_PMU_RAM_08() (REG32(ADR_PMU_RAM_08)) = (0x00000000) #define DEF_PMU_RAM_09() (REG32(ADR_PMU_RAM_09)) = (0x00000000) #define DEF_PMU_RAM_10() (REG32(ADR_PMU_RAM_10)) = (0x00000000) #define DEF_PMU_RAM_11() (REG32(ADR_PMU_RAM_11)) = (0x00000000) #define DEF_PMU_RAM_12() (REG32(ADR_PMU_RAM_12)) = (0x00000000) #define DEF_PMU_RAM_13() (REG32(ADR_PMU_RAM_13)) = (0x00000000) #define DEF_PMU_RAM_14() (REG32(ADR_PMU_RAM_14)) = (0x00000000) #define DEF_PMU_RAM_15() (REG32(ADR_PMU_RAM_15)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_SYS_REG() (REG32(ADR_WIFI_PHY_COMMON_SYS_REG)) = (0x00000010) #define DEF_WIFI_PHY_COMMON_ENABLE_REG() (REG32(ADR_WIFI_PHY_COMMON_ENABLE_REG)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_VERSION_REG() (REG32(ADR_WIFI_PHY_COMMON_VERSION_REG)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_DES_REG0() (REG32(ADR_WIFI_PHY_COMMON_DES_REG0)) = (0x00000064) #define DEF_WIFI_PHY_COMMON_DES_REG1() (REG32(ADR_WIFI_PHY_COMMON_DES_REG1)) = (0x00000fff) #define DEF_WIFI_PHY_COMMON_DES_REG2() (REG32(ADR_WIFI_PHY_COMMON_DES_REG2)) = (0x00807f03) #define DEF_WIFI_PHY_COMMON_DES_REG3() (REG32(ADR_WIFI_PHY_COMMON_DES_REG3)) = (0x0069023c) #define DEF_WIFI_PHY_COMMON_DES_REG4() (REG32(ADR_WIFI_PHY_COMMON_DES_REG4)) = (0x00000001) #define DEF_WIFI_PHY_COMMON_TX_CONTROL() (REG32(ADR_WIFI_PHY_COMMON_TX_CONTROL)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_DES_REG5() (REG32(ADR_WIFI_PHY_COMMON_DES_REG5)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_DES_REG6() (REG32(ADR_WIFI_PHY_COMMON_DES_REG6)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RFAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG0)) = (0x80046771) #define DEF_WIFI_PHY_COMMON_RFAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG1)) = (0x80046771) #define DEF_WIFI_PHY_COMMON_RFAGC_REG2() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG2)) = (0x1f300f6f) #define DEF_WIFI_PHY_COMMON_RFAGC_REG3() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG3)) = (0x663f36d0) #define DEF_WIFI_PHY_COMMON_RFAGC_REG4() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_REG4)) = (0x100c0000) #define DEF_WIFI_PHY_COMMON_11B_DAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG0)) = (0x01603fff) #define DEF_WIFI_PHY_COMMON_11B_DAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_11B_DAGC_REG1)) = (0x00080860) #define DEF_WIFI_PHY_COMMON_11GN20_DAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG0)) = (0xff000160) #define DEF_WIFI_PHY_COMMON_11GN20_DAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_11GN20_DAGC_REG1)) = (0x00100040) #define DEF_WIFI_PHY_COMMON_11BGN_DIGPWR_REG() (REG32(ADR_WIFI_PHY_COMMON_11BGN_DIGPWR_REG)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RFAGC_RO00() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO00)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RFAGC_RO01() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO01)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RFAGC_RO02() (REG32(ADR_WIFI_PHY_COMMON_RFAGC_RO02)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RXDC() (REG32(ADR_WIFI_PHY_COMMON_RXDC)) = (0x12301230) #define DEF_WIFI_PHY_COMMON_RXDC_RO() (REG32(ADR_WIFI_PHY_COMMON_RXDC_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RSSI_TBUS_REG() (REG32(ADR_WIFI_PHY_COMMON_RSSI_TBUS_REG)) = (0x00fc000f) #define DEF_WIFI_PHY_COMMON_RX_EN_CNT_REG() (REG32(ADR_WIFI_PHY_COMMON_RX_EN_CNT_REG)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_EDCCA_0() (REG32(ADR_WIFI_PHY_COMMON_EDCCA_0)) = (0x00000004) #define DEF_WIFI_PHY_COMMON_EDCCA_1() (REG32(ADR_WIFI_PHY_COMMON_EDCCA_1)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_EDCCA_2() (REG32(ADR_WIFI_PHY_COMMON_EDCCA_2)) = (0x00000000) #define DEF_WIFI_PHY_AGC_RELOCK_1() (REG32(ADR_WIFI_PHY_AGC_RELOCK_1)) = (0x00102000) #define DEF_WIFI_PHY_AGC_RELOCK_2() (REG32(ADR_WIFI_PHY_AGC_RELOCK_2)) = (0x00100018) #define DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0() (REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG0)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1() (REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_REG1)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0() (REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG0)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1() (REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_REG1)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_TX_LENGTH_CNT_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_RX_LENGTH_CNT_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG() (REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_REG)) = (0x0cff0cff) #define DEF_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_TRX_TYPE_CNT_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_11GN40_DAGC_REG0() (REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG0)) = (0x00000160) #define DEF_WIFI_PHY_COMMON_11GN40_DAGC_REG1() (REG32(ADR_WIFI_PHY_COMMON_11GN40_DAGC_REG1)) = (0x00100040) #define DEF_WIFI_PHY_COMMON_11GN_DAGC_INI_REG() (REG32(ADR_WIFI_PHY_COMMON_11GN_DAGC_INI_REG)) = (0x00100010) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_0() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_0)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_1() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_1)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_2() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_2)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_3() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_3)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_4() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_4)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_5() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_5)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_6() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_6)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_7() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_7)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_8() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_8)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_9() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_9)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_PKT_REG_A() (REG32(ADR_WIFI_PHY_COMMON_MAC_PKT_REG_A)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_0() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_0)) = (0x00000080) #define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_1() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_1)) = (0x80808080) #define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_2() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_2)) = (0x80808080) #define DEF_WIFI_PHY_COMMON_BB_SCALE_REG_3() (REG32(ADR_WIFI_PHY_COMMON_BB_SCALE_REG_3)) = (0x80808080) #define DEF_WIFI_PHY_COMMON_RF_PWR_REG_0() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_0)) = (0x0000007f) #define DEF_WIFI_PHY_COMMON_RF_PWR_REG_1() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_1)) = (0x7f7f7f7f) #define DEF_WIFI_PHY_COMMON_RF_PWR_REG_2() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_2)) = (0x7f7f7f7f) #define DEF_WIFI_PHY_COMMON_RF_PWR_REG_3() (REG32(ADR_WIFI_PHY_COMMON_RF_PWR_REG_3)) = (0x7f7f7f7f) #define DEF_WIFI_PHY_COMMON_RX_MON_0() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_0)) = (0x03e83ffe) #define DEF_WIFI_PHY_COMMON_RX_MON_1() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_1)) = (0x00640005) #define DEF_WIFI_PHY_COMMON_RX_MON_2() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_2)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_MON_3() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_3)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_MON_4() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_4)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_MON_5() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_5)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_MON_6() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_6)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_MON_7() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_7)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_MON_8() (REG32(ADR_WIFI_PHY_COMMON_RX_MON_8)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_TMR_MON_RO() (REG32(ADR_WIFI_PHY_COMMON_RX_TMR_MON_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_BKN_MON_RO() (REG32(ADR_WIFI_PHY_COMMON_RX_BKN_MON_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL() (REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_CTRL)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_MAC_IF_CNT_RO() (REG32(ADR_WIFI_PHY_COMMON_MAC_IF_CNT_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG() (REG32(ADR_WIFI_PHY_COMMON_RX_FFT_MEM_BIST_REG)) = (0x00000000) #define DEF_WIFI_PHY_AUDIO_CLK_CTRL() (REG32(ADR_WIFI_PHY_AUDIO_CLK_CTRL)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_TOP_STATUS_RO() (REG32(ADR_WIFI_PHY_COMMON_TOP_STATUS_RO)) = (0x00000000) #define DEF_WIFI_PHY_COMMON_RESERVED_REG() (REG32(ADR_WIFI_PHY_COMMON_RESERVED_REG)) = (0x00000000) #define DEF_WIFI_11B_TX_BB_RAMP_REG() (REG32(ADR_WIFI_11B_TX_BB_RAMP_REG)) = (0x00003c40) #define DEF_WIFI_11B_TX_PKT_CNT_SENT_REG() (REG32(ADR_WIFI_11B_TX_PKT_CNT_SENT_REG)) = (0x00000000) #define DEF_WIFI_11B_TX_DEBUG_SEL_REG() (REG32(ADR_WIFI_11B_TX_DEBUG_SEL_REG)) = (0x00000000) #define DEF_WIFI_11B_TX_RESERVED_REG() (REG32(ADR_WIFI_11B_TX_RESERVED_REG)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_000() (REG32(ADR_WIFI_11B_RX_REG_000)) = (0x00000244) #define DEF_WIFI_11B_RX_REG_001() (REG32(ADR_WIFI_11B_RX_REG_001)) = (0x00040000) #define DEF_WIFI_11B_RX_REG_002() (REG32(ADR_WIFI_11B_RX_REG_002)) = (0x00400040) #define DEF_WIFI_11B_RX_REG_003() (REG32(ADR_WIFI_11B_RX_REG_003)) = (0x00003467) #define DEF_WIFI_11B_RX_REG_004() (REG32(ADR_WIFI_11B_RX_REG_004)) = (0x00550000) #define DEF_WIFI_11B_RX_REG_005() (REG32(ADR_WIFI_11B_RX_REG_005)) = (0x20000015) #define DEF_WIFI_11B_RX_REG_006() (REG32(ADR_WIFI_11B_RX_REG_006)) = (0x00390002) #define DEF_WIFI_11B_RX_REG_007() (REG32(ADR_WIFI_11B_RX_REG_007)) = (0x03030004) #define DEF_WIFI_11B_RX_REG_008() (REG32(ADR_WIFI_11B_RX_REG_008)) = (0x00350046) #define DEF_WIFI_11B_RX_REG_009() (REG32(ADR_WIFI_11B_RX_REG_009)) = (0x00350046) #define DEF_WIFI_11B_RX_REG_010() (REG32(ADR_WIFI_11B_RX_REG_010)) = (0x00236700) #define DEF_WIFI_11B_RX_REG_011() (REG32(ADR_WIFI_11B_RX_REG_011)) = (0x000d1746) #define DEF_WIFI_11B_RX_REG_012() (REG32(ADR_WIFI_11B_RX_REG_012)) = (0x04061787) #define DEF_WIFI_11B_RX_REG_013() (REG32(ADR_WIFI_11B_RX_REG_013)) = (0x07800000) #define DEF_WIFI_11B_RX_REG_014() (REG32(ADR_WIFI_11B_RX_REG_014)) = (0x00000067) #define DEF_WIFI_11B_RX_REG_039() (REG32(ADR_WIFI_11B_RX_REG_039)) = (0x00c0000a) #define DEF_WIFI_11B_RX_REG_040() (REG32(ADR_WIFI_11B_RX_REG_040)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_041() (REG32(ADR_WIFI_11B_RX_REG_041)) = (0x00000006) #define DEF_WIFI_11B_RX_REG_240() (REG32(ADR_WIFI_11B_RX_REG_240)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_241() (REG32(ADR_WIFI_11B_RX_REG_241)) = (0x00000f10) #define DEF_WIFI_11B_RX_REG_244() (REG32(ADR_WIFI_11B_RX_REG_244)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_245() (REG32(ADR_WIFI_11B_RX_REG_245)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_246() (REG32(ADR_WIFI_11B_RX_REG_246)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_249() (REG32(ADR_WIFI_11B_RX_REG_249)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_250() (REG32(ADR_WIFI_11B_RX_REG_250)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_251() (REG32(ADR_WIFI_11B_RX_REG_251)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_252() (REG32(ADR_WIFI_11B_RX_REG_252)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_253() (REG32(ADR_WIFI_11B_RX_REG_253)) = (0x00000000) #define DEF_WIFI_11B_RX_REG_254() (REG32(ADR_WIFI_11B_RX_REG_254)) = (0x00100000) #define DEF_WIFI_11B_RX_REG_255() (REG32(ADR_WIFI_11B_RX_REG_255)) = (0x00000001) #define DEF_WIFI_11GN_TX_MEM_BIST_REG() (REG32(ADR_WIFI_11GN_TX_MEM_BIST_REG)) = (0x00000000) #define DEF_WIFI_11GN_TX_BB_RAMP_REG() (REG32(ADR_WIFI_11GN_TX_BB_RAMP_REG)) = (0x0000233c) #define DEF_WIFI_11GN_TX_CONTROL_REG() (REG32(ADR_WIFI_11GN_TX_CONTROL_REG)) = (0x00000011) #define DEF_WIFI_11GN_TX_STS_SCALE_REG() (REG32(ADR_WIFI_11GN_TX_STS_SCALE_REG)) = (0x01b001b0) #define DEF_WIFI_11GN_TX_FFT_SCALE_REG0() (REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG0)) = (0x0096009d) #define DEF_WIFI_11GN_TX_FFT_SCALE_REG1() (REG32(ADR_WIFI_11GN_TX_FFT_SCALE_REG1)) = (0x7f0c50cc) #define DEF_WIFI_11GN_TX_PKT_CNT_SENT_REG() (REG32(ADR_WIFI_11GN_TX_PKT_CNT_SENT_REG)) = (0x00000000) #define DEF_WIFI_11GN_TX_DEBUG_SEL_REG() (REG32(ADR_WIFI_11GN_TX_DEBUG_SEL_REG)) = (0x00000000) #define DEF_WIFI_11GN_TX_RESERVED_REG() (REG32(ADR_WIFI_11GN_TX_RESERVED_REG)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_000() (REG32(ADR_WIFI_11GN_RX_REG_000)) = (0x00000044) #define DEF_WIFI_11GN_RX_REG_001() (REG32(ADR_WIFI_11GN_RX_REG_001)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_002() (REG32(ADR_WIFI_11GN_RX_REG_002)) = (0x00004775) #define DEF_WIFI_11GN_RX_REG_003() (REG32(ADR_WIFI_11GN_RX_REG_003)) = (0x10000075) #define DEF_WIFI_11GN_RX_REG_004_() (REG32(ADR_WIFI_11GN_RX_REG_004_)) = (0x38324705) #define DEF_WIFI_11GN_RX_REG_005() (REG32(ADR_WIFI_11GN_RX_REG_005)) = (0x30182000) #define DEF_WIFI_11GN_RX_REG_006_() (REG32(ADR_WIFI_11GN_RX_REG_006_)) = (0x20600000) #define DEF_WIFI_11GN_RX_REG_007_() (REG32(ADR_WIFI_11GN_RX_REG_007_)) = (0x0a010080) #define DEF_WIFI_11GN_RX_REG_008() (REG32(ADR_WIFI_11GN_RX_REG_008)) = (0x50505050) #define DEF_WIFI_11GN_RX_REG_009() (REG32(ADR_WIFI_11GN_RX_REG_009)) = (0x50000000) #define DEF_WIFI_11GN_RX_REG_010_() (REG32(ADR_WIFI_11GN_RX_REG_010_)) = (0x50505050) #define DEF_WIFI_11GN_RX_REG_011() (REG32(ADR_WIFI_11GN_RX_REG_011)) = (0x50505050) #define DEF_WIFI_11GN_RX_REG_012() (REG32(ADR_WIFI_11GN_RX_REG_012)) = (0x50000000) #define DEF_WIFI_11GN_RX_REG_013() (REG32(ADR_WIFI_11GN_RX_REG_013)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_014() (REG32(ADR_WIFI_11GN_RX_REG_014)) = (0x00001420) #define DEF_WIFI_11GN_RX_REG_015() (REG32(ADR_WIFI_11GN_RX_REG_015)) = (0x00000040) #define DEF_WIFI_11GN_RX_REG_016() (REG32(ADR_WIFI_11GN_RX_REG_016)) = (0x7f7f7f7f) #define DEF_WIFI_11GN_RX_REG_017() (REG32(ADR_WIFI_11GN_RX_REG_017)) = (0x7f7f7f7f) #define DEF_WIFI_11GN_RX_REG_032() (REG32(ADR_WIFI_11GN_RX_REG_032)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_033() (REG32(ADR_WIFI_11GN_RX_REG_033)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_039() (REG32(ADR_WIFI_11GN_RX_REG_039)) = (0x0000200a) #define DEF_WIFI_11GN_RX_REG_040() (REG32(ADR_WIFI_11GN_RX_REG_040)) = (0x00000280) #define DEF_WIFI_11GN_RX_REG_048() (REG32(ADR_WIFI_11GN_RX_REG_048)) = (0x30000280) #define DEF_WIFI_11GN_RX_REG_049() (REG32(ADR_WIFI_11GN_RX_REG_049)) = (0x30023002) #define DEF_WIFI_11GN_RX_REG_050() (REG32(ADR_WIFI_11GN_RX_REG_050)) = (0x0000003a) #define DEF_WIFI_11GN_RX_REG_051() (REG32(ADR_WIFI_11GN_RX_REG_051)) = (0x00200120) #define DEF_WIFI_11GN_RX_REG_052() (REG32(ADR_WIFI_11GN_RX_REG_052)) = (0x00000120) #define DEF_WIFI_11GN_RX_REG_076() (REG32(ADR_WIFI_11GN_RX_REG_076)) = (0x40000000) #define DEF_WIFI_11GN_RX_REG_087() (REG32(ADR_WIFI_11GN_RX_REG_087)) = (0x01080110) #define DEF_WIFI_11GN_RX_REG_088() (REG32(ADR_WIFI_11GN_RX_REG_088)) = (0x00180120) #define DEF_WIFI_11GN_RX_REG_089() (REG32(ADR_WIFI_11GN_RX_REG_089)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_096() (REG32(ADR_WIFI_11GN_RX_REG_096)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_098() (REG32(ADR_WIFI_11GN_RX_REG_098)) = (0x02000000) #define DEF_WIFI_11GN_RX_REG_100() (REG32(ADR_WIFI_11GN_RX_REG_100)) = (0x02003030) #define DEF_WIFI_11GN_RX_REG_101() (REG32(ADR_WIFI_11GN_RX_REG_101)) = (0x09360000) #define DEF_WIFI_11GN_RX_REG_102() (REG32(ADR_WIFI_11GN_RX_REG_102)) = (0xff0cfc8c) #define DEF_WIFI_11GN_RX_REG_103() (REG32(ADR_WIFI_11GN_RX_REG_103)) = (0x0000fb88) #define DEF_WIFI_11GN_RX_REG_241() (REG32(ADR_WIFI_11GN_RX_REG_241)) = (0x00000f10) #define DEF_WIFI_11GN_RX_REG_244() (REG32(ADR_WIFI_11GN_RX_REG_244)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_245() (REG32(ADR_WIFI_11GN_RX_REG_245)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_246() (REG32(ADR_WIFI_11GN_RX_REG_246)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_247() (REG32(ADR_WIFI_11GN_RX_REG_247)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_248() (REG32(ADR_WIFI_11GN_RX_REG_248)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_249() (REG32(ADR_WIFI_11GN_RX_REG_249)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_250() (REG32(ADR_WIFI_11GN_RX_REG_250)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_251() (REG32(ADR_WIFI_11GN_RX_REG_251)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_252() (REG32(ADR_WIFI_11GN_RX_REG_252)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_253() (REG32(ADR_WIFI_11GN_RX_REG_253)) = (0x00000000) #define DEF_WIFI_11GN_RX_REG_254() (REG32(ADR_WIFI_11GN_RX_REG_254)) = (0x00100001) #define DEF_WIFI_11GN_RX_REG_255() (REG32(ADR_WIFI_11GN_RX_REG_255)) = (0x00000001) #define DEF_WIFI_RADAR_REG_00() (REG32(ADR_WIFI_RADAR_REG_00)) = (0x4d4d0d0a) #define DEF_WIFI_RADAR_REG_01() (REG32(ADR_WIFI_RADAR_REG_01)) = (0x07ee0007) #define DEF_WIFI_RADAR_REG_02() (REG32(ADR_WIFI_RADAR_REG_02)) = (0x0834002d) #define DEF_WIFI_RADAR_REG_03() (REG32(ADR_WIFI_RADAR_REG_03)) = (0x20600e74) #define DEF_WIFI_RADAR_REG_04() (REG32(ADR_WIFI_RADAR_REG_04)) = (0x04080000) #define DEF_WIFI_RADAR_REG_RO() (REG32(ADR_WIFI_RADAR_REG_RO)) = (0x00000000) #define DEF_WIFI_RADAR_REG_DB_A0_RO() (REG32(ADR_WIFI_RADAR_REG_DB_A0_RO)) = (0x00000000) #define DEF_WIFI_RADAR_REG_DB_A1_RO() (REG32(ADR_WIFI_RADAR_REG_DB_A1_RO)) = (0x00000000) #define DEF_WIFI_RADAR_REG_DB_A2_RO() (REG32(ADR_WIFI_RADAR_REG_DB_A2_RO)) = (0x00000000) #define DEF_WIFI_RADAR_REG_DB_P0_RO() (REG32(ADR_WIFI_RADAR_REG_DB_P0_RO)) = (0x00000000) #define DEF_WIFI_RADAR_REG_DB_P1_RO() (REG32(ADR_WIFI_RADAR_REG_DB_P1_RO)) = (0x00000000) #define DEF_WIFI_RADAR_REG_DB_P2_RO() (REG32(ADR_WIFI_RADAR_REG_DB_P2_RO)) = (0x00000000) #define DEF_WIFI_RADAR_CHIRP_REG() (REG32(ADR_WIFI_RADAR_CHIRP_REG)) = (0x07d003e8) #define DEF_MB_CPU_INT_ALT() (REG32(ADR_MB_CPU_INT_ALT)) = (0x00000000) #define DEF_MB_CPU_INT() (REG32(ADR_MB_CPU_INT)) = (0x00000000) #define DEF_CPU_ID_TB0() (REG32(ADR_CPU_ID_TB0)) = (0x00000000) #define DEF_CPU_ID_TB1() (REG32(ADR_CPU_ID_TB1)) = (0x00000000) #define DEF_CH0_TRIG_1() (REG32(ADR_CH0_TRIG_1)) = (0x00000000) #define DEF_CH0_TRIG_0() (REG32(ADR_CH0_TRIG_0)) = (0x00000000) #define DEF_CH0_PRI_TRIG() (REG32(ADR_CH0_PRI_TRIG)) = (0x00000000) #define DEF_MCU_STATUS() (REG32(ADR_MCU_STATUS)) = (0x00000000) #define DEF_RD_IN_FFCNT1() (REG32(ADR_RD_IN_FFCNT1)) = (0x00000000) #define DEF_RD_IN_FFCNT2() (REG32(ADR_RD_IN_FFCNT2)) = (0x00000000) #define DEF_RD_FFIN_FULL() (REG32(ADR_RD_FFIN_FULL)) = (0x00000000) #define DEF_CH2_TRIG_ALT() (REG32(ADR_CH2_TRIG_ALT)) = (0x00000000) #define DEF_CH2_INT_ADDR_ALT() (REG32(ADR_CH2_INT_ADDR_ALT)) = (0x00000000) #define DEF_MBOX_HALT_CFG() (REG32(ADR_MBOX_HALT_CFG)) = (0x00000000) #define DEF_MBOX_HALT_STS() (REG32(ADR_MBOX_HALT_STS)) = (0x00000000) #define DEF_MB_DBG_CFG1() (REG32(ADR_MB_DBG_CFG1)) = (0x00080000) #define DEF_MB_DBG_CFG2() (REG32(ADR_MB_DBG_CFG2)) = (0x00000000) #define DEF_MB_DBG_CFG3() (REG32(ADR_MB_DBG_CFG3)) = (0x00000000) #define DEF_MB_DBG_CFG4() (REG32(ADR_MB_DBG_CFG4)) = (0xffffffff) #define DEF_MB_OUT_QUEUE_CFG() (REG32(ADR_MB_OUT_QUEUE_CFG)) = (0x00000002) #define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000) #define DEF_MB_OUT_QUEUE_FLUSH() (REG32(ADR_MB_OUT_QUEUE_FLUSH)) = (0x00000000) #define DEF_RD_FFOUT_CNT1() (REG32(ADR_RD_FFOUT_CNT1)) = (0x00000000) #define DEF_RD_FFOUT_CNT2() (REG32(ADR_RD_FFOUT_CNT2)) = (0x00000000) #define DEF_RD_FFOUT_CNT3() (REG32(ADR_RD_FFOUT_CNT3)) = (0x00000000) #define DEF_RD_FFOUT_FULL() (REG32(ADR_RD_FFOUT_FULL)) = (0x00000000) #define DEF_MB_THRESHOLD6() (REG32(ADR_MB_THRESHOLD6)) = (0x00000000) #define DEF_MB_THRESHOLD7() (REG32(ADR_MB_THRESHOLD7)) = (0x00000000) #define DEF_MB_THRESHOLD8() (REG32(ADR_MB_THRESHOLD8)) = (0x00000000) #define DEF_MB_THRESHOLD9() (REG32(ADR_MB_THRESHOLD9)) = (0x00000000) #define DEF_MB_THRESHOLD10() (REG32(ADR_MB_THRESHOLD10)) = (0x00000000) #define DEF_MB_TRASH_CFG() (REG32(ADR_MB_TRASH_CFG)) = (0x01000001) #define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000) #define DEF_MB_IN_FF_FLUSH() (REG32(ADR_MB_IN_FF_FLUSH)) = (0x00000000) #define DEF_CPU_ID_TB2() (REG32(ADR_CPU_ID_TB2)) = (0x00000000) #define DEF_CPU_ID_TB3() (REG32(ADR_CPU_ID_TB3)) = (0x00000000) #define DEF_PHY_IQ_LOG_CFG0() (REG32(ADR_PHY_IQ_LOG_CFG0)) = (0x00000000) #define DEF_PHY_IQ_LOG_CFG1() (REG32(ADR_PHY_IQ_LOG_CFG1)) = (0x00000000) #define DEF_PHY_IQ_LOG_LEN() (REG32(ADR_PHY_IQ_LOG_LEN)) = (0x00001000) #define DEF_PHY_IQ_LOG_PTR() (REG32(ADR_PHY_IQ_LOG_PTR)) = (0x00000000) #define DEF_WR_ALC() (REG32(ADR_WR_ALC)) = (0x00000000) #define DEF_GETID() (REG32(ADR_GETID)) = (0x00000000) #define DEF_CH_STA_PRI() (REG32(ADR_CH_STA_PRI)) = (0x00000213) #define DEF_RD_ID0() (REG32(ADR_RD_ID0)) = (0x00000000) #define DEF_RD_ID1() (REG32(ADR_RD_ID1)) = (0x00000000) #define DEF_IMD_CFG() (REG32(ADR_IMD_CFG)) = (0x00000000) #define DEF_IMD_STA() (REG32(ADR_IMD_STA)) = (0x00000000) #define DEF_ALC_STA() (REG32(ADR_ALC_STA)) = (0x01000000) #define DEF_TRX_ID_COUNT() (REG32(ADR_TRX_ID_COUNT)) = (0x00000000) #define DEF_TRX_ID_THRESHOLD() (REG32(ADR_TRX_ID_THRESHOLD)) = (0x01ee3c3c) #define DEF_TX_ID0() (REG32(ADR_TX_ID0)) = (0x00000000) #define DEF_TX_ID1() (REG32(ADR_TX_ID1)) = (0x00000000) #define DEF_RX_ID0() (REG32(ADR_RX_ID0)) = (0x00000000) #define DEF_RX_ID1() (REG32(ADR_RX_ID1)) = (0x00000000) #define DEF_RTN_STA() (REG32(ADR_RTN_STA)) = (0x00000001) #define DEF_ID_LEN_THREADSHOLD1() (REG32(ADR_ID_LEN_THREADSHOLD1)) = (0x000f0641) #define DEF_ID_LEN_THREADSHOLD2() (REG32(ADR_ID_LEN_THREADSHOLD2)) = (0x00000000) #define DEF_CH_ARB_PRI() (REG32(ADR_CH_ARB_PRI)) = (0x00031201) #define DEF_TX_ID_REMAIN_STATUS() (REG32(ADR_TX_ID_REMAIN_STATUS)) = (0x00000000) #define DEF_ID_INFO_STA() (REG32(ADR_ID_INFO_STA)) = (0x00000100) #define DEF_TX_LIMIT_INTR() (REG32(ADR_TX_LIMIT_INTR)) = (0x00000000) #define DEF_TX_ID_ALL_INFO() (REG32(ADR_TX_ID_ALL_INFO)) = (0x00000000) #define DEF_RD_ID2() (REG32(ADR_RD_ID2)) = (0x00000000) #define DEF_RD_ID3() (REG32(ADR_RD_ID3)) = (0x00000000) #define DEF_TX_ID2() (REG32(ADR_TX_ID2)) = (0x00000000) #define DEF_TX_ID3() (REG32(ADR_TX_ID3)) = (0x00000000) #define DEF_RX_ID2() (REG32(ADR_RX_ID2)) = (0x00000000) #define DEF_RX_ID3() (REG32(ADR_RX_ID3)) = (0x00000000) #define DEF_TX_ID_ALL_INFO2() (REG32(ADR_TX_ID_ALL_INFO2)) = (0x00000000) #define DEF_TX_ID_ALL_INFO_A() (REG32(ADR_TX_ID_ALL_INFO_A)) = (0x00000000) #define DEF_TX_ID_ALL_INFO_B() (REG32(ADR_TX_ID_ALL_INFO_B)) = (0x00000000) #define DEF_TX_ID_REMAIN_STATUS2() (REG32(ADR_TX_ID_REMAIN_STATUS2)) = (0x01000100) #define DEF_ALC_ID_INFO() (REG32(ADR_ALC_ID_INFO)) = (0x00000000) #define DEF_ALC_ID_INF1() (REG32(ADR_ALC_ID_INF1)) = (0x00000000) #define DEF_ALC_ABORT() (REG32(ADR_ALC_ABORT)) = (0x00000000) #define DEF_ALC_RLS_STATUS() (REG32(ADR_ALC_RLS_STATUS)) = (0x00000000) #define DEF_DMN_STATUS() (REG32(ADR_DMN_STATUS)) = (0x00007ff0) #define DEF_TAG_STATUS() (REG32(ADR_TAG_STATUS)) = (0x00000000) #define DEF_REQ_STATUS() (REG32(ADR_REQ_STATUS)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_0() (REG32(ADR_PAGE_TAG_STATUS_0)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_1() (REG32(ADR_PAGE_TAG_STATUS_1)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_2() (REG32(ADR_PAGE_TAG_STATUS_2)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_3() (REG32(ADR_PAGE_TAG_STATUS_3)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_4() (REG32(ADR_PAGE_TAG_STATUS_4)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_5() (REG32(ADR_PAGE_TAG_STATUS_5)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_6() (REG32(ADR_PAGE_TAG_STATUS_6)) = (0x00000000) #define DEF_PAGE_TAG_STATUS_7() (REG32(ADR_PAGE_TAG_STATUS_7)) = (0x00000000) #define DEF_FPGA_GEMINIARF_SWITCH() (REG32(ADR_FPGA_GEMINIARF_SWITCH)) = (0x00000000) // the following is for run-time accesses //struct for FBUS_DMAC_REG //struct for SBUS_DMAC_REG //struct for I2S_TRX_REG //struct for I2CMST_REG //struct for SPIMST_REG //struct for USB20_REG //struct for SYS_REG //struct for CSR_ALLON //struct for TU0_US_REG //struct for TU1_US_REG //struct for TU2_US_REG //struct for TU3_US_REG //struct for TM0_MS_REG //struct for TM1_MS_REG //struct for TM2_MS_REG //struct for TM3_MS_REG //struct for MCU_WDT_REG //struct for SYS_WDT_REG //struct for PWM_REG //struct for IO_REG //struct for CSR_I2C_SLV //struct for SD_REG //struct for SPI_REG //struct for CSR_I2C_MST //struct for UART_REG //struct for DAT_UART_REG //struct for FLASH_SPI_REG //struct for DMA_REG //struct for D2_DMA_REG //struct for INT_CTRL_REG //struct for SYS_UTILS //struct for RTC_MISC_REG //struct for HCI_REG //struct for CO_REG //struct for EFS_REG //struct for CSR_SPIMAS //struct for SPIMAS_TX_BUF //struct for SPIMAS_RX_BUF //struct for MRX_REG //struct for AMPDU_REG //struct for MT_REG_CSR //struct for TXQ0_MT_Q_REG_CSR //struct for TXQ1_MT_Q_REG_CSR //struct for TXQ2_MT_Q_REG_CSR //struct for TXQ3_MT_Q_REG_CSR //struct for TXQ4_MT_Q_REG_CSR //struct for TXQ5_MT_Q_REG_CSR //struct for MT_RESPFRM_REG //struct for HIF_INFO //struct for PHY_RATE_INFO //struct for MAC_GLB_SET //struct for BTCX_REG //struct for MIB_REG //struct for WSID_EXT //struct for RF_REG //struct for CSR_TU_RF //struct for CSR_TU_PMU //struct for CSR_TU_PHY //struct for MB_REG //struct for ID_MNG_REG //struct for MMU_REG //struct for CSR_TEMP_REG //struct base for FBUS_DMAC_REG //struct base for SBUS_DMAC_REG //struct base for I2S_TRX_REG //struct base for I2CMST_REG //struct base for SPIMST_REG //struct base for USB20_REG //struct base for SYS_REG //struct base for CSR_ALLON //struct base for TU0_US_REG //struct base for TU1_US_REG //struct base for TU2_US_REG //struct base for TU3_US_REG //struct base for TM0_MS_REG //struct base for TM1_MS_REG //struct base for TM2_MS_REG //struct base for TM3_MS_REG //struct base for MCU_WDT_REG //struct base for SYS_WDT_REG //struct base for PWM_REG //struct base for IO_REG //struct base for CSR_I2C_SLV //struct base for SD_REG //struct base for SPI_REG //struct base for CSR_I2C_MST //struct base for UART_REG //struct base for DAT_UART_REG //struct base for FLASH_SPI_REG //struct base for DMA_REG //struct base for D2_DMA_REG //struct base for INT_CTRL_REG //struct base for SYS_UTILS //struct base for RTC_MISC_REG //struct base for HCI_REG //struct base for CO_REG //struct base for EFS_REG //struct base for CSR_SPIMAS //struct base for SPIMAS_TX_BUF //struct base for SPIMAS_RX_BUF //struct base for MRX_REG //struct base for AMPDU_REG //struct base for MT_REG_CSR //struct base for TXQ0_MT_Q_REG_CSR //struct base for TXQ1_MT_Q_REG_CSR //struct base for TXQ2_MT_Q_REG_CSR //struct base for TXQ3_MT_Q_REG_CSR //struct base for TXQ4_MT_Q_REG_CSR //struct base for TXQ5_MT_Q_REG_CSR //struct base for MT_RESPFRM_REG //struct base for HIF_INFO //struct base for PHY_RATE_INFO //struct base for MAC_GLB_SET //struct base for BTCX_REG //struct base for MIB_REG //struct base for WSID_EXT //struct base for RF_REG //struct base for CSR_TU_RF //struct base for CSR_TU_PMU //struct base for CSR_TU_PHY //struct base for MB_REG //struct base for ID_MNG_REG //struct base for MMU_REG //struct base for CSR_TEMP_REG //ssv struct base for FBUS_DMAC_REG //ssv struct base for SBUS_DMAC_REG //ssv struct base for I2S_TRX_REG //ssv struct base for I2CMST_REG //ssv struct base for SPIMST_REG //ssv struct base for USB20_REG //ssv struct base for SYS_REG //ssv struct base for CSR_ALLON //ssv struct base for TU0_US_REG //ssv struct base for TU1_US_REG //ssv struct base for TU2_US_REG //ssv struct base for TU3_US_REG //ssv struct base for TM0_MS_REG //ssv struct base for TM1_MS_REG //ssv struct base for TM2_MS_REG //ssv struct base for TM3_MS_REG //ssv struct base for MCU_WDT_REG //ssv struct base for SYS_WDT_REG //ssv struct base for PWM_REG //ssv struct base for IO_REG //ssv struct base for CSR_I2C_SLV //ssv struct base for SD_REG //ssv struct base for SPI_REG //ssv struct base for CSR_I2C_MST //ssv struct base for UART_REG //ssv struct base for DAT_UART_REG //ssv struct base for FLASH_SPI_REG //ssv struct base for DMA_REG //ssv struct base for D2_DMA_REG //ssv struct base for INT_CTRL_REG //ssv struct base for SYS_UTILS //ssv struct base for RTC_MISC_REG //ssv struct base for HCI_REG //ssv struct base for CO_REG //ssv struct base for EFS_REG //ssv struct base for CSR_SPIMAS //ssv struct base for SPIMAS_TX_BUF //ssv struct base for SPIMAS_RX_BUF //ssv struct base for MRX_REG //ssv struct base for AMPDU_REG //ssv struct base for MT_REG_CSR //ssv struct base for TXQ0_MT_Q_REG_CSR //ssv struct base for TXQ1_MT_Q_REG_CSR //ssv struct base for TXQ2_MT_Q_REG_CSR //ssv struct base for TXQ3_MT_Q_REG_CSR //ssv struct base for TXQ4_MT_Q_REG_CSR //ssv struct base for TXQ5_MT_Q_REG_CSR //ssv struct base for MT_RESPFRM_REG //ssv struct base for HIF_INFO //ssv struct base for PHY_RATE_INFO //ssv struct base for MAC_GLB_SET //ssv struct base for BTCX_REG //ssv struct base for MIB_REG //ssv struct base for WSID_EXT //ssv struct base for RF_REG //ssv struct base for CSR_TU_RF //ssv struct base for CSR_TU_PMU //ssv struct base for CSR_TU_PHY //ssv struct base for MB_REG //ssv struct base for ID_MNG_REG //ssv struct base for MMU_REG //ssv struct base for CSR_TEMP_REG