8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _UAPI__RK_PCIE_EP_H__
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#define _UAPI__RK_PCIE_EP_H__
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#include <linux/types.h>
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/*
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* rockchip pcie driver elbi ioctrl output data
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*/
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struct pcie_ep_user_data {
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__u64 bar0_phys_addr;
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__u32 elbi_app_user[11];
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};
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/*
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* rockchip driver cache ioctrl input param
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*/
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struct pcie_ep_dma_cache_cfg {
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__u64 addr;
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__u32 size;
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};
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#define PCIE_EP_OBJ_INFO_MAGIC 0x524B4550
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enum pcie_ep_obj_irq_type {
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OBJ_IRQ_UNKNOWN,
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OBJ_IRQ_DMA,
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OBJ_IRQ_USER,
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OBJ_IRQ_ELBI,
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};
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struct pcie_ep_obj_irq_dma_status {
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__u32 wr;
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__u32 rd;
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};
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enum pcie_ep_mmap_resource {
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PCIE_EP_MMAP_RESOURCE_DBI,
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PCIE_EP_MMAP_RESOURCE_BAR0,
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PCIE_EP_MMAP_RESOURCE_BAR2,
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PCIE_EP_MMAP_RESOURCE_BAR4,
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PCIE_EP_MMAP_RESOURCE_MAX,
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};
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/*
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* rockchip ep device information which is store in BAR0
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*/
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struct pcie_ep_obj_info {
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__u32 magic;
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__u32 version;
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__u8 reserved[0x1F8];
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__u32 irq_type_rc; /* Generate in ep isr, valid only for rc, clear in rc */
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struct pcie_ep_obj_irq_dma_status dma_status_rc; /* Generate in ep isr, valid only for rc, clear in rc */
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__u32 irq_type_ep; /* Generate in ep isr, valid only for ep, clear in ep */
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struct pcie_ep_obj_irq_dma_status dma_status_ep; /* Generate in ep isr, valid only for ep, clear in ep */
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__u32 obj_irq_user_data; /* OBJ_IRQ_USER userspace data */
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};
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#define PCIE_BASE 'P'
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#define PCIE_DMA_GET_ELBI_DATA _IOR(PCIE_BASE, 0, struct pcie_ep_user_data)
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#define PCIE_DMA_CACHE_INVALIDE _IOW(PCIE_BASE, 1, struct pcie_ep_dma_cache_cfg)
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#define PCIE_DMA_CACHE_FLUSH _IOW(PCIE_BASE, 2, struct pcie_ep_dma_cache_cfg)
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#define PCIE_DMA_IRQ_MASK_ALL _IOW(PCIE_BASE, 3, int)
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#define PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER _IOW(PCIE_BASE, 4, int)
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#define PCIE_EP_GET_USER_INFO _IOR(PCIE_BASE, 5, struct pcie_ep_user_data)
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#define PCIE_EP_SET_MMAP_RESOURCE _IOW(PCIE_BASE, 6, enum pcie_ep_mmap_resource)
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#endif
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