project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/**
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******************************************************************************
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*
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* @file rwnx_irqs.c
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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******************************************************************************
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*/
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#include <linux/interrupt.h>
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#include "rwnx_defs.h"
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#include "ipc_host.h"
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#include "rwnx_prof.h"
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/**
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* rwnx_irq_hdlr - IRQ handler
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*
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* Handler registerd by the platform driver
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*/
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irqreturn_t rwnx_irq_hdlr(int irq, void *dev_id)
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{
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struct rwnx_hw *rwnx_hw = (struct rwnx_hw *)dev_id;
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disable_irq_nosync(irq);
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tasklet_schedule(&rwnx_hw->task);
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return IRQ_HANDLED;
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}
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/**
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* rwnx_task - Bottom half for IRQ handler
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*
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* Read irq status and process accordingly
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*/
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void rwnx_task(unsigned long data)
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{
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struct rwnx_hw *rwnx_hw = (struct rwnx_hw *)data;
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REG_SW_SET_PROFILING(rwnx_hw, SW_PROF_RWNX_IPC_IRQ_HDLR);
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#if 0
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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u32 status, statuses = 0;
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/* Ack unconditionnally in case ipc_host_get_status does not see the irq */
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rwnx_plat->ack_irq(rwnx_plat);
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while ((status = ipc_host_get_status(rwnx_hw->ipc_env))) {
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statuses |= status;
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/* All kinds of IRQs will be handled in one shot (RX, MSG, DBG, ...)
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* this will ack IPC irqs not the cfpga irqs */
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ipc_host_irq(rwnx_hw->ipc_env, status);
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rwnx_plat->ack_irq(rwnx_plat);
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}
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#endif
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//if (statuses & IPC_IRQ_E2A_RXDESC)
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// rwnx_hw->stats.last_rx = now;
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//if (statuses & IPC_IRQ_E2A_TXCFM)
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// rwnx_hw->stats.last_tx = now;
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printk("rwnx_task\n");
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spin_lock_bh(&rwnx_hw->tx_lock);
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rwnx_hwq_process_all(rwnx_hw);
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spin_unlock_bh(&rwnx_hw->tx_lock);
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#if 0
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enable_irq(rwnx_platform_get_irq(rwnx_plat));
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#endif
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REG_SW_CLEAR_PROFILING(rwnx_hw, SW_PROF_RWNX_IPC_IRQ_HDLR);
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}
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