8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
302 lines
9.6 KiB
C
302 lines
9.6 KiB
C
/*
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* Low-level API for mac80211 altobeam apollo wifi drivers
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*
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* Copyright (c) 2016, altobeam
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*
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* Based on:
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* Copyright (c) 2010, stericsson
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* Author: Dmitry Tarnyagin <dmitry.tarnyagin@stericsson.com>
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*
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* Based on:
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* ST-Ericsson UMAC CW1200 driver which is
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* Copyright (c) 2010, ST-Ericsson
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* Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ATBM_APOLLO_HWIO_SDIO_H_INCLUDED
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#define ATBM_APOLLO_HWIO_SDIO_H_INCLUDED
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#include "apollo_plat.h"
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/* DPLL initial values */
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#define DPLL_INIT_VAL_9000 (0x00000191)
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#define DPLL_INIT_VAL_CW1200 (0x0EC4F121)
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#define MAX_RETRY 3
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#define SDIO_TX_MAXLEN 4096*8
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#define ALTOBEAM_WIFI_HDR_FLAG (0x34353677)
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#if (PROJ_TYPE>=ARES_A)
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#define DOWNLOAD_ITCM_ADDR (0x00010000)
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#else
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#define DOWNLOAD_ITCM_ADDR (0x00000000)
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#endif
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#define DOWNLOAD_ITCM_SIZE (160*1024)
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#define DOWNLOAD_DTCM_ADDR (0x00800000)
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#define DOWNLOAD_DTCM_SIZE (48*1024)
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#define DOWNLOAD_BLOCK_SIZE (128)
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#define SYS_BASE_ADDR_SILICON (0)
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#define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
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#define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
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#define CW12000_APB(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
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/* ***************************************************************
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*Device register definitions
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*************************************************************** */
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/* WBF - SPI Register Addresses */
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#define ATBM_HIFREG_ADDR_ID_BASE (0x0000)
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/* 16/32 bits */
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#define ATBM_HIFREG_CONFIG_REG_ID (0x0000)
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/* 16/32 bits */
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#define ATBM_HIFREG_CONTROL_REG_ID (0x0001)
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/* 16 bits, Q mode W/R */
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#define ATBM_HIFREG_IN_OUT_QUEUE_REG_ID (0x0002)
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/* 32 bits, AHB bus R/W */
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#define ATBM_HIFREG_AHB_DPORT_REG_ID (0x0003)
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/* 16/32 bits */
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#define ATBM_HIFREG_SRAM_BASE_ADDR_REG_ID (0x0004)
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/* 32 bits, APB bus R/W */
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#define ATBM_HIFREG_SRAM_DPORT_REG_ID (0x0005)
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/* 32 bits, t_settle/general */
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#define ATBM_HIFREG_TSET_GEN_R_W_REG_ID (0x0006)
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/* 16 bits, Q mode read, no length */
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#define ATBM_HIFREG_FRAME_OUT_REG_ID (0x0007)
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#define ATBM_HIFREG_ADDR_ID_MAX (ATBM_HIFREG_FRAME_OUT_REG_ID)
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/* WBF - Control register bit set */
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/* next o/p length, bit 11 to 0 */
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#define ATBM_HIFREG_CONT_NEXT_LEN_MASK (0xCFFF)
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#define ATBM_HIFREG_CONT_NEXT_LEN_LSB_MASK (0x0FFF)
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#define ATBM_HIFREG_CONT_NEXT_LEN_MSB_MASK (0xC000)
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#define ATBM_HIFREG_CONT_WUP_BIT (BIT(12))
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#define ATBM_HIFREG_CONT_RDY_BIT (BIT(13))
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#define ATBM_HIFREG_CONT_IRQ_ENABLE (BIT(14))
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#define ATBM_HIFREG_CONT_RDY_ENABLE (BIT(15))
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#define ATBM_HIFREG_CONT_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
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#define ATBM_HIFREG_PS_SYNC_SDIO_FLAG (BIT(23))
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#define ATBM_HIFREG_PS_SYNC_SDIO_CLEAN (BIT(24))
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/* SPI Config register bit set */
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#define ATBM_HIFREG_CONFIG_FRAME_BIT (BIT(2))
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#define ATBM_HIFREG_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4))
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#define ATBM_HIFREG_CONFIG_WORD_MODE_1 (BIT(3))
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#define ATBM_HIFREG_CONFIG_WORD_MODE_2 (BIT(4))
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#define ATBM_HIFREG_CONFIG_ERROR_0_BIT (BIT(5))
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#define ATBM_HIFREG_CONFIG_ERROR_1_BIT (BIT(6))
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#define ATBM_HIFREG_CONFIG_ERROR_2_BIT (BIT(7))
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/* TBD: Sure??? */
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#define ATBM_HIFREG_CONFIG_CSN_FRAME_BIT (BIT(7))
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#define ATBM_HIFREG_CONFIG_ERROR_3_BIT (BIT(8))
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#define ATBM_HIFREG_CONFIG_ERROR_4_BIT (BIT(9))
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/* QueueM */
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#define ATBM_HIFREG_CONFIG_ACCESS_MODE_BIT (BIT(10))
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/* AHB bus */
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#define ATBM_HIFREG_CONFIG_AHB_PFETCH_BIT (BIT(11))
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#define ATBM_HIFREG_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
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/* APB bus */
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#define ATBM_HIFREG_CONFIG_PFETCH_BIT (BIT(13))
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/* cpu reset */
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#define ATBM_HIFREG_CONFIG_CPU_RESET_BIT (BIT(14))
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#define ATBM_HIFREG_CONFIG_CLEAR_INT_BIT (BIT(15))
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/* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */
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#define ATBM_HIFREG_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17))
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#define ATBM_HIFREG_CONF_RDY_IRQ_ENABLE (BIT(17))
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#define ATBM_HIFREG_CONF_DATA_IRQ_ENABLE (BIT(16))
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#define ATBM_HIFREG_CONFIG_CPU_RESET_BIT_2 (BIT(22))
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int atbm_data_read_unlock(struct atbm_common *hw_priv, void *buf, u32 buf_len);
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int atbm_data_write_unlock(struct atbm_common *hw_priv, const void *buf,
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size_t buf_len);
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int atbm_data_read(struct atbm_common *hw_priv,
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void *buf, u32 buf_len);
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int atbm_data_write(struct atbm_common *hw_priv, const void *buf,
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size_t buf_len);
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int atbm_reg_read_dpll(struct atbm_common *hw_priv, u16 addr,
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void *buf, u32 buf_len);
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int atbm_reg_write_dpll(struct atbm_common *hw_priv, u16 addr,
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const void *buf, u32 buf_len);
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int atbm_reg_read(struct atbm_common *hw_priv, u16 addr,
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void *buf, u32 buf_len);
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int atbm_reg_write(struct atbm_common *hw_priv, u16 addr,
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const void *buf, u32 buf_len);
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int atbm_reg_read_unlock(struct atbm_common *hw_priv, u16 addr,
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void *buf, u32 buf_len);
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int atbm_reg_write_unlock(struct atbm_common *hw_priv, u16 addr,
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const void *buf, u32 buf_len);
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static inline int atbm_reg_read_8(struct atbm_common *hw_priv,
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u16 addr, u8 *val)
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{
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u32 bigVal;
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int ret;
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ret = atbm_reg_read_dpll(hw_priv, addr, &bigVal, sizeof(bigVal));
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// atbm_dbg(ATBM_APOLLO_DBG_MSG, "%x,bigVal,func=%s\n",bigVal,__func__);
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*val = (u8)bigVal;
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return ret;
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}
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static inline int atbm_reg_write_8(struct atbm_common *hw_priv,
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u16 addr, u8 val)
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{
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u32 bigVal = (u32)val;
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// atbm_dbg(ATBM_APOLLO_DBG_MSG, "%x,val,func=%s\n",val,__func__);
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return atbm_reg_write_dpll(hw_priv, addr, &bigVal, sizeof(bigVal));
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}
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static inline int atbm_reg_read_16(struct atbm_common *hw_priv,
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u16 addr, u16 *val)
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{
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u32 bigVal;
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int ret;
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ret = atbm_reg_read(hw_priv, addr, &bigVal, sizeof(bigVal));
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*val = (u16)bigVal;
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return ret;
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}
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static inline int atbm_reg_read_16_unlock(struct atbm_common *hw_priv,
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u16 addr, u16 *val)
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{
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u32 bigVal;
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int ret;
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ret = atbm_reg_read_unlock(hw_priv, addr, &bigVal, sizeof(bigVal));
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*val = (u16)bigVal;
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return ret;
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}
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static inline int atbm_reg_write_16(struct atbm_common *hw_priv,
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u16 addr, u16 val)
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{
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u32 bigVal = (u32)val;
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return atbm_reg_write(hw_priv, addr, &bigVal, sizeof(bigVal));
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}
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static inline int atbm_reg_read_32(struct atbm_common *hw_priv,
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u16 addr, u32 *val)
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{
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return atbm_reg_read(hw_priv, addr, val, sizeof(int));
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}
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static inline int atbm_reg_write_32(struct atbm_common *hw_priv,
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u16 addr, u32 val)
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{
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return atbm_reg_write(hw_priv, addr, &val, sizeof(int));
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}
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static inline int atbm_reg_read_unlock_32(struct atbm_common *hw_priv,
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u16 addr, u32 *val)
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{
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return atbm_reg_read_unlock(hw_priv, addr, val, sizeof(int));
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}
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static inline int atbm_reg_write_unlock_32(struct atbm_common *hw_priv,
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u16 addr, u32 val)
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{
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return atbm_reg_write_unlock(hw_priv, addr, &val, sizeof(int));
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}
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int atbm_indirect_read_unlock(struct atbm_common *hw_priv, u32 addr, void *buf,
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u32 buf_len, u32 prefetch, u16 port_addr);
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int atbm_indirect_read(struct atbm_common *hw_priv, u32 addr, void *buf,
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u32 buf_len, u32 prefetch, u16 port_addr);
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int atbm_apb_write(struct atbm_common *hw_priv, u32 addr, const void *buf,
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u32 buf_len);
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int atbm_ahb_write(struct atbm_common *priv, u32 addr, const void *buf,
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u32 buf_len);
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int atbm_ahb_write_unlock(struct atbm_common *priv, u32 addr, const void *buf,
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u32 buf_len);
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int atbm_direct_read_reg_32(struct atbm_common *hw_priv, u32 addr, u32 *val);
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int atbm_direct_write_reg_32(struct atbm_common *hw_priv, u32 addr, u32 val);
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int __atbm_irq_enable(struct atbm_common *priv, int enable);
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void __atbm_irq_dbgPrint(struct atbm_common *priv);
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int atbm_direct_read_unlock(struct atbm_common *hw_priv, u32 addr, u32 *val);
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int atbm_direct_write_unlock(struct atbm_common *hw_priv, u32 addr, u32 val);
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static inline int atbm_apb_read(struct atbm_common *hw_priv, u32 addr,
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void *buf, u32 buf_len)
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{
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return atbm_indirect_read(hw_priv, addr, buf, buf_len,
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ATBM_HIFREG_CONFIG_PFETCH_BIT, ATBM_HIFREG_SRAM_DPORT_REG_ID);
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}
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static inline int atbm_ahb_read(struct atbm_common *hw_priv, u32 addr,
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void *buf, size_t buf_len)
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{
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return atbm_indirect_read(hw_priv, addr, buf, buf_len,
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ATBM_HIFREG_CONFIG_AHB_PFETCH_BIT, ATBM_HIFREG_AHB_DPORT_REG_ID);
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}
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static inline int atbm_ahb_read_unlock(struct atbm_common *hw_priv, u32 addr,
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void *buf, size_t buf_len)
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{
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return atbm_indirect_read_unlock(hw_priv, addr, buf, buf_len,
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ATBM_HIFREG_CONFIG_AHB_PFETCH_BIT, ATBM_HIFREG_AHB_DPORT_REG_ID);
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}
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static inline int atbm_apb_read_32(struct atbm_common *hw_priv,
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u32 addr, u32 *val)
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{
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return atbm_apb_read(hw_priv, addr, val, sizeof(int));
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}
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static inline int atbm_apb_write_32(struct atbm_common *hw_priv,
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u32 addr, u32 val)
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{
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return atbm_apb_write(hw_priv, addr, &val, sizeof(val));
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}
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static inline int atbm_ahb_read_32(struct atbm_common *hw_priv,
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u32 addr, u32 *val)
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{
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return atbm_ahb_read(hw_priv, addr, val, sizeof(int));
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}
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#define WRITE_32K_ADDR_MSK (0xfffff000)
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#define WRITE_32K_ADDR (0x16101000)
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static inline int atbm_ahb_write_32(struct atbm_common *hw_priv,
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u32 addr, u32 val)
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{
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int ret = atbm_ahb_write(hw_priv, addr, &val, sizeof(val));
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if((addr&WRITE_32K_ADDR_MSK)==WRITE_32K_ADDR)
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{
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mdelay(10);
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}
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return ret;
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}
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static inline int atbm_ahb_read_unlock_32(struct atbm_common *hw_priv,
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u32 addr, u32 *val)
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{
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return atbm_ahb_read_unlock(hw_priv, addr, val, sizeof(int));
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}
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static inline int atbm_ahb_write_unlock_32(struct atbm_common *hw_priv,
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u32 addr, u32 val)
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{
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int ret;
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int retry = 0;
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while(retry<=3){
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ret = atbm_ahb_write_unlock(hw_priv, addr, &val, sizeof(val));
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if(ret){
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atbm_printk_err("%s\n",__func__);
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}else{
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break;
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}
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}
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if((addr&WRITE_32K_ADDR_MSK)==WRITE_32K_ADDR)
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{
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mdelay(10);
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}
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return ret;
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}
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#endif /* ATBM_APOLLO_HWIO_SDIO_H_INCLUDED */
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