8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
126 lines
2.8 KiB
ArmAsm
126 lines
2.8 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-05 Bernard the first version
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*/
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.globl rt_cpu_get_smp_id
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rt_cpu_get_smp_id:
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mrc p15, #0, r0, c0, c0, #5
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bx lr
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.globl rt_cpu_vector_set_base
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rt_cpu_vector_set_base:
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mcr p15, #0, r0, c12, c0, #0
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dsb
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bx lr
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.globl rt_hw_cpu_dcache_enable
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rt_hw_cpu_dcache_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x00000004
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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.globl rt_hw_cpu_icache_enable
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rt_hw_cpu_icache_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x00001000
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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_FLD_MAX_WAY:
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.word 0x3ff
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_FLD_MAX_IDX:
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.word 0x7ff
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.globl rt_cpu_dcache_clean_flush
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rt_cpu_dcache_clean_flush:
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push {r4-r11}
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dmb
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mrc p15, #1, r0, c0, c0, #1 @ read clid register
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ands r3, r0, #0x7000000 @ get level of coherency
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mov r3, r3, lsr #23
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beq finished
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mov r10, #0
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loop1:
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add r2, r10, r10, lsr #1
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mov r1, r0, lsr r2
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and r1, r1, #7
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cmp r1, #2
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blt skip
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mcr p15, #2, r10, c0, c0, #0
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isb
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mrc p15, #1, r1, c0, c0, #0
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and r2, r1, #7
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add r2, r2, #4
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ldr r4, _FLD_MAX_WAY
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ands r4, r4, r1, lsr #3
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clz r5, r4
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ldr r7, _FLD_MAX_IDX
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ands r7, r7, r1, lsr #13
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loop2:
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mov r9, r4
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loop3:
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orr r11, r10, r9, lsl r5
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orr r11, r11, r7, lsl r2
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mcr p15, #0, r11, c7, c14, #2
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subs r9, r9, #1
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bge loop3
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subs r7, r7, #1
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bge loop2
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skip:
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add r10, r10, #2
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cmp r3, r10
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bgt loop1
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finished:
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dsb
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isb
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pop {r4-r11}
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bx lr
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.globl rt_hw_cpu_dcache_disable
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rt_hw_cpu_dcache_disable:
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push {r4-r11, lr}
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bl rt_cpu_dcache_clean_flush
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x00000004
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mcr p15, #0, r0, c1, c0, #0
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pop {r4-r11, lr}
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bx lr
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.globl rt_hw_cpu_icache_disable
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rt_hw_cpu_icache_disable:
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x00001000
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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.globl rt_cpu_mmu_disable
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rt_cpu_mmu_disable:
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mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #1
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mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
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dsb
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bx lr
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.globl rt_cpu_mmu_enable
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rt_cpu_mmu_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x001
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mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
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dsb
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bx lr
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.globl rt_cpu_tlb_set
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rt_cpu_tlb_set:
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mcr p15, #0, r0, c2, c0, #0
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dmb
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bx lr
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