luckfox-pico-sdk/sysdrv/source/mcu/rt-thread/libcpu/mips/xburst/cache_gcc.S
luckfox-eng29 8f34c2760d project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between
the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door
for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more
usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp:
Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for
compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem.
sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device
tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately.
sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick
boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades.
sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for
fastboot.

Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
2024-10-14 09:47:04 +08:00

43 lines
1007 B
ArmAsm

/*
* File : cache_init.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include "../common/mips.inc"
#include "../common/mipsregs.h"
#include "../common/stackframe.h"
.text
.set noreorder
.globl cache_init
.ent cache_init
cache_init:
.set noreorder
mtc0 zero, CP0_TAGLO
move t0, a0 // cache total size
move t1, a1 // cache line size
li t2, 0x80000000
addu t3, t0, t2
_cache_init_loop:
cache 8, 0(t2) // icache_index_store_tag
cache 9, 0(t2) // dcache_index_store_tag
addu t2, t1
bne t2, t3, _cache_init_loop
nop
mfc0 t0, CP0_CONFIG
li t1, 0x7
not t1
and t0, t0, t1
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
mtc0 t0, CP0_CONFIG
jr ra
nop
.set reorder
.end cache_init