8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Renesas RPC-IF core driver
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*
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* Copyright (C) 2018~2019 Renesas Solutions Corp.
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* Copyright (C) 2019 Macronix International Co., Ltd.
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* Copyright (C) 2019-2020 Cogent Embedded, Inc.
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*/
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#ifndef __RENESAS_RPC_IF_H
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#define __RENESAS_RPC_IF_H
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#include <linux/types.h>
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enum rpcif_data_dir {
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RPCIF_NO_DATA,
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RPCIF_DATA_IN,
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RPCIF_DATA_OUT,
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};
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struct rpcif_op {
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struct {
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u8 buswidth;
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u8 opcode;
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bool ddr;
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} cmd, ocmd;
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struct {
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u8 nbytes;
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u8 buswidth;
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bool ddr;
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u64 val;
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} addr;
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struct {
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u8 ncycles;
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u8 buswidth;
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} dummy;
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struct {
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u8 nbytes;
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u8 buswidth;
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bool ddr;
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u32 val;
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} option;
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struct {
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u8 buswidth;
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unsigned int nbytes;
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enum rpcif_data_dir dir;
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bool ddr;
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union {
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void *in;
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const void *out;
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} buf;
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} data;
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};
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struct rpcif {
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struct device *dev;
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void __iomem *base;
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void __iomem *dirmap;
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struct regmap *regmap;
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struct reset_control *rstc;
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size_t size;
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enum rpcif_data_dir dir;
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u8 bus_size;
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u8 xfer_size;
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void *buffer;
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u32 xferlen;
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u32 smcr;
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u32 smadr;
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u32 command; /* DRCMR or SMCMR */
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u32 option; /* DROPR or SMOPR */
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u32 enable; /* DRENR or SMENR */
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u32 dummy; /* DRDMCR or SMDMCR */
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u32 ddr; /* DRDRENR or SMDRENR */
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};
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int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
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void rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
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void rpcif_enable_rpm(struct rpcif *rpc);
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void rpcif_disable_rpm(struct rpcif *rpc);
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void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
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size_t *len);
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int rpcif_manual_xfer(struct rpcif *rpc);
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ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf);
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#endif // __RENESAS_RPC_IF_H
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