8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <asm/arch/param.h>
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#include <asm/arch/rk_atags.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void fpga_init_atags(void)
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{
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#ifdef CONFIG_FPGA_RAM
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struct tag_ram_partition t_ram_part;
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#endif
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struct tag_bootdev t_bootdev;
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struct tag_ddr_mem t_ddrmem;
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struct tag_serial t_serial;
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struct tag_tos_mem t_tos;
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#if defined(CONFIG_ARM64) || defined(CONFIG_ARM64_BOOT_AARCH32)
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struct tag_atf_mem t_atf;
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#endif
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/* destroy ! */
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atags_destroy();
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/* serial */
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memset(&t_serial, 0, sizeof(t_serial));
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t_serial.version = 0;
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t_serial.enable = 1;
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t_serial.addr = CONFIG_DEBUG_UART_BASE;
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t_serial.baudrate = CONFIG_BAUDRATE;
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t_serial.m_mode = 0;
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t_serial.id = 2;
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atags_set_tag(ATAG_SERIAL, &t_serial);
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/* ddr memory */
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memset(&t_ddrmem, 0, sizeof(t_ddrmem));
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t_ddrmem.version = 0;
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t_ddrmem.count = 1;
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t_ddrmem.bank[0] = CONFIG_SYS_SDRAM_BASE;
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t_ddrmem.bank[1] = SZ_512M;
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atags_set_tag(ATAG_DDR_MEM, &t_ddrmem);
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/* bootdev */
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memset(&t_bootdev, 0, sizeof(t_bootdev));
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t_bootdev.version = 0;
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#ifdef CONFIG_FPGA_RAM
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t_bootdev.devtype = BOOT_TYPE_RAM;
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#else
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t_bootdev.devtype = BOOT_TYPE_EMMC;
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#endif
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t_bootdev.devnum = 0;
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t_bootdev.sdupdate = 0;
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atags_set_tag(ATAG_BOOTDEV, &t_bootdev);
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/* atf */
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#if defined(CONFIG_ARM64) || defined(CONFIG_ARM64_BOOT_AARCH32)
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memset(&t_atf, 0, sizeof(t_atf));
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t_atf.version = 0;
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t_atf.phy_addr = CONFIG_SYS_SDRAM_BASE;
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t_atf.size = SZ_1M;
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t_atf.flags = 0;
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atags_set_tag(ATAG_ATF_MEM, &t_atf);
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#endif
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/* op-tee */
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memset(&t_tos, 0, sizeof(t_tos));
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t_tos.version = 0;
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strcpy(t_tos.tee_mem.name, "op-tee");
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#ifdef CONFIG_ARM64
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t_tos.tee_mem.phy_addr = 0x8400000; /* 132M offset */
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t_tos.tee_mem.size = 0x1e00000; /* 30M size */
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#endif
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t_tos.tee_mem.flags = 1;
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atags_set_tag(ATAG_TOS_MEM, &t_tos);
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#ifdef CONFIG_FPGA_RAM
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/* ram part */
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memset(&t_ram_part, 0, sizeof(t_ram_part));
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t_ram_part.version = 0;
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t_ram_part.count = 1;
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strcpy(t_ram_part.part[0].name, "boot");
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t_ram_part.part[0].start = 0x4000000; /* 64M offset */
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t_ram_part.part[0].size = 0x2000000; /* 32M size */
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atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
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#endif
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}
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int arch_fpga_init(void)
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{
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fpga_init_atags();
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return 0;
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}
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