191 lines
6.1 KiB
C
191 lines
6.1 KiB
C
/*
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* Copyright (c) 2015 iComm-semi Ltd.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _SDIO_DEF_H_
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#define _SDIO_DEF_H_
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#include <linux/scatterlist.h>
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/* -------------- h/w register ------------------- */
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#define BASE_SDIO 0 /* for CMD52 */
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#define SD_REG_BASE 0xc0000800 /* for CMD53 */
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/* Note :
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For now, the reg of SDIO Host & Card Controller are the same.
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If it changes in the future, you should define again.
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*/
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#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00) // 0
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#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01) // 0
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#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02) // 0
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#define REG_INT_MASK (BASE_SDIO + 0x04) // 0
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#define REG_INT_STATUS (BASE_SDIO + 0x08) // 0
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#define REG_INT_TRIGGER (BASE_SDIO + 0x09) // 0
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#define REG_Fn1_STATUS (BASE_SDIO + 0x0c) // 0
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#define REG_SD_READY_FLAG (BASE_SDIO + 0x0f) // 0
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#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10) // 0
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#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11) // 0
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#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12) // 0
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#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13) // 0
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#define REG_CARD_RCA_0 (BASE_SDIO + 0x20) // 0
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#define REG_CARD_RCA_1 (BASE_SDIO + 0x21) // 0
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#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24) // 80
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#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25) // 0
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#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55) // 0
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#define MCU_NOTIFY_HOST_CFG (BASE_SDIO + 0x56)
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#define REG_SDIO_DAT3_DELAY (BASE_SDIO + 0x59) // 44
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#define REG_SDIO_DAT2_DELAY (BASE_SDIO + 0x5a) // 44
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#define REG_SDIO_DAT1_DELAY (BASE_SDIO + 0x5b) // 44
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#define REG_SDIO_DAT0_DELAY (BASE_SDIO + 0x5c) // 44
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//#define REG_PMU_WAKEUP (BASE_SDIO + 0x64) // 0 FPGA
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#define REG_PMU_WAKEUP (BASE_SDIO + 0x67) // 0
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#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70) // 0
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#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71) // 0
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#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72) // 0
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//SDIO TX ALLOCATE FUNCTION
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#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98) // 0
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#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99) // 0
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#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a) // 0
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#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c) // 0
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#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d) // 0
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#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e) // 0
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#if 0
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#define SDIO_TX_ALLOC_SUCCESS 0x01
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#define SDIO_TX_NO_ALLOC 0x02
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#define SDIO_TX_DULPICATE_ALLOC 0x04
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#define SDIO_TX_TX_DONE 0x08
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#define SDIO_TX_AHB_HANG 0x10
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#define SDIO_TX_MB_FULL 0x80
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#define SDIO_HCI_IN_QUEUE_EMPTY 0x04
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#define SDIO_EDCA0_SHIFT 4
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#define SDIO_TX_ALLOC_SIZE_SHIFT 0x07
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#define SDIO_TX_ALLOC_ENABLE 0x10
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#endif
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/* -------------- default ------------------- */
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#define SDIO_DEF_BLOCK_SIZE 0x80 // 128,should be the multiple of 8 bytes
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#if (SDIO_DEF_BLOCK_SIZE % 8)
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#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
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#endif
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//output timing
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// 0: cmd [0]:positive [1]:negative
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// 1: data [0]:positive [1]:negative
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#define SDIO_DEF_OUTPUT_TIMING 0
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// block mode threshold
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#define SDIO_DEF_BLOCK_MODE_THRD 128
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#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
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#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
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#endif
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// 0: false, 1: true
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#define SDIO_DEF_FORCE_BLOCK_MODE 0
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/* Scatter/Gather related */
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#define MAX_SCATTER_ENTRIES_PER_REQ 8
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struct sdio_scatter_item {
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u8 *buf;
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int len;
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};
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struct sdio_scatter_req {
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/* request flags */
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u32 req;
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/* total length of entire transfer */
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u32 len;
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int scat_entries;
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/* bounce buffer for upper layers to copy to/from */
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struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
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struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
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};
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//-------------------------------------------------------------
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/* request flags of sdio_scatter_req*/
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/* direction of transfer (read/write) */
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#define SDIO_READ 0x00000001
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#define SDIO_WRITE 0x00000002
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//cmd 53 r/w flags
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#define CMD53_ARG_READ 0
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#define CMD53_ARG_WRITE 1
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//cmd53 block basis
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#define CMD53_ARG_BLOCK_BASIS 1
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//cmd 53 opcode
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#define CMD53_ARG_FIXED_ADDRESS 0
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#define CMD53_ARG_INCR_ADDRESS 1
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#ifdef CONFIG_FW_ALIGNMENT_CHECK
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#define SDIO_DMA_BUFFER_LEN 2048
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#endif
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#ifdef CONFIG_PM
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#define SDIO_COMMAND_BUFFER_LEN 256
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#endif
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#define IO_REG_BURST_RD_PORT_REG 0x10080
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#define IO_REG_BURST_WR_PORT_REG 0x10040
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#define MAX_BURST_READ_REG_AMOUNT 2
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#define MAX_BURST_WRITE_REG_AMOUNT 2
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//-------------------------------------------------------------
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/* SDIO Delay chain */
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#define SDIO_INPUT_DELAY_MSK 0x04
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#define SDIO_INPUT_DELAY_SFT 2
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#define SDIO_INPUT_DELAY_LEVEL_MSK 0x03
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#define SDIO_INPUT_DELAY_LEVEL_SFT 0
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#define SDIO_OUTPUT_DELAY_MSK 0x40
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#define SDIO_OUTPUT_DELAY_SFT 6
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#define SDIO_OUTPUT_DELAY_LEVEL_MSK 0x30
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#define SDIO_OUTPUT_DELAY_LEVEL_SFT 4
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#define SDIO_DELAY_LEVEL_OFF 0
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#define SDIO_DELAY_LEVEL_0 1
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#define SDIO_DELAY_LEVEL_1 2
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#define SDIO_DELAY_LEVEL_2 3
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#define SDIO_DELAY_LEVEL_3 4
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//-------------------------------------------------------------
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/* SDIO ready flag related */
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#define SDIO_READY_FLAG_BUSY 0x0
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#define SDIO_READY_FLAG_IDLE 0x2
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#define SDIO_READY_FLAG_BUSY_THRESHOLD 10000
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#define SDIO_READY_FLAG_BUSY_DELAY 5
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#define PLATFORM_DEF_DMA_ALIGN_SIZE 32
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#define PLATFORM_DMA_ALIGNED __attribute__ ((aligned(PLATFORM_DEF_DMA_ALIGN_SIZE)))
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#endif /* _SDIO_DEF_H_ */
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