8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
143 lines
4.5 KiB
C
143 lines
4.5 KiB
C
/**
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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******************************************************************************
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* @file dma.h
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* @author Sugar Zhang
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* @version V0.1
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* @date 8-Feb-2019
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* @brief general dma framework driver for pisces
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*
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******************************************************************************
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*/
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#ifndef __DMA_H__
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#define __DMA_H__
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/* Includes ------------------------------------------------------------------*/
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#include <rtthread.h>
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#include <hal_base.h>
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/* Exported macro ------------------------------------------------------------*/
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#define RT_DEVICE_CTRL_DMA_OPEN (1)
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#define RT_DEVICE_CTRL_DMA_CLOSE (2)
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#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL (3)
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#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL (4)
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#define RT_DEVICE_CTRL_DMA_SINGLE_PREPARE (5)
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#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE (6)
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#define RT_DEVICE_CTRL_DMA_START (7)
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#define RT_DEVICE_CTRL_DMA_STOP (8)
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#define RT_DEVICE_CTRL_DMA_GET_POSITION (9)
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/* Exported types ------------------------------------------------------------*/
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typedef enum
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{
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RT_DMA_MEM_TO_MEM = 0,
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RT_DMA_MEM_TO_DEV = 1,
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RT_DMA_DEV_TO_MEM = 2,
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RT_DMA_DEV_TO_DEV = 3,
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RT_DMA_TRANS_NONE = 4,
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} dma_direction_t;
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typedef enum
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{
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RT_DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
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RT_DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
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RT_DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
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RT_DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
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RT_DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
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RT_DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
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RT_DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
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RT_DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
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RT_DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
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} dma_slave_buswidth_t;
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struct dma_slave_config
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{
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dma_direction_t direction;
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dma_slave_buswidth_t src_addr_width;
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dma_slave_buswidth_t dst_addr_width;
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uint32_t src_addr;
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uint32_t dst_addr;
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uint16_t src_maxburst;
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uint16_t dst_maxburst;
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uint16_t src_interlace_size;
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uint16_t dst_interlace_size;
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};
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typedef void (*dma_callback)(void *cparam);
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struct rt_dma_chan;
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struct rt_dma_device
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{
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struct rt_device dev;
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uint32_t base;
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int (*start)(struct rt_dma_chan *chan);
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int (*stop)(struct rt_dma_chan *chan);
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/* id: DMA_REQ_Type */
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struct rt_dma_chan *(*request_channel)(struct rt_dma_device *dma, uint16_t id);
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int (*release_channel)(struct rt_dma_chan *chan);
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int (*config)(struct rt_dma_chan *chan, struct dma_slave_config *config);
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int (*prep_dma_memcpy)(struct rt_dma_chan *chan, uint32_t dst,
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uint32_t src, uint32_t len,
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dma_callback callback, void *cparam);
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int (*prep_dma_cyclic)(struct rt_dma_chan *chan, uint32_t dmaAddr,
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uint32_t len, uint32_t periodLen,
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dma_direction_t direction,
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dma_callback callback, void *cparam);
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int (*prep_dma_single)(struct rt_dma_chan *chan, uint32_t dmaAddr,
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uint32_t len,
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dma_direction_t direction,
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dma_callback callback, void *cparam);
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int (*get_position)(struct rt_dma_chan *chan);
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};
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struct rt_dma_chan
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{
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struct rt_dma_device *device;
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int chanId;
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};
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struct rt_dma_transfer
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{
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rt_uint32_t position;
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/* user's params */
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rt_uint32_t dma_req_num; /* peri dma request num */
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rt_uint32_t direction; /* direction */
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rt_uint32_t src_addr; /* src addr */
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rt_uint32_t dst_addr; /* dst addr */
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rt_uint32_t src_addr_width; /* addr bus width */
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rt_uint32_t dst_addr_width; /* addr bus width */
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rt_uint32_t src_maxburst; /* burst len */
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rt_uint32_t dst_maxburst; /* burst len */
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rt_uint32_t src_interlace_size; /* interlace size */
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rt_uint32_t dst_interlace_size; /* interlace size */
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rt_uint32_t len; /* in bytes */
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rt_uint32_t period_len; /* in bytes */
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rt_bool_t cyclic; /* indicate whether the xfer is cyclic or single */
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dma_callback callback; /* dma xfer complete callback func */
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void *cparam; /* callback param */
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struct rt_dma_chan *chan; /* don't touch this. */
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};
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/* Exported constants --------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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rt_device_t rt_dma_get(uint32_t base);
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rt_err_t rt_hw_dma_register(struct rt_dma_device *dma);
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void *rt_dma_malloc(uint32_t size);
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__STATIC_FORCEINLINE void rt_dma_free(void *ptr)
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{
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rt_free_align(ptr);
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}
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#endif
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