8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
47 lines
2.0 KiB
C
47 lines
2.0 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard first version
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*/
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#ifndef __INTERRUPT_H__
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#define __INTERRUPT_H__
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#define INT_IRQ 0x00
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#define INT_FIQ 0x01
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#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0)
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#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10)
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#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14)
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#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40)
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#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44)
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#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48)
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#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c)
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#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50)
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#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60)
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#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64)
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#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68)
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#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c)
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#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04))
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#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20))
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#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20))
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#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20))
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#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20))
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#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20))
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#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20))
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#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20))
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#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20))
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#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04))
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void rt_hw_interrupt_control(int vector, int priority, int route);
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int rt_hw_interrupt_get_active(int fiq_irq);
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void rt_hw_interrupt_ack(int fiq_irq);
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void rt_hw_interrupt_trigger(int vector);
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void rt_hw_interrupt_clear(int vector);
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#endif
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