8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
141 lines
3.6 KiB
C
141 lines
3.6 KiB
C
/*
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* File : ls1b.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-08 lgnq first version
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*/
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#ifndef __LS1B_H__
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#define __LS1B_H__
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#include "../common/mipsregs.h"
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#define LS1B_ACPI_IRQ 0
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#define LS1B_HPET_IRQ 1
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#define LS1B_UART0_IRQ 2
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#define LS1B_UART1_IRQ 3
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#define LS1B_UART2_IRQ 4
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#define LS1B_UART3_IRQ 5
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#define LS1B_CAN0_IRQ 6
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#define LS1B_CAN1_IRQ 7
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#define LS1B_SPI0_IRQ 8
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#define LS1B_SPI1_IRQ 9
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#define LS1B_AC97_IRQ 10
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#define LS1B_MS_IRQ 11
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#define LS1B_KB_IRQ 12
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#define LS1B_DMA0_IRQ 13
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#define LS1B_DMA1_IRQ 14
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#define LS1B_NAND_IRQ 15
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#define LS1B_I2C0_IRQ 16
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#define LS1B_I2C1_IRQ 17
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#define LS1B_PWM0_IRQ 18
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#define LS1B_PWM1_IRQ 19
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#define LS1B_PWM2_IRQ 20
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#define LS1B_PWM3_IRQ 21
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#define LS1B_LPC_IRQ 22
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#define LS1B_EHCI_IRQ 32
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#define LS1B_OHCI_IRQ 33
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#define LS1B_GMAC1_IRQ 34
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#define LS1B_GMAC2_IRQ 35
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#define LS1B_SATA_IRQ 36
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#define LS1B_GPU_IRQ 37
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#define LS1B_PCI_INTA_IRQ 38
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#define LS1B_PCI_INTB_IRQ 39
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#define LS1B_PCI_INTC_IRQ 40
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#define LS1B_PCI_INTD_IRQ 41
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#define LS1B_GPIO_IRQ 64
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#define LS1B_GPIO_FIRST_IRQ 64
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#define LS1B_GPIO_IRQ_COUNT 96
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#define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
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#define INT_PCI_INTA (1<<6)
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#define INT_PCI_INTB (1<<7)
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#define INT_PCI_INTC (1<<8)
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#define INT_PCI_INTD (1<<9)
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#define LS1B_LAST_IRQ 159
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#define MIPS_CPU_TIMER_IRQ 167
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#define LS1B_INTREG_BASE 0xbfd01040
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#define LS1B_DMA_IRQ_BASE 168
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#define LS1B_DMA_IRQ_COUNT 16
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struct ls1b_intc_regs
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{
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volatile unsigned int int_isr;
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volatile unsigned int int_en;
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volatile unsigned int int_set;
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volatile unsigned int int_clr; /* offset 0x10*/
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volatile unsigned int int_pol;
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volatile unsigned int int_edge; /* offset 0 */
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};
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struct ls1b_cop_global_regs
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{
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volatile unsigned int control;
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volatile unsigned int rd_inten;
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volatile unsigned int wr_inten;
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volatile unsigned int rd_intisr; /* offset 0x10*/
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volatile unsigned int wr_intisr;
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unsigned int unused[11];
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} ;
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struct ls1b_cop_channel_regs
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{
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volatile unsigned int rd_control;
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volatile unsigned int rd_src;
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volatile unsigned int rd_cnt;
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volatile unsigned int rd_status; /* offset 0x10*/
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volatile unsigned int wr_control;
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volatile unsigned int wr_src;
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volatile unsigned int wr_cnt;
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volatile unsigned int wr_status; /* offset 0x10*/
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} ;
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struct ls1b_cop_regs
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{
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struct ls1b_cop_global_regs global;
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struct ls1b_cop_channel_regs chan[8][2];
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} ;
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#define __REG8(addr) *((volatile unsigned char *)(addr))
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#define __REG16(addr) *((volatile unsigned short *)(addr))
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#define __REG32(addr) *((volatile unsigned int *)(addr))
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#define GMAC0_BASE 0xBFE10000
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#define GMAC0_DMA_BASE 0xBFE11000
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#define GMAC1_BASE 0xBFE20000
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#define GMAC1_DMA_BASE 0xBFE21000
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#define I2C0_BASE 0xBFE58000
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#define PWM0_BASE 0xBFE5C000
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#define PWM1_BASE 0xBFE5C010
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#define PWM2_BASE 0xBFE5C020
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#define PWM3_BASE 0xBFE5C030
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#define WDT_BASE 0xBFE5C060
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#define RTC_BASE 0xBFE64000
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#define I2C1_BASE 0xBFE68000
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#define I2C2_BASE 0xBFE70000
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#define AC97_BASE 0xBFE74000
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#define NAND_BASE 0xBFE78000
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#define SPI_BASE 0xBFE80000
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#define CAN1_BASE 0xBF004300
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#define CAN0_BASE 0xBF004400
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/* Watch Dog registers */
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#define WDT_EN __REG32(WDT_BASE + 0x00)
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#define WDT_SET __REG32(WDT_BASE + 0x04)
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#define WDT_TIMER __REG32(WDT_BASE + 0x08)
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#define PLL_FREQ __REG32(0xbfe78030)
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#define PLL_DIV_PARAM __REG32(0xbfe78034)
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#endif
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