8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/*
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* File : mipscfg.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-05-27 swkyer first version
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*/
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#include <rtthread.h>
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#include "../common/mipsregs.h"
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#include "../common/mipscfg.h"
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mips32_core_cfg_t g_mips_core =
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{
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16, /* icache_line_size */
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256, /* icache_lines_per_way */
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4, /* icache_ways */
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16, /* dcache_line_size */
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256, /* dcache_lines_per_way */
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4, /* dcache_ways */
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16, /* max_tlb_entries */
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};
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static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
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{
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rt_uint16_t rets = 1;
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while (n--)
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rets *= b;
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return rets;
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}
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static rt_uint16_t m_log2(rt_uint16_t b)
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{
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rt_uint16_t rets = 0;
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while (b != 1)
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{
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b /= 2;
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rets++;
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}
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return rets;
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}
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/**
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* read core attribute
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*/
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void mips32_cfg_init(void)
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{
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rt_uint16_t val;
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rt_uint32_t cp0_config1;
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cp0_config1 = read_c0_config();
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if (cp0_config1 & 0x80000000)
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{
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cp0_config1 = read_c0_config1();
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val = (cp0_config1 & (7<<22))>>22;
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g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
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val = (cp0_config1 & (7<<19))>>19;
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g_mips_core.icache_line_size = 2 * m_pow(2, val);
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val = (cp0_config1 & (7<<16))>>16;
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g_mips_core.icache_ways = val + 1;
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val = (cp0_config1 & (7<<13))>>13;
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g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
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val = (cp0_config1 & (7<<10))>>10;
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g_mips_core.dcache_line_size = 2 * m_pow(2, val);
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val = (cp0_config1 & (7<<7))>>7;
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g_mips_core.dcache_ways = val + 1;
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val = (cp0_config1 & (0x3F<<25))>>25;
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g_mips_core.max_tlb_entries = val + 1;
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}
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}
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