8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
122 lines
3.2 KiB
ArmAsm
122 lines
3.2 KiB
ArmAsm
#include <p32xxxx.h>
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#include "../common/mips.inc"
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#include "../common/stackframe.h"
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.section ".text", "ax"
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.set noat
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.set noreorder
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/*
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* rt_base_t rt_hw_interrupt_disable()
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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mfc0 v0, CP0_STATUS /* v0 = status */
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addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
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and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */
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mtc0 v1, CP0_STATUS /* status = v1 */
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jr ra
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nop
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/*
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* void rt_hw_interrupt_enable(rt_base_t level)
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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mtc0 a0, CP0_STATUS
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jr ra
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nop
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/*
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* void rt_hw_context_switch_to(rt_uint32 to)/*
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* a0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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lw sp, 0(a0) /* get new task stack pointer */
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RESTORE_ALL_AND_RET
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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mtc0 ra, CP0_EPC
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SAVE_ALL
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sw sp, 0(a0) /* store sp in preempted tasks TCB */
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lw sp, 0(a1) /* get new task stack pointer */
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RESTORE_ALL_AND_RET
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
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*/
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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la t0, rt_thread_switch_interrupt_flag
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lw t1, 0(t0)
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nop
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bnez t1, _reswitch
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nop
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li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
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sw t1, 0(t0)
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la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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sw a0, 0(t0)
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_reswitch:
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la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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sw a1, 0(t0)
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/* trigger the soft exception (causes context switch) */
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mfc0 t0, CP0_CAUSE /* t0 = Cause */
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ori t0, t0, (1<<8) /* t0 |= (1<<8) */
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mtc0 t0, CP0_CAUSE /* cause = t0 */
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addiu t1, zero, -257 /* t1 = ~(1<<8) */
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and t0, t0, t1 /* t0 &= t1 */
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mtc0 t0, CP0_CAUSE /* cause = t0 */
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jr ra
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nop
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/*
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* void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void)
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*/
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.section ".text", "ax"
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.set noreorder
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.set noat
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.ent CoreSW0Handler
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.globl CoreSW0Handler
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CoreSW0Handler:
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SAVE_ALL
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/* mCS0ClearIntFlag(); */
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la t0, IFS0CLR /* t0 = IFS0CLR */
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addiu t1,zero,0x02 /* t1 = (1<<2) */
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sw t1, 0(t0) /* IFS0CLR = t1 */
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la k0, rt_thread_switch_interrupt_flag
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sw zero, 0(k0) /* clear flag */
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/*
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* switch to the new thread
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*/
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la k0, rt_interrupt_from_thread
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lw k1, 0(k0)
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nop
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sw sp, 0(k1) /* store sp in preempted tasks's TCB */
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la k0, rt_interrupt_to_thread
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lw k1, 0(k0)
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nop
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lw sp, 0(k1) /* get new task's stack pointer */
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RESTORE_ALL_AND_RET
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.end CoreSW0Handler
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