8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
94 lines
1.8 KiB
C
94 lines
1.8 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __ARMV6_H__
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#define __ARMV6_H__
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/*****************************/
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/* CPU Mode */
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/*****************************/
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#define USERMODE 0x10
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#define FIQMODE 0x11
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#define IRQMODE 0x12
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#define SVCMODE 0x13
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#define ABORTMODE 0x17
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#define UNDEFMODE 0x1b
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#define MODEMASK 0x1f
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#define NOINT 0xc0
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#ifndef __ASSEMBLY__
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struct rt_hw_register
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{
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rt_uint32_t cpsr;
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t fp;
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rt_uint32_t ip;
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rt_uint32_t sp;
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rt_uint32_t lr;
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rt_uint32_t pc;
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};
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#if(0)
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struct rt_hw_register{
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t fp;
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rt_uint32_t ip;
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rt_uint32_t sp;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t cpsr;
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rt_uint32_t ORIG_r0;
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};
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#endif
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#endif
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/* rt_hw_register offset */
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#define S_FRAME_SIZE 68
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#define S_PC 64
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#define S_LR 60
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#define S_SP 56
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#define S_IP 52
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#define S_FP 48
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#define S_R10 44
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#define S_R9 40
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#define S_R8 36
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#define S_R7 32
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#define S_R6 28
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#define S_R5 24
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#define S_R4 20
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#define S_R3 16
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#define S_R2 12
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#define S_R1 8
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#define S_R0 4
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#define S_CPSR 0
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#endif
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