8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
105 lines
2.0 KiB
C
105 lines
2.0 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2008-04-25 Yi.qiu first version
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*/
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#include <rtthread.h>
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#include "s3c24x0.h"
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#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
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#if CONFIG_SYS_CLK_FREQ == 12000000
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/* MPLL=2*12*100/6=400MHz */
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#define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
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#define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
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#define MPL_SDIV 0 /* s=MPL_SDIV=0 */
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/* UPLL=12*64/8=96MHz */
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#define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
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#define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
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#define UPL_SDIV 1 /* s=UPL_SDIV=1 */
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/* System clock divider FCLK:HCLK:PCLK=1:4:8 */
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#define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
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#define HDIVN 0x2 /* HCLK = FCLK / 4 */
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#define PDIVN 0x1 /* PCLK = HCLK / 2 */
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#endif
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rt_uint32_t PCLK;
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rt_uint32_t FCLK;
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rt_uint32_t HCLK;
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rt_uint32_t UCLK;
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void rt_hw_get_clock(void)
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{
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rt_uint32_t val;
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rt_uint8_t m, p, s;
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val = MPLLCON;
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m = (val>>12)&0xff;
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p = (val>>4)&0x3f;
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s = val&3;
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FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
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val = CLKDIVN;
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m = (val>>1)&3;
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p = val&1;
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switch (m) {
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case 0:
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HCLK = FCLK;
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break;
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case 1:
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HCLK = FCLK>>1;
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break;
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case 2:
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if(s&2)
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HCLK = FCLK>>3;
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else
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HCLK = FCLK>>2;
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break;
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case 3:
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if(s&1)
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HCLK = FCLK/6;
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else
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HCLK = FCLK/3;
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break;
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}
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if(p)
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PCLK = HCLK>>1;
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else
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PCLK = HCLK;
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}
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void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
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{
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MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
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}
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void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
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{
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UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
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}
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void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
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{
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CLKDIVN = (hdivn<<1) | pdivn;
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}
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/**
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* @brief System Clock Configuration
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*/
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void rt_hw_clock_init(void)
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{
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LOCKTIME = 0xFFFFFFFF;
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rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
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rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
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rt_hw_set_divider(HDIVN, PDIVN);
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}
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