8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
433 lines
11 KiB
C
433 lines
11 KiB
C
/*
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* Copyright (c) 2016 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <pwm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/pwm.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* regs for pwm v4
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*/
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#define HIWORD_UPDATE(v, l, h) (((v) << (l)) | (GENMASK(h, l) << 16))
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/* VERSION_ID */
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#define VERSION_ID 0x0
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#define CHANNEL_NUM_SUPPORT_SHIFT 0
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#define CHANNEL_NUM_SUPPORT_MASK (0xf << CHANNEL_NUM_SUPPORT_SHIFT)
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#define CHANNLE_INDEX_SHIFT 4
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#define CHANNLE_INDEX_MASK (0xf << CHANNLE_INDEX_SHIFT)
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/* ENABLE */
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#define ENABLE 0x4
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#define PWM_ENABLE_V4 (0x3 << 0)
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#define PWM_CLK_EN(v) HIWORD_UPDATE(v, 0, 0)
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#define PWM_EN(v) HIWORD_UPDATE(v, 1, 1)
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#define PWM_CTRL_UPDATE_EN(v) HIWORD_UPDATE(v, 2, 2)
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#define PWM_GLOBAL_JOIN_EN(v) HIWORD_UPDATE(v, 4, 4)
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/* CLK_CTRL */
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#define CLK_CTRL 0x8
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#define CLK_PRESCALE(v) HIWORD_UPDATE(v, 0, 2)
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#define CLK_SCALE(v) HIWORD_UPDATE(v, 4, 12)
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#define CLK_SRC_SEL(v) HIWORD_UPDATE(v, 13, 14)
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#define CLK_GLOBAL_SEL(v) HIWORD_UPDATE(v, 15, 15)
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/* CTRL */
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#define CTRL_V4 0xc
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#define PWM_MODE(v) HIWORD_UPDATE(v, 0, 1)
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#define ONESHOT_MODE 0
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#define CONTINUOUS_MODE 1
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#define CAPTURE_MODE 2
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#define PWM_POLARITY(v) HIWORD_UPDATE(v, 2, 3)
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#define DUTY_NEGATIVE (0 << 0)
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#define DUTY_POSITIVE (1 << 0)
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#define INACTIVE_NEGATIVE (0 << 1)
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#define INACTIVE_POSITIVE (1 << 1)
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#define PWM_ALIGNED_INVALID(v) HIWORD_UPDATE(v, 5, 5)
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#define PWM_IN_SEL(v) HIWORD_UPDATE(v, 6, 8)
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/* PERIOD */
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#define PERIOD 0x10
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/* DUTY */
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#define DUTY 0x14
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struct rk_pwm_priv {
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fdt_addr_t base;
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ulong freq;
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u32 conf_polarity;
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bool vop_pwm_en; /* indicate voppwm mirror register state */
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const struct rockchip_pwm_data *data;
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};
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struct rockchip_pwm_funcs {
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int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
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int (*set_config)(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns);
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int (*set_enable)(struct udevice *dev, uint channel, bool enable);
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};
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struct rockchip_pwm_data {
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struct rockchip_pwm_regs regs;
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struct rockchip_pwm_funcs funcs;
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unsigned int prescaler;
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bool supports_polarity;
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bool supports_lock;
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bool vop_pwm;
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u8 main_version;
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u32 enable_conf;
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u32 enable_conf_mask;
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};
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static int rk_pwm_set_invert_v4(struct udevice *dev, uint channel, bool polarity)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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debug("%s: polarity=%u\n", __func__, polarity);
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if (polarity)
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priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
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else
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priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
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return 0;
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}
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static int rk_pwm_set_invert_v1(struct udevice *dev, uint channel, bool polarity)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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debug("%s: polarity=%u\n", __func__, polarity);
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if (polarity)
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priv->conf_polarity = PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
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else
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priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
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return 0;
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}
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static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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if (!priv->data->supports_polarity) {
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debug("%s: Do not support polarity\n", __func__);
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return 0;
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}
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return priv->data->funcs.set_invert(dev, channel, polarity);
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}
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static int rk_pwm_set_config_v4(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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unsigned long period, duty;
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period = lldiv((uint64_t)(priv->freq / 1000) * period_ns,
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priv->data->prescaler * 1000000);
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duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns,
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priv->data->prescaler * 1000000);
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writel(period, priv->base + PERIOD);
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writel(duty, priv->base + DUTY);
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if (priv->data->supports_polarity)
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writel(PWM_POLARITY(priv->conf_polarity), priv->base + CTRL_V4);
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writel(PWM_MODE(CONTINUOUS_MODE) | PWM_ALIGNED_INVALID(false),
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priv->base + CTRL_V4);
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writel(PWM_CTRL_UPDATE_EN(true), priv->base + ENABLE);
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debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
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return 0;
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}
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static int rk_pwm_set_config_v1(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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const struct rockchip_pwm_regs *regs = &priv->data->regs;
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unsigned long period, duty;
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u32 ctrl;
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debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
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ctrl = readl(priv->base + regs->ctrl);
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if (priv->data->vop_pwm) {
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if (priv->vop_pwm_en)
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ctrl |= RK_PWM_ENABLE;
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else
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ctrl &= ~RK_PWM_ENABLE;
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}
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/*
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* Lock the period and duty of previous configuration, then
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* change the duty and period, that would not be effective.
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*/
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if (priv->data->supports_lock) {
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ctrl |= PWM_LOCK;
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writel(ctrl, priv->base + regs->ctrl);
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}
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period = lldiv((uint64_t)(priv->freq / 1000) * period_ns,
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priv->data->prescaler * 1000000);
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duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns,
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priv->data->prescaler * 1000000);
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writel(period, priv->base + regs->period);
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writel(duty, priv->base + regs->duty);
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if (priv->data->supports_polarity) {
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ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
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ctrl |= priv->conf_polarity;
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}
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/*
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* Unlock and set polarity at the same time,
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* the configuration of duty, period and polarity
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* would be effective together at next period.
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*/
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if (priv->data->supports_lock)
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ctrl &= ~PWM_LOCK;
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writel(ctrl, priv->base + regs->ctrl);
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debug("%s: period=%lu, duty=%lu\n", __func__, period, duty);
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return 0;
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}
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static int rk_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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return priv->data->funcs.set_config(dev, channel, period_ns, duty_ns);
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}
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static int rk_pwm_set_enable_v4(struct udevice *dev, uint channel, bool enable)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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debug("%s: Enable '%s'\n", __func__, dev->name);
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writel(PWM_EN(enable) | PWM_CLK_EN(enable), priv->base + ENABLE);
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if (enable)
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pinctrl_select_state(dev, "active");
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return 0;
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}
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static int rk_pwm_set_enable_v1(struct udevice *dev, uint channel, bool enable)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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const struct rockchip_pwm_regs *regs = &priv->data->regs;
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u32 ctrl;
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debug("%s: Enable '%s'\n", __func__, dev->name);
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ctrl = readl(priv->base + regs->ctrl);
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ctrl &= ~priv->data->enable_conf_mask;
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if (enable)
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ctrl |= priv->data->enable_conf;
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else
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ctrl &= ~priv->data->enable_conf;
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writel(ctrl, priv->base + regs->ctrl);
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if (priv->data->vop_pwm)
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priv->vop_pwm_en = enable;
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if (enable)
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pinctrl_select_state(dev, "active");
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return 0;
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}
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static int rk_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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return priv->data->funcs.set_enable(dev, channel, enable);
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}
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static int rk_pwm_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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return 0;
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}
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static int rk_pwm_probe(struct udevice *dev)
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{
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struct rk_pwm_priv *priv = dev_get_priv(dev);
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struct clk clk;
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int ret = 0;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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debug("%s get clock fail!\n", __func__);
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return -EINVAL;
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}
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ret = clk_get_rate(&clk);
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if (ret < 0) {
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debug("%s pwm get clock rate fail!\n", __func__);
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return -EINVAL;
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}
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priv->freq = ret;
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priv->data = (struct rockchip_pwm_data *)dev_get_driver_data(dev);
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if (priv->data->supports_polarity)
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priv->conf_polarity = PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE;
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return 0;
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}
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static const struct pwm_ops rk_pwm_ops = {
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.set_invert = rk_pwm_set_invert,
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.set_config = rk_pwm_set_config,
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.set_enable = rk_pwm_set_enable,
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};
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static const struct rockchip_pwm_data pwm_data_v1 = {
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.main_version = 0x01,
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.regs = {
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.version = 0x5c,
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.duty = 0x04,
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.period = 0x08,
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.ctrl = 0x0c,
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},
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.prescaler = 2,
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.supports_polarity = false,
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.supports_lock = false,
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.vop_pwm = false,
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.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
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.enable_conf_mask = BIT(1) | BIT(3),
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.funcs = {
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.set_invert = rk_pwm_set_invert_v1,
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.set_config = rk_pwm_set_config_v1,
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.set_enable = rk_pwm_set_enable_v1,
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},
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};
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static const struct rockchip_pwm_data pwm_data_v2 = {
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.main_version = 0x02,
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.regs = {
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.version = 0x5c,
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.duty = 0x08,
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.period = 0x04,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = false,
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.vop_pwm = false,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
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PWM_CONTINUOUS,
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.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
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.funcs = {
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.set_invert = rk_pwm_set_invert_v1,
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.set_config = rk_pwm_set_config_v1,
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.set_enable = rk_pwm_set_enable_v1,
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},
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};
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static const struct rockchip_pwm_data pwm_data_vop = {
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.main_version = 0x02,
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.regs = {
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.version = 0x5c,
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.duty = 0x08,
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.period = 0x04,
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.ctrl = 0x00,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = false,
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.vop_pwm = true,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
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PWM_CONTINUOUS,
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.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
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.funcs = {
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.set_invert = rk_pwm_set_invert_v1,
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.set_config = rk_pwm_set_config_v1,
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.set_enable = rk_pwm_set_enable_v1,
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},
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};
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static const struct rockchip_pwm_data pwm_data_v3 = {
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.main_version = 0x03,
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.regs = {
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.version = 0x5c,
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.duty = 0x08,
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.period = 0x04,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = true,
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.vop_pwm = false,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | RK_PWM_ENABLE |
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PWM_CONTINUOUS,
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.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
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.funcs = {
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.set_invert = rk_pwm_set_invert_v1,
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.set_config = rk_pwm_set_config_v1,
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.set_enable = rk_pwm_set_enable_v1,
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},
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};
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static const struct rockchip_pwm_data pwm_data_v4 = {
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.main_version = 0x04,
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.regs = {
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.version = 0x0,
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.enable = 0x4,
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.ctrl = 0xc,
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.period = 0x10,
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.duty = 0x14,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = true,
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.vop_pwm = false,
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.enable_conf = PWM_ENABLE_V4,
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.funcs = {
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.set_invert = rk_pwm_set_invert_v4,
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.set_config = rk_pwm_set_config_v4,
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.set_enable = rk_pwm_set_enable_v4,
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},
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};
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static const struct udevice_id rk_pwm_ids[] = {
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{ .compatible = "rockchip,rk2928-pwm", .data = (ulong)&pwm_data_v1},
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{ .compatible = "rockchip,rk3288-pwm", .data = (ulong)&pwm_data_v2},
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{ .compatible = "rockchip,rk3328-pwm", .data = (ulong)&pwm_data_v3},
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{ .compatible = "rockchip,vop-pwm", .data = (ulong)&pwm_data_vop},
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{ .compatible = "rockchip,rk3399-pwm", .data = (ulong)&pwm_data_v2},
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{ .compatible = "rockchip,rk3576-pwm", .data = (ulong)&pwm_data_v4},
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{ }
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};
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U_BOOT_DRIVER(rk_pwm) = {
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.name = "rk_pwm",
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.id = UCLASS_PWM,
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.of_match = rk_pwm_ids,
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.ops = &rk_pwm_ops,
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.ofdata_to_platdata = rk_pwm_ofdata_to_platdata,
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.probe = rk_pwm_probe,
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.priv_auto_alloc_size = sizeof(struct rk_pwm_priv),
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};
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