8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
286 lines
8.0 KiB
C
286 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2024 Rockchip Electronics Co.Ltd.
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <linux/err.h>
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#include <linux/ioport.h>
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#include <ufs.h>
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#include "ufs.h"
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#include "unipro.h"
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#include "ufs-rockchip.h"
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extern int ufshcd_dme_enable(struct ufs_hba *hba);
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static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
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{
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return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
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}
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#if !defined(CONFIG_SPL_BUILD)
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static int ufs_rockchip_test_linkup(struct ufs_hba *hba)
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{
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unsigned long start = 0;
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u32 intr_status;
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u32 enabled_intr_status;
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/* Write Args */
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ufshcd_writel(hba, 0, REG_UIC_COMMAND_ARG_1);
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ufshcd_writel(hba, 0, REG_UIC_COMMAND_ARG_2);
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ufshcd_writel(hba, 0, REG_UIC_COMMAND_ARG_3);
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/* Write UIC Cmd */
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ufshcd_writel(hba, UIC_CMD_DME_LINK_STARTUP & COMMAND_OPCODE_MASK, REG_UIC_COMMAND);
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start = get_timer(0);
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do {
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intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
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enabled_intr_status = intr_status & hba->intr_mask;
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ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
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if (get_timer(start) > 50) {
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dev_err(hba->dev,
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"Timedout waiting for UIC response\n");
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return -ETIMEDOUT;
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}
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if (enabled_intr_status & UFSHCD_ERROR_MASK) {
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dev_err(hba->dev, "Error in status:%08x\n",
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enabled_intr_status);
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return -1;
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}
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} while (!(enabled_intr_status & UFSHCD_UIC_MASK));
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return 0;
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}
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#endif
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static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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if (status == POST_CHANGE) {
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ufshcd_dme_reset(hba);
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ufshcd_dme_enable(hba);
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#if !defined(CONFIG_SPL_BUILD)
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/* Try linkup to test if mphy has power supply */
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if (ufs_rockchip_test_linkup(hba)) {
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return -EIO;
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} else {
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ufshcd_dme_reset(hba);
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ufshcd_dme_enable(hba);
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}
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#endif
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if (hba->ops->phy_initialization) {
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err = hba->ops->phy_initialization(hba);
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if (err) {
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dev_err(hba->dev, "Phy setup failed (%d)\n", err);
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}
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}
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}
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return err;
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}
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static const unsigned char rk3576_phy_value[15][4] = {
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{0x03, 0x38, 0x50, 0x80},
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{0x03, 0x14, 0x58, 0x80},
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{0x03, 0x26, 0x58, 0x80},
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{0x03, 0x49, 0x58, 0x80},
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{0x03, 0x5A, 0x58, 0x80},
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{0xC3, 0x38, 0x50, 0xC0},
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{0xC3, 0x14, 0x58, 0xC0},
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{0xC3, 0x26, 0x58, 0xC0},
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{0xC3, 0x49, 0x58, 0xC0},
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{0xC3, 0x5A, 0x58, 0xC0},
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{0x43, 0x38, 0x50, 0xC0},
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{0x43, 0x14, 0x58, 0xC0},
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{0x43, 0x26, 0x58, 0xC0},
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{0x43, 0x49, 0x58, 0xC0},
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{0x43, 0x5A, 0x58, 0xC0}
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};
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static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
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{
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struct ufs_rockchip_host *host = dev_get_priv(hba->dev);
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int try_case = host->phy_config_mode, value;
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
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/* enable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x40);
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for (int i = 0; i < 2; i++) {
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/* Configuration M-TX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xaa, SEL_TX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xa9, SEL_TX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xad, SEL_TX_LANE0 + i), 0x44);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xac, SEL_TX_LANE0 + i), 0xe6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xab, SEL_TX_LANE0 + i), 0x07);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x94, SEL_TX_LANE0 + i), 0x93);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x93, SEL_TX_LANE0 + i), 0xc9);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7f, SEL_TX_LANE0 + i), 0x00);
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/* Configuration M-RX */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, SEL_RX_LANE0 + i), 0x06);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x11, SEL_RX_LANE0 + i), 0x00);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1d, SEL_RX_LANE0 + i), 0x58);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1c, SEL_RX_LANE0 + i), 0x8c);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1b, SEL_RX_LANE0 + i), 0x02);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, SEL_RX_LANE0 + i), 0xf6);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, SEL_RX_LANE0 + i), 0x69);
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}
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/* disable the mphy DME_SET cfg */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x200, 0x0), 0x00);
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ufs_sys_writel(host->mphy_base, 0x80, 0x08C);
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ufs_sys_writel(host->mphy_base, 0xB5, 0x110);
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ufs_sys_writel(host->mphy_base, 0xB5, 0x250);
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value = rk3576_phy_value[try_case][0];
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ufs_sys_writel(host->mphy_base, value, 0x134);
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ufs_sys_writel(host->mphy_base, value, 0x274);
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value = rk3576_phy_value[try_case][1];
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ufs_sys_writel(host->mphy_base, value, 0x0E0);
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ufs_sys_writel(host->mphy_base, value, 0x220);
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value = rk3576_phy_value[try_case][2];
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ufs_sys_writel(host->mphy_base, value, 0x164);
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ufs_sys_writel(host->mphy_base, value, 0x2A4);
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value = rk3576_phy_value[try_case][3];
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ufs_sys_writel(host->mphy_base, value, 0x178);
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ufs_sys_writel(host->mphy_base, value, 0x2B8);
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ufs_sys_writel(host->mphy_base, 0x18, 0x1B0);
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ufs_sys_writel(host->mphy_base, 0x18, 0x2F0);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x120);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x260);
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ufs_sys_writel(host->mphy_base, 0x03, 0x094);
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ufs_sys_writel(host->mphy_base, 0x03, 0x1B4);
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ufs_sys_writel(host->mphy_base, 0x03, 0x2F4);
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ufs_sys_writel(host->mphy_base, 0xC0, 0x08C);
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udelay(1);
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ufs_sys_writel(host->mphy_base, 0x00, 0x08C);
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udelay(200);
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/* start link up */
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
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ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
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return 0;
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}
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static int ufs_rockchip_common_init(struct ufs_hba *hba)
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{
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struct udevice *dev = hba->dev;
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struct ufs_rockchip_host *host = dev_get_priv(dev);
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struct resource res;
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int err = 0;
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/* system control register for hci */
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err = dev_read_resource_byname(dev, "hci_grf", &res);
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if (err) {
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dev_err(dev, "cannot ioremap for hci system control register\n");
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return -ENODEV;
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}
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host->ufs_sys_ctrl = (void *)(res.start);
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/* system control register for mphy */
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err = dev_read_resource_byname(dev, "mphy_grf", &res);
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if (err) {
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dev_err(dev, "cannot ioremap for mphy system control register\n");
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return -ENODEV;
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}
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host->ufs_phy_ctrl = (void *)(res.start);
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/* mphy base register */
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err = dev_read_resource_byname(dev, "mphy", &res);
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if (err) {
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dev_err(dev, "cannot ioremap for mphy base register\n");
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return -ENODEV;
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}
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host->mphy_base = (void *)(res.start);
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host->phy_config_mode = dev_read_u32_default(dev, "ufs-phy-config-mode", 0);
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host->hba = hba;
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return 0;
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}
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static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
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{
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int ret = 0;
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ret = ufs_rockchip_common_init(hba);
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if (ret) {
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dev_err(hba->dev, "%s: ufs common init fail\n", __func__);
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return ret;
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}
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/* UFS PHY select 26M from ppll */
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writel(0x00030002, 0x2722030C);
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/* set UFS_REFCLK, UFS_RSTN */
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writel(0x00FF0011, 0x2604B398);
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udelay(20);
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writel(0x00100010, 0x2604B400);
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return 0;
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}
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static struct ufs_hba_ops ufs_hba_rk3576_vops = {
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.init = ufs_rockchip_rk3576_init,
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.phy_initialization = ufs_rockchip_rk3576_phy_init,
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.hce_enable_notify = ufs_rockchip_hce_enable_notify,
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};
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static const struct udevice_id ufs_rockchip_of_match[] = {
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{ .compatible = "rockchip,rk3576-ufs", .data = (ulong)&ufs_hba_rk3576_vops},
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{},
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};
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static int ufs_rockchip_probe(struct udevice *dev)
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{
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struct ufs_hba_ops *ops = (struct ufs_hba_ops *)dev_get_driver_data(dev);
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int err;
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err = ufshcd_probe(dev, ops);
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if (err)
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dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
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return err;
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}
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static int ufs_rockchip_bind(struct udevice *dev)
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{
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struct udevice *scsi_dev;
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return ufs_scsi_bind(dev, &scsi_dev);
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}
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U_BOOT_DRIVER(ti_j721e_ufs) = {
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.name = "ufshcd-rockchip",
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.id = UCLASS_UFS,
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.of_match = ufs_rockchip_of_match,
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.probe = ufs_rockchip_probe,
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.bind = ufs_rockchip_bind,
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.priv_auto_alloc_size = sizeof(struct ufs_rockchip_host),
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};
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