8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
68 lines
1.3 KiB
C
68 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2022 Rockchip Electronics Co., Ltd
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*/
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#ifndef _MAX96745_H_
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#define _MAX96745_H_
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#include <linux/bitfield.h>
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#define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 8))
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#define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 8))
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#define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 8))
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#define GPIO_D_REG(gpio) (0x0203 + ((gpio) * 8))
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/* 0010h */
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#define RESET_ALL BIT(7)
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#define SLEEP BIT(3)
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/* 0011h */
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#define CXTP_B BIT(2)
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#define CXTP_A BIT(0)
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/* 0028h, 0032h */
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#define LINK_EN BIT(7)
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#define TX_RATE GENMASK(3, 2)
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/* 0029h, 0033h */
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#define RESET_LINK BIT(0)
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#define RESET_ONESHOT BIT(1)
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/* 002Ah, 0034h */
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#define LINK_LOCKED BIT(0)
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/* 0076h, 0086h */
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#define DIS_REM_CC BIT(7)
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/* 0100h */
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#define VID_LINK_SEL GENMASK(2, 1)
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#define VID_TX_EN BIT(0)
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/* 0200h */
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#define RES_CFG BIT(7)
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#define TX_COM_EN BIT(5)
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#define GPIO_OUT BIT(4)
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#define GPIO_IN BIT(3)
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#define GPIO_OUT_DIS BIT(0)
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/* 0201h */
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#define PULL_UPDN_SEL GENMASK(7, 6)
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#define OUT_TYPEC BIT(5)
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#define GPIO_TX_ID GENMASK(4, 0)
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/* 0202h */
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#define OVR_RES_CFG BIT(7)
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#define IO_EDGE_RATE GENMASK(6, 5)
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#define GPIO_RX_ID GENMASK(4, 0)
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/* 0203h */
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#define GPIO_IO_RX_EN BIT(5)
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#define GPIO_OUT_LGC BIT(4)
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#define GPIO_RX_EN_B BIT(3)
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#define GPIO_TX_EN_B BIT(2)
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#define GPIO_RX_EN_A BIT(1)
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#define GPIO_TX_EN_A BIT(0)
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#endif
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