8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
369 lines
10 KiB
C
369 lines
10 KiB
C
/**
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******************************************************************************
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*
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* @file rwnx_rx.h
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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******************************************************************************
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*/
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#ifndef _RWNX_RX_H_
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#define _RWNX_RX_H_
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#include "aicwf_txrxif.h"
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#define SERVER_PORT 67
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#define CLIENT_PORT 68
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#define DHCP_MAGIC 0x63825363
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#define DHCP_ACK 5
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#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */
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#define DHCP_OPTION_END 255
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enum rx_status_bits
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{
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/// The buffer can be forwarded to the networking stack
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RX_STAT_FORWARD = 1 << 0,
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/// A new buffer has to be allocated
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RX_STAT_ALLOC = 1 << 1,
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/// The buffer has to be deleted
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RX_STAT_DELETE = 1 << 2,
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/// The length of the buffer has to be updated
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RX_STAT_LEN_UPDATE = 1 << 3,
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/// The length in the Ethernet header has to be updated
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RX_STAT_ETH_LEN_UPDATE = 1 << 4,
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/// Simple copy
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RX_STAT_COPY = 1 << 5,
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/// Spurious frame (inform upper layer and discard)
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RX_STAT_SPURIOUS = 1 << 6,
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/// packet for monitor interface
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RX_STAT_MONITOR = 1 << 7,
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};
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/*
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* Decryption status subfields.
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* {
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*/
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#define RWNX_RX_HD_DECR_UNENC 0 // ENCRYPTION TYPE NONE
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#define RWNX_RX_HD_DECR_WEP 1 // ENCRYPTION TYPE WEP
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#define RWNX_RX_HD_DECR_TKIP 2 // ENCRYPTION TYPE TKIP
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#define RWNX_RX_HD_DECR_CCMP128 3 // ENCRYPTION TYPE CCMP128
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#define RWNX_RX_HD_DECR_CCMP256 4 // ENCRYPTION TYPE CCMP256
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#define RWNX_RX_HD_DECR_GCMP128 5 // ENCRYPTION TYPE GCMP128
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#define RWNX_RX_HD_DECR_GCMP256 6 // ENCRYPTION TYPE GCMP256
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#define RWNX_RX_HD_DECR_WAPI 7 // ENCRYPTION TYPE WAPI
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// @}
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//#ifdef CONFIG_RWNX_MON_DATA
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#if 0
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#define RX_MACHDR_BACKUP_LEN 64
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#endif
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struct rx_vector_1_old {
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/** Receive Vector 1a */
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u32 leg_length :12;
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u32 leg_rate : 4;
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u32 ht_length :16;
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/** Receive Vector 1b */
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u32 _ht_length : 4; // FIXME
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u32 short_gi : 1;
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u32 stbc : 2;
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u32 smoothing : 1;
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u32 mcs : 7;
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u32 pre_type : 1;
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u32 format_mod : 3;
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u32 ch_bw : 2;
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u32 n_sts : 3;
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u32 lsig_valid : 1;
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u32 sounding : 1;
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u32 num_extn_ss : 2;
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u32 aggregation : 1;
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u32 fec_coding : 1;
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u32 dyn_bw : 1;
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u32 doze_not_allowed : 1;
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/** Receive Vector 1c */
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u32 antenna_set : 8;
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u32 partial_aid : 9;
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u32 group_id : 6;
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u32 first_user : 1;
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s32 rssi1 : 8;
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/** Receive Vector 1d */
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s32 rssi2 : 8;
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s32 rssi3 : 8;
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s32 rssi4 : 8;
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u32 reserved_1d : 8;
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};
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struct rx_leg_vect
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{
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u8 dyn_bw_in_non_ht : 1;
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u8 chn_bw_in_non_ht : 2;
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u8 rsvd_nht : 4;
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u8 lsig_valid : 1;
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} __packed;
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struct rx_ht_vect
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{
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u16 sounding : 1;
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u16 smoothing : 1;
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u16 short_gi : 1;
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u16 aggregation : 1;
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u16 stbc : 1;
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u16 num_extn_ss : 2;
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u16 lsig_valid : 1;
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u16 mcs : 7;
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u16 fec : 1;
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u16 length :16;
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} __packed;
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struct rx_vht_vect
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{
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u8 sounding : 1;
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u8 beamformed : 1;
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u8 short_gi : 1;
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u8 rsvd_vht1 : 1;
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u8 stbc : 1;
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u8 doze_not_allowed : 1;
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u8 first_user : 1;
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u8 rsvd_vht2 : 1;
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u16 partial_aid : 9;
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u16 group_id : 6;
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u16 rsvd_vht3 : 1;
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u32 mcs : 4;
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u32 nss : 3;
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u32 fec : 1;
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u32 length :20;
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u32 rsvd_vht4 : 4;
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} __packed;
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struct rx_he_vect
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{
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u8 sounding : 1;
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u8 beamformed : 1;
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u8 gi_type : 2;
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u8 stbc : 1;
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u8 rsvd_he1 : 3;
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u8 uplink_flag : 1;
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u8 beam_change : 1;
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u8 dcm : 1;
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u8 he_ltf_type : 2;
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u8 doppler : 1;
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u8 rsvd_he2 : 2;
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u8 bss_color : 6;
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u8 rsvd_he3 : 2;
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u8 txop_duration : 7;
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u8 rsvd_he4 : 1;
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u8 pe_duration : 4;
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u8 spatial_reuse : 4;
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u8 sig_b_comp_mode : 1;
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u8 dcm_sig_b : 1;
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u8 mcs_sig_b : 3;
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u8 ru_size : 3;
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u32 mcs : 4;
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u32 nss : 3;
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u32 fec : 1;
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u32 length :20;
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u32 rsvd_he6 : 4;
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} __packed;
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struct rx_vector_1 {
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u8 format_mod : 4;
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u8 ch_bw : 3;
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u8 pre_type : 1;
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u8 antenna_set : 8;
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s32 rssi_leg : 8;
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u32 leg_length :12;
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u32 leg_rate : 4;
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s32 rssi1 : 8;
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union
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{
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struct rx_leg_vect leg;
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struct rx_ht_vect ht;
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struct rx_vht_vect vht;
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struct rx_he_vect he;
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};
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} __packed;
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struct rx_vector_2_old {
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/** Receive Vector 2a */
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u32 rcpi : 8;
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u32 evm1 : 8;
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u32 evm2 : 8;
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u32 evm3 : 8;
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/** Receive Vector 2b */
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u32 evm4 : 8;
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u32 reserved2b_1 : 8;
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u32 reserved2b_2 : 8;
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u32 reserved2b_3 : 8;
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};
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struct rx_vector_2 {
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/** Receive Vector 2a */
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u32 rcpi1 : 8;
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u32 rcpi2 : 8;
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u32 rcpi3 : 8;
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u32 rcpi4 : 8;
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/** Receive Vector 2b */
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u32 evm1 : 8;
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u32 evm2 : 8;
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u32 evm3 : 8;
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u32 evm4 : 8;
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};
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struct phy_channel_info_desc {
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/** PHY channel information 1 */
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u32 phy_band : 8;
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u32 phy_channel_type : 8;
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u32 phy_prim20_freq : 16;
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/** PHY channel information 2 */
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u32 phy_center1_freq : 16;
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u32 phy_center2_freq : 16;
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};
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struct hw_vect {
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/** Total length for the MPDU transfer */
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u32 len :16;
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u32 reserved : 8;//data type is included
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/** AMPDU Status Information */
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u32 mpdu_cnt : 6;
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u32 ampdu_cnt : 2;
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/** TSF Low */
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__le32 tsf_lo;
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/** TSF High */
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__le32 tsf_hi;
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/** Receive Vector 1 */
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struct rx_vector_1 rx_vect1;
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/** Receive Vector 2 */
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struct rx_vector_2 rx_vect2;
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/** Status **/
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u32 rx_vect2_valid : 1;
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u32 resp_frame : 1;
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/** Decryption Status */
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u32 decr_status : 3;
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u32 rx_fifo_oflow : 1;
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/** Frame Unsuccessful */
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u32 undef_err : 1;
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u32 phy_err : 1;
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u32 fcs_err : 1;
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u32 addr_mismatch : 1;
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u32 ga_frame : 1;
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u32 current_ac : 2;
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u32 frm_successful_rx : 1;
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/** Descriptor Done */
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u32 desc_done_rx : 1;
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/** Key Storage RAM Index */
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u32 key_sram_index : 10;
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/** Key Storage RAM Index Valid */
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u32 key_sram_v : 1;
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u32 type : 2;
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u32 subtype : 4;
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};
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//#ifdef CONFIG_RWNX_MON_DATA
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#if 0
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/// MAC header backup descriptor
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struct mon_machdrdesc
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{
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/// Length of the buffer
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u32 buf_len;
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/// Buffer containing mac header, LLC and SNAP
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u8 buffer[RX_MACHDR_BACKUP_LEN];
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};
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#endif
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struct hw_rxhdr_t {
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/** RX vector */
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struct hw_vect hwvect;
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/** PHY channel information */
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struct phy_channel_info_desc phy_info;
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/** RX flags */
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u32 flags_is_amsdu : 1;
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u32 flags_is_80211_mpdu: 1;
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u32 flags_is_4addr : 1;
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u32 flags_new_peer : 1;
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#if defined(AICWF_SDIO_SUPPORT) || defined(AICWF_USB_SUPPORT)
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u32 flags_user_prio : 1; // aic: fw not fill any more
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u32 flags_need_reord : 1;
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u32 flags_upload : 1;
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#else
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u32 flags_user_prio : 3;
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#endif
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#ifndef AICWF_RX_REORDER
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u32 flags_rsvd0 : 1;
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#else
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u32 is_monitor_vif : 1;
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#endif
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u32 flags_vif_idx : 8; // 0xFF if invalid VIF index
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u32 flags_sta_idx : 8; // 0xFF if invalid STA index
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u32 flags_dst_idx : 8; // 0xFF if unknown destination STA
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//#ifdef CONFIG_RWNX_MON_DATA
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#if 0
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/// MAC header backup descriptor (used only for MSDU when there is a monitor and a data interface)
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struct mon_machdrdesc mac_hdr_backup;
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#endif
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/** Pattern indicating if the buffer is available for the driver */
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u32 pattern;
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};
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struct mac_hdr_t
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{
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u16 fctl;
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u16 durid;
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u8 addr1[MAC_ADDR_LEN];
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u8 addr2[MAC_ADDR_LEN];
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u8 addr3[MAC_ADDR_LEN];
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u16 seq;
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};
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typedef struct
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{
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struct hw_rxhdr_t hw_rxhdr;
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u16 rsvd1[2];
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u8 payload[1600];
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}rx_buff_tag;
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u8 rwnx_rxdataind(void *pthis, void *hostid);
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//u8 rwnx_rxdataind_aicwf(struct rwnx_hw *rwnx_hw, void *hostid, void *rx_priv);
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int aicwf_process_rxframes(struct aicwf_rx_priv *rx_priv);
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#ifdef AICWF_RX_REORDER
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struct recv_msdu *reord_rxframe_alloc(spinlock_t *lock, struct list_head *q);
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void reord_rxframe_free(spinlock_t *lock, struct list_head *q, struct list_head *list);
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struct reord_ctrl_info *reord_init_sta( struct aicwf_rx_priv *rx_priv, const u8 *mac_addr);
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void reord_deinit_sta(struct aicwf_rx_priv *rx_priv, struct reord_ctrl_info *reord_info);
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int reord_need_check(struct reord_ctrl *preorder_ctrl, u16 seq_num);
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int reord_rxframe_enqueue(struct reord_ctrl *preorder_ctrl, struct recv_msdu *prframe);
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void reord_timeout_worker(struct work_struct *work);
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int reord_single_frame_ind(struct aicwf_rx_priv *rx_priv, struct recv_msdu *prframe);
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
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void reord_timeout_handler (ulong data);
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#else
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void reord_timeout_handler (struct timer_list *t);
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#endif
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#endif
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void rwnx_rx_handle_msg( void *dev, struct ipc_e2a_msg *msg);
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void rwnx_rx_handle_data( struct aicwf_rx_priv *rx_priv, struct sk_buff *skb);
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#endif /* _RWNX_RX_H_ */
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