8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
/*
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* HND SiliconBackplane PMU support.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#ifndef _hndlhl_h_
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#define _hndlhl_h_
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enum {
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LHL_MAC_TIMER = 0,
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LHL_ARM_TIMER = 1
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};
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typedef struct {
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uint16 offset;
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uint32 mask;
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uint32 val;
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} lhl_reg_set_t;
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#define LHL_REG_OFF(reg) OFFSETOF(gciregs_t, reg)
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extern void si_lhl_timer_config(si_t *sih, osl_t *osh, int timer_type);
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extern void si_lhl_timer_enable(si_t *sih);
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extern void si_lhl_timer_reset(si_t *sih, uint coreid, uint coreunit);
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extern void si_lhl_setup(si_t *sih, osl_t *osh);
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extern void si_lhl_enable(si_t *sih, osl_t *osh, bool enable);
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extern void si_lhl_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period);
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extern void si_lhl_enable_sdio_wakeup(si_t *sih, osl_t *osh);
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extern void si_lhl_disable_sdio_wakeup(si_t *sih);
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extern int si_lhl_set_lpoclk(si_t *sih, osl_t *osh, uint32 lpo_force);
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extern void si_set_lv_sleep_mode_lhl_config_4369(si_t *sih);
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extern void si_set_lv_sleep_mode_lhl_config_4362(si_t *sih);
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extern void si_set_lv_sleep_mode_lhl_config_4378(si_t *sih);
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extern void si_set_lv_sleep_mode_lhl_config_4387(si_t *sih);
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extern void si_set_lv_sleep_mode_lhl_config_4389(si_t *sih);
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#define HIB_EXT_WAKEUP_CAP(sih) (PMUREV(sih->pmurev) >= 33)
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#ifdef WL_FWSIGN
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#define LHL_IS_PSMODE_0(sih) (1)
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#define LHL_IS_PSMODE_1(sih) (0)
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#else
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#define LHL_IS_PSMODE_0(sih) (si_lhl_ps_mode(sih) == LHL_PS_MODE_0)
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#define LHL_IS_PSMODE_1(sih) (si_lhl_ps_mode(sih) == LHL_PS_MODE_1)
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#endif /* WL_FWSIGN */
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/* LHL revid in capabilities register */
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#define LHL_CAP_REV_MASK 0x000000ff
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/* LHL rev 6 requires this bit to be set first */
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#define LHL_PWRSEQCTL_WL_FLLPU_EN (1 << 7)
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#define LHL_CBUCK_VOLT_SLEEP_SHIFT 12u
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#define LHL_CBUCK_VOLT_SLEEP_MASK 0x0000F000
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#define LHL_ABUCK_VOLT_SLEEP_SHIFT 0u
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#define LHL_ABUCK_VOLT_SLEEP_MASK 0x0000000F
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extern void si_lhl_mactim0_set(si_t *sih, uint32 val);
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/* LHL Chip Control 1 Register */
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#define LHL_1MHZ_FLL_DAC_EXT_SHIFT (9u)
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#define LHL_1MHZ_FLL_DAC_EXT_MASK (0xffu << 9u)
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#define LHL_1MHZ_FLL_PRELOAD_MASK (1u << 17u)
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/* LHL Top Level Power Sequence Control Register */
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#define LHL_TOP_PWRSEQ_SLEEP_ENAB_MASK (1u << 0)
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#define LHL_TOP_PWRSEQ_TOP_ISO_EN_MASK (1u << 3u)
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#define LHL_TOP_PWRSEQ_TOP_SLB_EN_MASK (1u << 4u)
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#define LHL_TOP_PWRSEQ_TOP_PWRSW_EN_MASK (1u << 5u)
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#define LHL_TOP_PWRSEQ_MISCLDO_PU_EN_MASK (1u << 6u)
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#define LHL_TOP_PWRSEQ_SERDES_SLB_EN_MASK (1u << 9u)
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#define LHL_TOP_PWRSEQ_SERDES_CLK_DIS_EN_MASK (1u << 10u)
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#endif /* _hndlhl_h_ */
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