8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
157 lines
6.2 KiB
C
157 lines
6.2 KiB
C
/**
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******************************************************************************
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*
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* @file reg_access.h
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*
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* @brief Definitions and macros for MAC HW and platform register accesses
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*
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* Copyright (C) RivieraWaves 2011-2019
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*
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******************************************************************************
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*/
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#ifndef REG_ACCESS_H_
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#define REG_ACCESS_H_
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/*****************************************************************************
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* Addresses within RWNX_ADDR_CPU
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*****************************************************************************/
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#define RAM_LMAC_FW_ADDR 0x00000000
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#define ROM_FMAC_FW_ADDR 0x00010000
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#define RAM_FMAC_FW_ADDR 0x00120000
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/*****************************************************************************
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* Addresses within RWNX_ADDR_SYSTEM
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*****************************************************************************/
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/* Shard RAM */
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#define SHARED_RAM_START_ADDR 0x00000000
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/* IPC registers */
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#define IPC_REG_BASE_ADDR 0x00800000
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/* System Controller Registers */
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#define SYSCTRL_SIGNATURE_ADDR 0x00900000
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// old diag register name
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#define SYSCTRL_DIAG_CONF_ADDR 0x00900068
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#define SYSCTRL_PHYDIAG_CONF_ADDR 0x00900074
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#define SYSCTRL_RIUDIAG_CONF_ADDR 0x00900078
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// new diag register name
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#define SYSCTRL_DIAG_CONF0 0x00900064
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#define SYSCTRL_DIAG_CONF1 0x00900068
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#define SYSCTRL_DIAG_CONF2 0x00900074
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#define SYSCTRL_DIAG_CONF3 0x00900078
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#define SYSCTRL_MISC_CNTL_ADDR 0x009000E0
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#define BOOTROM_ENABLE BIT(4)
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#define FPGA_B_RESET BIT(1)
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#define SOFT_RESET BIT(0)
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/* MAC platform */
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#define NXMAC_VERSION_1_ADDR 0x00B00004
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#define NXMAC_MU_MIMO_TX_BIT BIT(19)
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#define NXMAC_BFMER_BIT BIT(18)
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#define NXMAC_BFMEE_BIT BIT(17)
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#define NXMAC_MAC_80211MH_FORMAT_BIT BIT(16)
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#define NXMAC_COEX_BIT BIT(14)
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#define NXMAC_WAPI_BIT BIT(13)
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#define NXMAC_TPC_BIT BIT(12)
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#define NXMAC_VHT_BIT BIT(11)
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#define NXMAC_HT_BIT BIT(10)
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#define NXMAC_RCE_BIT BIT(8)
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#define NXMAC_CCMP_BIT BIT(7)
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#define NXMAC_TKIP_BIT BIT(6)
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#define NXMAC_WEP_BIT BIT(5)
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#define NXMAC_SECURITY_BIT BIT(4)
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#define NXMAC_SME_BIT BIT(3)
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#define NXMAC_HCCA_BIT BIT(2)
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#define NXMAC_EDCA_BIT BIT(1)
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#define NXMAC_QOS_BIT BIT(0)
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#define NXMAC_RX_CNTRL_ADDR 0x00B00060
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#define NXMAC_EN_DUPLICATE_DETECTION_BIT BIT(31)
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#define NXMAC_ACCEPT_UNKNOWN_BIT BIT(30)
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#define NXMAC_ACCEPT_OTHER_DATA_FRAMES_BIT BIT(29)
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#define NXMAC_ACCEPT_QO_S_NULL_BIT BIT(28)
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#define NXMAC_ACCEPT_QCFWO_DATA_BIT BIT(27)
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#define NXMAC_ACCEPT_Q_DATA_BIT BIT(26)
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#define NXMAC_ACCEPT_CFWO_DATA_BIT BIT(25)
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#define NXMAC_ACCEPT_DATA_BIT BIT(24)
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#define NXMAC_ACCEPT_OTHER_CNTRL_FRAMES_BIT BIT(23)
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#define NXMAC_ACCEPT_CF_END_BIT BIT(22)
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#define NXMAC_ACCEPT_ACK_BIT BIT(21)
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#define NXMAC_ACCEPT_CTS_BIT BIT(20)
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#define NXMAC_ACCEPT_RTS_BIT BIT(19)
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#define NXMAC_ACCEPT_PS_POLL_BIT BIT(18)
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#define NXMAC_ACCEPT_BA_BIT BIT(17)
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#define NXMAC_ACCEPT_BAR_BIT BIT(16)
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#define NXMAC_ACCEPT_OTHER_MGMT_FRAMES_BIT BIT(15)
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#define NXMAC_ACCEPT_BFMEE_FRAMES_BIT BIT(14)
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#define NXMAC_ACCEPT_ALL_BEACON_BIT BIT(13)
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#define NXMAC_ACCEPT_NOT_EXPECTED_BA_BIT BIT(12)
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#define NXMAC_ACCEPT_DECRYPT_ERROR_FRAMES_BIT BIT(11)
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#define NXMAC_ACCEPT_BEACON_BIT BIT(10)
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#define NXMAC_ACCEPT_PROBE_RESP_BIT BIT(9)
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#define NXMAC_ACCEPT_PROBE_REQ_BIT BIT(8)
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#define NXMAC_ACCEPT_MY_UNICAST_BIT BIT(7)
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#define NXMAC_ACCEPT_UNICAST_BIT BIT(6)
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#define NXMAC_ACCEPT_ERROR_FRAMES_BIT BIT(5)
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#define NXMAC_ACCEPT_OTHER_BSSID_BIT BIT(4)
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#define NXMAC_ACCEPT_BROADCAST_BIT BIT(3)
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#define NXMAC_ACCEPT_MULTICAST_BIT BIT(2)
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#define NXMAC_DONT_DECRYPT_BIT BIT(1)
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#define NXMAC_EXC_UNENCRYPTED_BIT BIT(0)
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#define NXMAC_DEBUG_PORT_SEL_ADDR 0x00B00510
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#define NXMAC_SW_SET_PROFILING_ADDR 0x00B08564
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#define NXMAC_SW_CLEAR_PROFILING_ADDR 0x00B08568
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/* Modem Status */
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#define MDM_HDMCONFIG_ADDR 0x00C00000
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/* Clock gating configuration */
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#define MDM_MEMCLKCTRL0_ADDR 0x00C00848
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#define MDM_CLKGATEFCTRL0_ADDR 0x00C00874
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#define CRM_CLKGATEFCTRL0_ADDR 0x00940010
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/* AGC (trident) */
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#define AGC_RWNXAGCCNTL_ADDR 0x00C02060
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/* LDPC RAM*/
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#define PHY_LDPC_RAM_ADDR 0x00C09000
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/* FCU (elma )*/
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#define FCU_RWNXFCAGCCNTL_ADDR 0x00C09034
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/* AGC RAM */
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#define PHY_AGC_UCODE_ADDR 0x00C0A000
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/* RIU */
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#define RIU_RWNXVERSION_ADDR 0x00C0B000
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#define RIU_RWNXDYNAMICCONFIG_ADDR 0x00C0B008
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#define RIU_AGCMEMBISTSTAT_ADDR 0x00C0B238
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#define RIU_AGCMEMSIGNATURESTAT_ADDR 0x00C0B23C
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#define RIU_RWNXAGCCNTL_ADDR 0x00C0B390
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/* FCU RAM */
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#define PHY_FCU_UCODE_ADDR 0x00C0E000
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/* RF ITF */
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#define FPGAB_MPIF_SEL_ADDR 0x00C10030
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#define RF_V6_DIAGPORT_CONF1_ADDR 0x00C10010
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#define RF_v6_PHYDIAG_CONF1_ADDR 0x00C10018
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#define RF_V7_DIAGPORT_CONF1_ADDR 0x00F10010
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#define RF_v7_PHYDIAG_CONF1_ADDR 0x00F10018
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/*****************************************************************************
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* Macros for generated register files
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*****************************************************************************/
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/* Macros for IPC registers access (used in reg_ipc_app.h) */
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#define REG_IPC_APP_RD(env, INDEX) \
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(*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)))
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#define REG_IPC_APP_WR(env, INDEX, value) \
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(*(volatile u32*)((u8*)env + IPC_REG_BASE_ADDR + 4*(INDEX)) = value)
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#endif /* REG_ACCESS_H_ */
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