8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
437 lines
14 KiB
C
437 lines
14 KiB
C
#ifndef __IPC_MSG_H__
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#define __IPC_MSG_H__
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/*******************************************************************************
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* Include Files
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******************************************************************************/
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#include "rf_table.h"
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/*******************************************************************************
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* Defines
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******************************************************************************/
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#ifndef SSV_PACKED_STRUCT
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//SSV PACK Definition
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#define SSV_PACKED_STRUCT_BEGIN
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#define SSV_PACKED_STRUCT //__attribute__ ((packed))
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#define SSV_PACKED_STRUCT_END //__attribute__((packed))
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#define SSV_PACKED_STRUCT_STRUCT __attribute__ ((packed))
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#define SSV_PACKED_STRUCT_FIELD(x) x
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#endif
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#define REG_FW_VERSION 0x08D00804
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/*******************************************************************************
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* Enumerations
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******************************************************************************/
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typedef enum _en_ipc_type
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{
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E_IPC_TYPE_MSG = 0,
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E_IPC_TYPE_ACK = 1,
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E_IPC_TYPE_DBG = 2,
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E_IPC_TYPE_DATA = 3,
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E_IPC_TYPE_TXCFM = 4,
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E_IPC_TYPE_AGG_REORD_MSG = 5,
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E_IPC_TYPE_DBG_DUMP_START = 6,
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E_IPC_TYPE_DBG_DUMP_END = 7,
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E_IPC_TYPE_DBG_LA_TRACE = 8,
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E_IPC_TYPE_DBG_RHD_DESC = 9,
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E_IPC_TYPE_DBG_RBD_DESC = 10,
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E_IPC_TYPE_DBG_TX_DESC = 11,
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E_IPC_TYPE_DUMP_INFO = 12,
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E_IPC_TYPE_TX_STOP = 13,
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E_IPC_TYPE_TX_RESUME = 14,
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E_IPC_TYPE_PRIV_MSG = 15,
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E_IPC_TYPE_MAX,
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} EN_IPC_TYPE;
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//if change must sync to lmac_msg.h of HOST size
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enum private_msg_tag
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{
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PRIV_SET_AMPDU,
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PRIV_TXTPUT_REQ,
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PRIV_TXTPUT_IND,
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PRIV_RXTPUT_REQ,
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PRIV_RXTPUT_CFM,
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PRIV_MAX,
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};
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typedef enum en_ipc_priv_msg_type
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{
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E_IPC_PRIV_MSG_TYPE_START = 0,
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E_IPC_PRIV_MSG_TYPE_SET_AMPDU, ///< 1, Set AMPDU
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E_IPC_PRIV_MSG_TYPE_TXTPUT_REQ, ///< 2, Txtput request
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E_IPC_PRIV_MSG_TYPE_TXTPUT_IND, ///< 3, Txtput indication
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E_IPC_PRIV_MSG_TYPE_RXTPUT_REQ, ///< 4, Rxtput request
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E_IPC_PRIV_MSG_TYPE_RXTPUT_IND, ///< 5, Rxtput indication
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E_IPC_PRIV_MSG_TYPE_SW_ACK_IND, ///< 6, sw ack ind
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E_IPC_PRIV_MSG_TYPE_FILTER_DUP_RX_REQ, ///< 7, filter duplicate rx
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E_IPC_PRIV_MSG_TYPE_NIMBLE_OPS, ///< 8, nimble ops
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E_IPC_PRIV_MSG_TYPE_NIMBLE_EVT, ///< 9, nimble event
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E_IPC_PRIV_MSG_TYPE_CMD_RFPHY_SET_TABLE = 10, ///< 10, RF set conf table
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E_IPC_PRIV_MSG_TYPE_CMD_RFPHY_OPS, ///< 11, RF Tool ops
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E_IPC_PRIV_MSG_TYPE_CMD_EFUSE_OPS, ///< 12, RF Tool ops
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E_IPC_PRIV_MSG_TYPE_RSP_EFUSE_IND,
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E_IPC_PRIV_MSG_TYPE_CMD_RFPHY_INIT_TABLE, /// 14, RF set conf table and init rfphy
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E_IPC_PRIV_MSG_TYPE_CMD_AGC_REG_TABLE, /// 15. Send agc setting
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E_IPC_PRIV_MSG_TYPE_CMD_RFPHY_REG_TABLE, /// 16. Send rf phy setting
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E_IPC_PRIV_MSG_TYPE_RSP_RF_IND, /// 17 Response to host
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E_IPC_PRIV_MSG_TYPE_MACADDR_REQ, /// 18. mac address
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E_IPC_PRIV_MSG_TYPE_CMD_REG_RW, /// 19. read/write register request from host
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E_IPC_PRIV_MSG_TYPE_RSP_REG_RW, /// 20. read/write register reponse to host
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E_IPC_PRIV_MSG_TYPE_WMM_FOLLOW_VO_REQ, /// 21. wmm follow by vo param
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E_IPC_PRIV_MSG_TYPE_IPC_TX_USE_ONE_HWQ = 22, /// 22. IPC TX uses one HWQ
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E_IPC_PRIV_MSG_TYPE_SET_POLICY_TBL_REQ, /// 23. set rts method
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E_IPC_PRIV_MSG_TYPE_CMD_RFCALIB_RESULT_BACKUP, /// 24. Notify Fw backup rf calibration result
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E_IPC_PRIV_MSG_TYPE_TXQ_CREDIT_BOUNDARY, /// 25. set txq credit boundary
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E_IPC_PRIV_MSG_TYPE_IO_AGGR, ///< 26, Set IO aggregation
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E_IPC_PRIV_MSG_TYPE_PING_IPC_REQ, /// 27, ping IPC layer request
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E_IPC_PRIV_MSG_TYPE_PING_IPC_IND, /// 28, ping IPC layer reply
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E_IPC_PRIV_MSG_TYPE_BLE_INIT, /// 29. ble init
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E_IPC_PRIV_MSG_TYPE_BLE_OPS, /// 30. ble packet
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E_IPC_PRIV_MSG_TYPE_BLE_EVT, /// 31. ble event
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E_IPC_PRIV_MSG_TYPE_SET_MIFI_FEATURE, ///32, Set MIFI Lowpower
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E_IPC_PRIV_MSG_TYPE_ADAPTIVE_OPS_ENABLE, ///33, adapt enable
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E_IPC_PRIV_MSG_TYPE_ADAPTIVE_OPS_DISABLE, ///34, adapt disable
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E_IPC_PRIV_MSG_TYPE_ADAPTIVE_OPS_SET, ///35, adapt set parameter
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E_IPC_PRIV_MSG_TYPE_MAC_ADDR_RULE, ///< 36, Set mac addr rule
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E_IPC_PRIV_MSG_TYPE_END = 0xFFFF,
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}EN_IPC_PRIV_MSG_TYPE;
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typedef enum {
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SSV6XXX_RFPHY_CMD_INIT_PLL_PHY_RF = 0,
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SSV6XXX_RFPHY_CMD_CHAN = 1,
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SSV6XXX_RFPHY_CMD_RF_ENABLE = 2,
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SSV6XXX_RFPHY_CMD_RF_DISABLE = 3,
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SSV6XXX_RFPHY_CMD_PHY_ENABLE = 4,
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SSV6XXX_RFPHY_CMD_PHY_DISABLE = 5,
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SSV6XXX_RFPHY_CMD_DUMP_PHY_REG = 6,
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SSV6XXX_RFPHY_CMD_DUMP_RF_REG = 7,
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SSV6XXX_RFPHY_CMD_TX_PWR = 8,
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SSV6XXX_RFPHY_CMD_INIT_CALI = 9,
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SSV6XXX_RFPHY_CMD_RESTORE_CALI = 10,
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SSV6XXX_RFPHY_CMD_DPD_ENABLE = 11,
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SSV6XXX_RFPHY_CMD_DPD_DISABLE = 12,
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SSV6XXX_RFPHY_CMD_RESTORE_DPD = 13,
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SSV6XXX_RFPHY_CMD_INIT_DPD = 14,
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SSV6XXX_RFPHY_CMD_INIT_PLL = 15,
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SSV6XXX_RFPHY_CMD_RF_TOOL_TX = 16, //tx
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SSV6XXX_RFPHY_CMD_RF_TOOL_STOP = 17, //stop
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SSV6XXX_RFPHY_CMD_RF_TOOL_RATE = 18,
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SSV6XXX_RFPHY_CMD_RF_TOOL_FREQ = 19,
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SSV6XXX_RFPHY_CMD_RF_TOOL_RX_MIB = 20,
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SSV6XXX_RFPHY_CMD_RF_TOOL_RX_RESET = 21, //rxreset
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SSV6XXX_RFPHY_CMD_RF_TOOL_CH = 22, //ch
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SSV6XXX_RFPHY_CMD_RF_TOOL_THERMAL = 23,
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SSV6XXX_RFPHY_CMD_RF_TOOL_DCDC = 24,
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SSV6XXX_RFPHY_CMD_RF_TOOL_DACGAIN = 25,
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SSV6XXX_RFPHY_CMD_RF_TOOL_PADPD = 26,
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SSV6XXX_RFPHY_CMD_RF_TOOL_WFBLE = 27,
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SSV6XXX_RFPHY_CMD_RF_TOOL_RATEBGAIN = 28,
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SSV6XXX_RFPHY_CMD_RF_TONE_GEN = 29,
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SSV6XXX_RFPHY_CMD_RF_TOOL_HETBRUIDX = 30,
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SSV6XXX_RFPHY_CMD_RF_TOOL_RATEPOWER = 31,
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SSV6XXX_RFPHY_CMD_RF_TOOL_ENGMODE = 32,
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SSV6XXX_RFPHY_CMD_RF_TOOL_TEMPERATURE = 33,
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SSV6XXX_RFPHY_CMD_SCAN_START = 50,
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SSV6XXX_RFPHY_CMD_SCAN_DONE,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_START,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_STOP,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_RATE,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_CH,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_RESET,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_COUNT,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_DACGAIN,
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SSV6XXX_RFPHY_CMD_RFBLE_TOOL_PATTERN,
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} ssv_rf_phy_ops;
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typedef enum {
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SSV6XXX_EFUSE_CMD_READ_CHIPID = 0,
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SSV6XXX_EFUSE_CMD_READ_MAC = 1,
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SSV6XXX_EFUSE_CMD_WRITE_MAC = 2,
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SSV6XXX_EFUSE_CMD_READ_TX_POWER1 = 3,
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SSV6XXX_EFUSE_CMD_WRITE_TX_POWER1 = 4,
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SSV6XXX_EFUSE_CMD_READ_XTAL = 5,
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SSV6XXX_EFUSE_CMD_WRITE_XTAL = 6,
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SSV6XXX_EFUSE_CMD_READ_RATE_GAIN_B_N40 = 7,
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SSV6XXX_EFUSE_CMD_WRITE_RATE_GAIN_B_N40 = 8,
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SSV6XXX_EFUSE_CMD_READ_PSK = 9,
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SSV6XXX_EFUSE_CMD_WRITE_PSK = 10,
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SSV6XXX_EFUSE_CMD_CHECK_ITEM_FREE = 11,
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SSV6XXX_EFUSE_CMD_READ_BLE_POWER = 12,
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SSV6XXX_EFUSE_CMD_WRITE_BLE_POWER = 13,
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SSV6XXX_EFUSE_CMD_READ_RATE_GAIN_G_N20 = 14,
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SSV6XXX_EFUSE_CMD_WRITE_RATE_GAIN_G_N20 = 15,
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SSV6XXX_EFUSE_CMD_READ_HETB_CAL_RATE_POWER = 16,
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SSV6XXX_EFUSE_CMD_WRITE_HETB_CAL_RATE_POWER = 17,
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SSV6XXX_EFUSE_CMD_READ_RATE_GAIN_SU20 = 18,
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SSV6XXX_EFUSE_CMD_WRITE_RATE_GAIN_SU20 = 19,
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SSV6XXX_EFUSE_CMD_READ_RATE_GAIN_SU40 = 20,
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SSV6XXX_EFUSE_CMD_WRITE_RATE_GAIN_SU40 = 21,
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SSV6XXX_EFUSE_CMD_READ_RATE_GAIN_TB20 = 22,
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SSV6XXX_EFUSE_CMD_WRITE_RATE_GAIN_TB20 = 23,
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SSV6XXX_EFUSE_CMD_READ_RATE_GAIN_TB40 = 24,
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SSV6XXX_EFUSE_CMD_WRITE_RATE_GAIN_TB40 = 25,
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SSV6XXX_EFUSE_CMD_READ_USB_PID_VID = 26,
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SSV6XXX_EFUSE_CMD_WRITE_USB_PID_VID = 27,
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} ssv_efuse_ops;
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/*******************************************************************************
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* Structures
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******************************************************************************/
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_set_ampdu_req
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{
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u32 priv_type;
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u32 length;
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u32 hw_cap;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_SET_AMPDU_REQ;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_priv_msg
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{
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u32 msgid;
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u32 msglen;
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u8 data[0];
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_PRIV_MSG;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_tput_param
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{
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u32 size;
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u32 looptimes;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_TPUT_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_filter_dup_rx_param
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{
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u32 filter_duplicate_rx;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_FILTER_DUP_RX_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_wmm_follow_vo_param
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{
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u32 wmm_follow_vo;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_WMM_FOLLOW_VO_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_mac_addr_param
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{
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u8 mac_addr0[6];
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u8 mac_addr1[6];
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_MAC_ADDR_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_reg_rw_param
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{
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u32 rw_method;
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u32 addr;
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u32 value;
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}__packed ST_IPC_REG_RW_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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struct ssv_efuse_tool_param {
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u32 efuse_cmd;
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u8 wait_resp;
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u8 resv1;
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u8 xtal;
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u8 psk_len;
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u8 psk[32];
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u32 chip_id;
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u8 mac[6];
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u8 txpower1_gain5200;
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u8 txpower1_gain2000;
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u8 rate_gain_b;
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u8 rate_gain_n40;
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u8 rate_gain_g;
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u8 rate_gain_n20;
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u8 hetb_cal_rate;
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u8 hetb_cal_power;
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u8 rate_gain_su20;
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u8 rate_gain_su40;
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u8 rate_gain_tb20;
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u8 rate_gain_tb40;
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u8 ble_gain;
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u8 check_item_free;
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u16 usb_pid;
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u16 usb_vid;
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u32 resv2;
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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struct ssv_rf_tool_param {
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u16 rf_cmd;
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u16 wait_resp;
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u32 interval;
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u32 count;
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u16 rate;
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u16 freq;
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u32 rx_reset:8;
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u32 rx_mib:8;
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u32 ch:8;
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u32 ch_type:8;
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u32 rx_count:16;
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u32 rx_err_count:16;
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u32 disable_thermal:1;
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u32 dcdc:1;
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u32 dacgain:8;
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u32 padpd:4;
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u32 wfble:1;
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u32 ratebgain:8;
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u32 tone_gen:1;
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u32 rssi:8;
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u32 hetbruid:16;
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u32 ratepower:16;
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u32 engmode:8;
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u32 temperature:8;
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u32 reserve1:8;
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u32 reserve2:8;
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT
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struct ssv_rfble_tool_param {
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u16 rfble_cmd;
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u16 wait_resp;
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u32 count;
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u8 packet_len;
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u8 rate;
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u8 chan;
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u8 interval;
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u16 rx_count;
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u16 rx_err_count;
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u32 dacgain:8;
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u32 pattern:8;
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u32 rsvd0:8;
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u32 rsvd1:8;
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT
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struct ssv_rf_cali {
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u32 xtal;
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u32 support_5g:4;
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u32 thermal:4;
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u32 greentx_en:1;
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u32 disable_cci:1;
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u32 resv1:6;
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u32 bus_clk:16;
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u32 thermal_low_thershold:16;
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u32 thermal_high_thershold:16;
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u32 resv0;
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struct st_rf_table rf_table;
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_set_policy_tbl_param
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{
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/*set_rts_method:
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3b000: No protection;
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3b001: Self-CTS;
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3b010: RTS/CTS with intended receiver of this PPDU;
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3b011: RTS/CTS with QAP;
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3b100: STBC protection;*/
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u8 set_rts_method;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_SET_POLICY_TBL_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_txq_credit_boundary_param
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{
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u32 boundary;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_TXQ_CREDIT_BOUNDARY_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_ipc_io_aggr_param
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{
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u32 is_rx;
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u32 enable;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_IO_AGGR_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct st_mac_addr_rule_param
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{
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u32 mac_low_mask;
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u32 mac_high_mask;
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}SSV_PACKED_STRUCT_STRUCT ST_MAC_ADDR_RULE_PARAM;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT_BEGIN
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typedef struct ST_IPC_SET_MIFI
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{
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u32 status;
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u32 no_traffic_duration;
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}SSV_PACKED_STRUCT_STRUCT ST_IPC_SET_MIFI;
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SSV_PACKED_STRUCT_END
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// hci bus defines
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#define SSV_BLE_HCI_OVER_UART 0
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#define SSV_BLE_HCI_OVER_HWIF 1 // USB or SDIO
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SSV_PACKED_STRUCT
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struct ssv_ble_cfg {
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u8 bus:1;
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u8 hci_reset:1;
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u8 dtm:1;
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u8 rsvd:5;
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u8 bdaddr[6];
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u16 replace_scan_interval;
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u16 replace_scan_win;
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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//ipc memory 使用的policy
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//驅動ipc msg tx rx 尚未ready前, 可以使用ipc memory和FW交換訊息
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//當ipc msg tx rx ready後, 建議使用ke msg和FW交換訊息
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#define SSV_IPC_MEM_SIZE 512
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#define SSV_CALI_RESULT_SIZE 43
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SSV_PACKED_STRUCT
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struct st_ipc_mem_layout {
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u32 pattern;
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u32 rf_cali_result[SSV_CALI_RESULT_SIZE];
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u32 rf_cali_mcs9_result[SSV_CALI_RESULT_SIZE];
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u8 reserve[164];
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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SSV_PACKED_STRUCT
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struct st_ipc_adaptive_param {
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u32 interval;
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u32 hit_count;
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u32 total_count;
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u32 threshold;
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}SSV_PACKED_STRUCT_STRUCT;
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SSV_PACKED_STRUCT_END
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Funcations
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******************************************************************************/
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#endif /* __IPC_MSG_H__ */
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