8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
254 lines
7.1 KiB
C
254 lines
7.1 KiB
C
/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SOC_ROCKCHIP_OPP_SELECT_H
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#define __SOC_ROCKCHIP_OPP_SELECT_H
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#define VOLT_RM_TABLE_END ~1
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/*
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* [0]: set intermediate rate
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* [1]: scaling up rate or scaling down rate
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* [1]: add length for pvtpll
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* [2:5]: length
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* [2]: use low length for pvtpll
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* [3:5]: reserved
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*/
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#define OPP_RATE_MASK 0x3f
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/* Set intermediate rate */
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#define OPP_INTERMEDIATE_RATE BIT(0)
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#define OPP_SCALING_UP_RATE BIT(1)
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#define OPP_SCALING_UP_INTER (OPP_INTERMEDIATE_RATE | OPP_SCALING_UP_RATE)
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#define OPP_SCALING_DOWN_INTER OPP_INTERMEDIATE_RATE
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/* Add length for pvtpll */
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#define OPP_ADD_LENGTH BIT(1)
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#define OPP_LENGTH_MASK 0xf
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#define OPP_LENGTH_SHIFT 2
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/* Use low length for pvtpll */
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#define OPP_LENGTH_LOW BIT(2)
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struct rockchip_opp_info;
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struct volt_rm_table {
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int volt;
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int rm;
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};
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struct rockchip_opp_data {
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int (*get_soc_info)(struct device *dev, struct device_node *np,
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int *bin, int *process);
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int (*set_soc_info)(struct device *dev, struct device_node *np,
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int bin, int process, int volt_sel);
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int (*set_read_margin)(struct device *dev,
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struct rockchip_opp_info *opp_info,
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u32 rm);
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};
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struct pvtpll_opp_table {
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unsigned long rate;
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unsigned long u_volt;
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unsigned long u_volt_min;
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unsigned long u_volt_max;
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unsigned long u_volt_mem;
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unsigned long u_volt_mem_min;
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unsigned long u_volt_mem_max;
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};
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struct rockchip_opp_info {
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struct device *dev;
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struct pvtpll_opp_table *opp_table;
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const struct rockchip_opp_data *data;
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struct volt_rm_table *volt_rm_tbl;
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struct regmap *grf;
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struct regmap *dsu_grf;
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struct clk_bulk_data *clks;
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struct clk *scmi_clk;
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/* The threshold frequency for set intermediate rate */
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unsigned long intermediate_threshold_freq;
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unsigned int pvtpll_avg_offset;
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unsigned int pvtpll_min_rate;
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unsigned int pvtpll_volt_step;
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int num_clks;
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/* The read margin for low voltage */
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u32 low_rm;
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u32 current_rm;
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u32 target_rm;
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};
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#if IS_ENABLED(CONFIG_ROCKCHIP_OPP)
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int rockchip_of_get_leakage(struct device *dev, char *lkg_name, int *leakage);
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void rockchip_of_get_lkg_sel(struct device *dev, struct device_node *np,
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char *lkg_name, int process,
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int *volt_sel, int *scale_sel);
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void rockchip_pvtpll_calibrate_opp(struct rockchip_opp_info *info);
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void rockchip_pvtpll_add_length(struct rockchip_opp_info *info);
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void rockchip_of_get_pvtm_sel(struct device *dev, struct device_node *np,
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char *reg_name, int process,
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int *volt_sel, int *scale_sel);
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void rockchip_of_get_bin_sel(struct device *dev, struct device_node *np,
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int bin, int *scale_sel);
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void rockchip_of_get_bin_volt_sel(struct device *dev, struct device_node *np,
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int bin, int *bin_volt_sel);
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int rockchip_nvmem_cell_read_u8(struct device_node *np, const char *cell_id,
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u8 *val);
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int rockchip_nvmem_cell_read_u16(struct device_node *np, const char *cell_id,
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u16 *val);
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int rockchip_get_volt_rm_table(struct device *dev, struct device_node *np,
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char *porp_name, struct volt_rm_table **table);
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void rockchip_get_opp_data(const struct of_device_id *matches,
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struct rockchip_opp_info *info);
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void rockchip_get_scale_volt_sel(struct device *dev, char *lkg_name,
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char *reg_name, int bin, int process,
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int *scale, int *volt_sel);
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struct opp_table *rockchip_set_opp_prop_name(struct device *dev, int process,
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int volt_sel);
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int rockchip_adjust_power_scale(struct device *dev, int scale);
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int rockchip_get_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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unsigned long volt, u32 *target_rm);
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int rockchip_set_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info, u32 rm,
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bool is_set_rm);
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int rockchip_init_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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char *reg_name);
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int rockchip_set_intermediate_rate(struct device *dev,
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struct rockchip_opp_info *opp_info,
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struct clk *clk, unsigned long old_freq,
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unsigned long new_freq, bool is_scaling_up,
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bool is_set_clk);
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int rockchip_init_opp_table(struct device *dev,
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struct rockchip_opp_info *info,
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char *lkg_name, char *reg_name);
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#else
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static inline int rockchip_of_get_leakage(struct device *dev, char *lkg_name,
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int *leakage)
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{
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return -EOPNOTSUPP;
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}
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static inline void rockchip_of_get_lkg_sel(struct device *dev,
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struct device_node *np,
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char *lkg_name, int process,
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int *volt_sel, int *scale_sel)
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{
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}
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static inline void rockchip_pvtpll_calibrate_opp(struct rockchip_opp_info *info)
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{
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}
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static inline void rockchip_pvtpll_add_length(struct rockchip_opp_info *info)
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{
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}
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static inline void rockchip_of_get_pvtm_sel(struct device *dev,
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struct device_node *np,
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char *reg_name, int process,
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int *volt_sel, int *scale_sel)
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{
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}
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static inline void rockchip_of_get_bin_sel(struct device *dev,
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struct device_node *np, int bin,
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int *scale_sel)
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{
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}
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static inline void rockchip_of_get_bin_volt_sel(struct device *dev,
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struct device_node *np,
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int bin, int *bin_volt_sel)
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{
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}
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static inline int rockchip_nvmem_cell_read_u8(struct device_node *np,
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const char *cell_id, u8 *val)
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{
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return -EOPNOTSUPP;
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}
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static inline int rockchip_nvmem_cell_read_u16(struct device_node *np,
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const char *cell_id, u16 *val)
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{
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return -EOPNOTSUPP;
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}
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static inline int rockchip_get_volt_rm_table(struct device *dev,
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struct device_node *np,
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char *porp_name,
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struct volt_rm_table **table)
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{
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return -EOPNOTSUPP;
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}
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static inline void rockchip_get_opp_data(const struct of_device_id *matches,
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struct rockchip_opp_info *info)
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{
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}
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static inline void rockchip_get_scale_volt_sel(struct device *dev,
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char *lkg_name, char *reg_name,
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int bin, int process, int *scale,
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int *volt_sel)
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{
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}
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static inline struct opp_table *rockchip_set_opp_prop_name(struct device *dev,
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int process,
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int volt_sel)
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{
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return ERR_PTR(-EOPNOTSUPP);
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}
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static inline int rockchip_adjust_power_scale(struct device *dev, int scale)
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{
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return -EOPNOTSUPP;
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}
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static inline int rockchip_get_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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unsigned long volt, u32 *target_rm)
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{
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return -EOPNOTSUPP;
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}
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static inline int rockchip_set_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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u32 rm, bool is_set_rm)
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{
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return -EOPNOTSUPP;
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}
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static inline int rockchip_init_read_margin(struct device *dev,
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struct rockchip_opp_info *opp_info,
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char *reg_name)
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{
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return -EOPNOTSUPP;
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}
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static inline int
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rockchip_set_intermediate_rate(struct device *dev,
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struct rockchip_opp_info *opp_info,
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struct clk *clk, unsigned long old_freq,
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unsigned long new_freq, bool is_scaling_up,
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bool is_set_clk)
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{
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return -EOPNOTSUPP;
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}
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static inline int rockchip_init_opp_table(struct device *dev,
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struct rockchip_opp_info *info,
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char *lkg_name, char *reg_name)
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{
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return -EOPNOTSUPP;
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}
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#endif /* CONFIG_ROCKCHIP_OPP */
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#endif
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