luckfox-pico-sdk/sysdrv/source/kernel/arch/arm/mach-rockchip/rkpm_gicv2.h
luckfox-eng29 8f34c2760d project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between
the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door
for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more
usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp:
Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for
compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem.
sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device
tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately.
sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick
boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades.
sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for
fastboot.

Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
2024-10-14 09:47:04 +08:00

40 lines
1.1 KiB
C

/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#ifndef RKPM_GICV2_H
#define RKPM_GICV2_H
struct plat_gicv2_dist_ctx_t {
u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
u32 saved_spi_prio[DIV_ROUND_UP(1020, 4)];
u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
u32 saved_spi_grp[DIV_ROUND_UP(1020, 32)];
u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
u32 saved_gicd_ctrl;
};
struct plat_gicv2_cpu_ctx_t {
u32 saved_ppi_enable;
u32 saved_ppi_active;
u32 saved_ppi_conf[DIV_ROUND_UP(32, 16)];
u32 saved_ppi_prio[DIV_ROUND_UP(32, 4)];
u32 saved_ppi_grp;
u32 saved_gicc_ctrl;
u32 saved_gicc_pmr;
};
void rkpm_gicv2_dist_save(void __iomem *dist_base,
struct plat_gicv2_dist_ctx_t *ctx);
void rkpm_gicv2_dist_restore(void __iomem *dist_base,
struct plat_gicv2_dist_ctx_t *ctx);
void rkpm_gicv2_cpu_save(void __iomem *dist_base,
void __iomem *cpu_base,
struct plat_gicv2_cpu_ctx_t *ctx);
void rkpm_gicv2_cpu_restore(void __iomem *dist_base,
void __iomem *cpu_base,
struct plat_gicv2_cpu_ctx_t *ctx);
#endif