8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include "rkpm_helpers.h"
|
|
#include "rkpm_uart.h"
|
|
|
|
#define UART_DEFAULT_BAUDRATE 115200
|
|
|
|
void rkpm_uart_debug_init(void __iomem *base,
|
|
unsigned int uart_clk,
|
|
unsigned int baud_rate)
|
|
{
|
|
u32 uart_dll, uart_dlh;
|
|
u32 div;
|
|
|
|
if (!base || !uart_clk || !baud_rate)
|
|
return;
|
|
|
|
div = uart_clk / baud_rate / 16;
|
|
uart_dll = div & 0xff;
|
|
uart_dlh = (div >> 8) & 0xff;
|
|
|
|
/* Reset uart */
|
|
writel_relaxed(XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET,
|
|
base + UARTSRR);
|
|
rkpm_raw_udelay(10);
|
|
|
|
writel_relaxed(UART_MCR_LOOP, base + UARTMCR);
|
|
writel_relaxed(0x83, base + UARTLCR);
|
|
writel_relaxed(uart_dll, base + UARTDLL);
|
|
writel_relaxed(uart_dlh, base + UARTDLLM);
|
|
writel_relaxed(0x03, base + UARTLCR);
|
|
writel_relaxed(0x01, base + UARTIER);
|
|
writel_relaxed(UARTFCR_FIFOEN, base + UARTFCR);
|
|
writel_relaxed(0, base + UARTMCR);
|
|
}
|
|
|
|
void rkpm_uart_debug_save(void __iomem *base,
|
|
struct uart_debug_ctx *ctx)
|
|
{
|
|
u32 wait_cnt = 50000;
|
|
u32 uart_mcr;
|
|
|
|
/* Saved the uart registers before and don't need to save again */
|
|
if (ctx->uart_dll || ctx->uart_dlh)
|
|
return;
|
|
|
|
uart_mcr = readl_relaxed(base + UARTMCR);
|
|
writel_relaxed(uart_mcr | UART_MCR_LOOP, base + UARTMCR);
|
|
|
|
while ((readl_relaxed(base + UARTUSR) & UARTUSR_BUSY) &&
|
|
--wait_cnt)
|
|
rkpm_raw_udelay(10);
|
|
|
|
writel_relaxed(uart_mcr, base + UARTMCR);
|
|
|
|
/* Uart error! Unlikely to reach here */
|
|
if (wait_cnt == 0) {
|
|
rkpm_printstr("uart always busy, recover to default baudrate:");
|
|
rkpm_printdec(UART_DEFAULT_BAUDRATE);
|
|
rkpm_printstr("!!!\n");
|
|
rkpm_uart_debug_init(base, 24000000, UART_DEFAULT_BAUDRATE);
|
|
}
|
|
|
|
ctx->uart_lcr = readl_relaxed(base + UARTLCR);
|
|
ctx->uart_ier = readl_relaxed(base + UARTIER);
|
|
ctx->uart_mcr = readl_relaxed(base + UARTMCR);
|
|
writel_relaxed(ctx->uart_lcr | UARTLCR_DLAB, base + UARTLCR);
|
|
ctx->uart_dll = readl_relaxed(base + UARTDLL);
|
|
ctx->uart_dlh = readl_relaxed(base + UARTDLLM);
|
|
writel_relaxed(ctx->uart_lcr, base + UARTLCR);
|
|
}
|
|
|
|
void rkpm_uart_debug_restore(void __iomem *base,
|
|
struct uart_debug_ctx *ctx)
|
|
{
|
|
u32 uart_lcr, uart_mcr;
|
|
u32 wait_cnt = 560;
|
|
|
|
uart_mcr = readl_relaxed(base + UARTMCR);
|
|
writel_relaxed(uart_mcr | UART_MCR_LOOP, base + UARTMCR);
|
|
|
|
while ((readl_relaxed(base + UARTUSR) & UARTUSR_BUSY) &&
|
|
--wait_cnt)
|
|
rkpm_raw_udelay(10);
|
|
|
|
writel_relaxed(uart_mcr, base + UARTMCR);
|
|
|
|
writel_relaxed(XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET,
|
|
base + UARTSRR);
|
|
rkpm_raw_udelay(10);
|
|
uart_lcr = readl_relaxed(base + UARTLCR);
|
|
writel_relaxed(UART_MCR_LOOP, base + UARTMCR);
|
|
writel_relaxed(uart_lcr | UARTLCR_DLAB, base + UARTLCR);
|
|
writel_relaxed(ctx->uart_dll, base + UARTDLL);
|
|
writel_relaxed(ctx->uart_dlh, base + UARTDLLM);
|
|
writel_relaxed(ctx->uart_lcr, base + UARTLCR);
|
|
writel_relaxed(ctx->uart_ier, base + UARTIER);
|
|
writel_relaxed(UARTFCR_FIFOEN, base + UARTFCR);
|
|
writel_relaxed(ctx->uart_mcr, base + UARTMCR);
|
|
}
|
|
|