8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
174 lines
3.5 KiB
C
174 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* rt1308-sdw.h -- RT1308 ALSA SoC audio driver header
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*
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* Copyright(c) 2019 Realtek Semiconductor Corp.
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*/
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#ifndef __RT1308_SDW_H__
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#define __RT1308_SDW_H__
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static const struct reg_default rt1308_reg_defaults[] = {
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{ 0x0000, 0x00 },
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{ 0x0001, 0x00 },
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{ 0x0002, 0x00 },
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{ 0x0003, 0x00 },
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{ 0x0004, 0x00 },
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{ 0x0005, 0x01 },
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{ 0x0020, 0x00 },
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{ 0x0022, 0x00 },
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{ 0x0023, 0x00 },
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{ 0x0024, 0x00 },
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{ 0x0025, 0x00 },
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{ 0x0026, 0x00 },
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{ 0x0030, 0x00 },
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{ 0x0032, 0x00 },
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{ 0x0033, 0x00 },
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{ 0x0034, 0x00 },
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{ 0x0035, 0x00 },
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{ 0x0036, 0x00 },
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{ 0x0040, 0x00 },
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{ 0x0041, 0x00 },
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{ 0x0042, 0x00 },
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{ 0x0043, 0x00 },
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{ 0x0044, 0x20 },
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{ 0x0045, 0x01 },
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{ 0x0046, 0x01 },
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{ 0x0048, 0x00 },
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{ 0x0049, 0x00 },
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{ 0x0050, 0x20 },
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{ 0x0051, 0x02 },
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{ 0x0052, 0x5D },
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{ 0x0053, 0x13 },
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{ 0x0054, 0x08 },
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{ 0x0055, 0x00 },
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{ 0x0060, 0x00 },
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{ 0x0070, 0x00 },
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{ 0x00E0, 0x00 },
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{ 0x00F0, 0x00 },
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{ 0x0100, 0x00 },
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{ 0x0101, 0x00 },
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{ 0x0102, 0x20 },
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{ 0x0103, 0x00 },
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{ 0x0104, 0x00 },
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{ 0x0105, 0x03 },
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{ 0x0120, 0x00 },
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{ 0x0122, 0x00 },
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{ 0x0123, 0x00 },
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{ 0x0124, 0x00 },
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{ 0x0125, 0x00 },
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{ 0x0126, 0x00 },
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{ 0x0127, 0x00 },
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{ 0x0130, 0x00 },
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{ 0x0132, 0x00 },
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{ 0x0133, 0x00 },
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{ 0x0134, 0x00 },
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{ 0x0135, 0x00 },
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{ 0x0136, 0x00 },
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{ 0x0137, 0x00 },
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{ 0x0200, 0x00 },
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{ 0x0201, 0x00 },
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{ 0x0202, 0x00 },
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{ 0x0203, 0x00 },
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{ 0x0204, 0x00 },
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{ 0x0205, 0x03 },
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{ 0x0220, 0x00 },
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{ 0x0222, 0x00 },
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{ 0x0223, 0x00 },
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{ 0x0224, 0x00 },
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{ 0x0225, 0x00 },
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{ 0x0226, 0x00 },
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{ 0x0227, 0x00 },
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{ 0x0230, 0x00 },
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{ 0x0232, 0x00 },
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{ 0x0233, 0x00 },
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{ 0x0234, 0x00 },
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{ 0x0235, 0x00 },
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{ 0x0236, 0x00 },
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{ 0x0237, 0x00 },
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{ 0x0400, 0x00 },
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{ 0x0401, 0x00 },
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{ 0x0402, 0x00 },
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{ 0x0403, 0x00 },
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{ 0x0404, 0x00 },
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{ 0x0405, 0x03 },
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{ 0x0420, 0x00 },
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{ 0x0422, 0x00 },
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{ 0x0423, 0x00 },
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{ 0x0424, 0x00 },
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{ 0x0425, 0x00 },
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{ 0x0426, 0x00 },
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{ 0x0427, 0x00 },
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{ 0x0430, 0x00 },
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{ 0x0432, 0x00 },
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{ 0x0433, 0x00 },
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{ 0x0434, 0x00 },
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{ 0x0435, 0x00 },
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{ 0x0436, 0x00 },
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{ 0x0437, 0x00 },
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{ 0x0f00, 0x00 },
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{ 0x0f01, 0x00 },
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{ 0x0f02, 0x00 },
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{ 0x0f03, 0x00 },
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{ 0x0f04, 0x00 },
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{ 0x0f05, 0x00 },
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{ 0x0f20, 0x00 },
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{ 0x0f22, 0x00 },
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{ 0x0f23, 0x00 },
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{ 0x0f24, 0x00 },
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{ 0x0f25, 0x00 },
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{ 0x0f26, 0x00 },
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{ 0x0f27, 0x00 },
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{ 0x0f30, 0x00 },
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{ 0x0f32, 0x00 },
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{ 0x0f33, 0x00 },
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{ 0x0f34, 0x00 },
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{ 0x0f35, 0x00 },
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{ 0x0f36, 0x00 },
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{ 0x0f37, 0x00 },
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{ 0x2f01, 0x01 },
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{ 0x2f02, 0x09 },
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{ 0x2f03, 0x00 },
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{ 0x2f04, 0x0f },
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{ 0x2f05, 0x0b },
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{ 0x2f06, 0x01 },
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{ 0x2f07, 0x8e },
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{ 0x3000, 0x00 },
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{ 0x3001, 0x00 },
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{ 0x3004, 0x01 },
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{ 0x3005, 0x23 },
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{ 0x3008, 0x02 },
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{ 0x300a, 0x00 },
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{ 0xc000 | (RT1308_DATA_PATH << 4), 0x00 },
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{ 0xc003 | (RT1308_DAC_SET << 4), 0x00 },
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{ 0xc001 | (RT1308_POWER << 4), 0x00 },
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{ 0xc002 | (RT1308_POWER << 4), 0x00 },
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{ 0xc000 | (RT1308_POWER_STATUS << 4), 0x00 },
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};
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#define RT1308_SDW_OFFSET 0xc000
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#define RT1308_SDW_OFFSET_BYTE0 0xc000
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#define RT1308_SDW_OFFSET_BYTE1 0xc001
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#define RT1308_SDW_OFFSET_BYTE2 0xc002
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#define RT1308_SDW_OFFSET_BYTE3 0xc003
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#define RT1308_SDW_RESET (RT1308_SDW_OFFSET | (RT1308_RESET << 4))
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struct rt1308_sdw_priv {
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struct snd_soc_component *component;
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struct regmap *regmap;
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struct sdw_slave *sdw_slave;
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enum sdw_slave_status status;
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struct sdw_bus_params params;
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bool hw_init;
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bool first_hw_init;
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int rx_mask;
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int slots;
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};
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struct sdw_stream_data {
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struct sdw_stream_runtime *sdw_stream;
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};
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#endif /* __RT1308_SDW_H__ */
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