8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
294 lines
8.3 KiB
C
294 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2024 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask;
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u8 bit;
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u32 data;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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regmap = priv->regmap_base;
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reg = bank->iomux[iomux_num].offset;
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
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reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
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debug("iomux write reg = %x data = %x\n", reg, data);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3576_DRV_BITS_PER_PIN 4
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#define RK3576_DRV_PINS_PER_REG 4
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#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
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#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
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#define RK3576_DRV_GPIO1_OFFSET 0x6020
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#define RK3576_DRV_GPIO2_OFFSET 0x6040
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#define RK3576_DRV_GPIO3_OFFSET 0x6060
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#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
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#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
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#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
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static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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if (bank->bank_num == 0 && pin_num < 12)
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*reg = RK3576_DRV_GPIO0_AL_OFFSET;
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else if (bank->bank_num == 0)
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*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
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else if (bank->bank_num == 1)
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*reg = RK3576_DRV_GPIO1_OFFSET;
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else if (bank->bank_num == 2)
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*reg = RK3576_DRV_GPIO2_OFFSET;
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else if (bank->bank_num == 3)
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*reg = RK3576_DRV_GPIO3_OFFSET;
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else if (bank->bank_num == 4 && pin_num < 16)
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*reg = RK3576_DRV_GPIO4_AL_OFFSET;
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else if (bank->bank_num == 4 && pin_num < 24)
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*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
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else if (bank->bank_num == 4)
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*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
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else {
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*reg = 0;
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dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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}
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*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RK3576_DRV_PINS_PER_REG;
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*bit *= RK3576_DRV_BITS_PER_PIN;
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}
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static int rk3576_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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int drv = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
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rk3576_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3576_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (drv << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3576_PULL_BITS_PER_PIN 2
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#define RK3576_PULL_PINS_PER_REG 8
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#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
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#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
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#define RK3576_PULL_GPIO1_OFFSET 0x6110
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#define RK3576_PULL_GPIO2_OFFSET 0x6120
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#define RK3576_PULL_GPIO3_OFFSET 0x6130
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#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
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#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
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#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
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static void rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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if (bank->bank_num == 0 && pin_num < 12)
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*reg = RK3576_PULL_GPIO0_AL_OFFSET;
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else if (bank->bank_num == 0)
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*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
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else if (bank->bank_num == 1)
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*reg = RK3576_PULL_GPIO1_OFFSET;
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else if (bank->bank_num == 2)
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*reg = RK3576_PULL_GPIO2_OFFSET;
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else if (bank->bank_num == 3)
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*reg = RK3576_PULL_GPIO3_OFFSET;
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else if (bank->bank_num == 4 && pin_num < 16)
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*reg = RK3576_PULL_GPIO4_AL_OFFSET;
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else if (bank->bank_num == 4 && pin_num < 24)
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*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
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else if (bank->bank_num == 4)
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*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
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else {
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*reg = 0;
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dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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}
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*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RK3576_PULL_PINS_PER_REG;
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*bit *= RK3576_PULL_BITS_PER_PIN;
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}
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static int rk3576_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk3576_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3576_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3576_SMT_BITS_PER_PIN 1
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#define RK3576_SMT_PINS_PER_REG 8
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#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
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#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
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#define RK3576_SMT_GPIO1_OFFSET 0x6210
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#define RK3576_SMT_GPIO2_OFFSET 0x6220
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#define RK3576_SMT_GPIO3_OFFSET 0x6230
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#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
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#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
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#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
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static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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if (bank->bank_num == 0 && pin_num < 12)
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*reg = RK3576_SMT_GPIO0_AL_OFFSET;
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else if (bank->bank_num == 0)
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*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
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else if (bank->bank_num == 1)
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*reg = RK3576_SMT_GPIO1_OFFSET;
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else if (bank->bank_num == 2)
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*reg = RK3576_SMT_GPIO2_OFFSET;
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else if (bank->bank_num == 3)
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*reg = RK3576_SMT_GPIO3_OFFSET;
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else if (bank->bank_num == 4 && pin_num < 16)
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*reg = RK3576_SMT_GPIO4_AL_OFFSET;
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else if (bank->bank_num == 4 && pin_num < 24)
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*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
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else if (bank->bank_num == 4)
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*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
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else {
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*reg = 0;
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dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
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}
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*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3576_SMT_PINS_PER_REG;
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*bit *= RK3576_SMT_BITS_PER_PIN;
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return 0;
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}
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static int rk3576_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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rk3576_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = ((1 << RK3576_SMT_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (enable << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
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PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
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IOMUX_WIDTH_4BIT, \
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IOMUX_WIDTH_4BIT, \
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IOMUX_WIDTH_4BIT, \
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IOMUX_WIDTH_4BIT, \
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OFFSET0, OFFSET1, \
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OFFSET2, OFFSET3, \
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PULL_TYPE_IO_1, PULL_TYPE_IO_1, \
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PULL_TYPE_IO_1, PULL_TYPE_IO_1)
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static struct rockchip_pin_bank rk3576_pin_banks[] = {
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RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
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RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
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RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
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RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
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RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
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};
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static const struct rockchip_pin_ctrl rk3576_pin_ctrl = {
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.pin_banks = rk3576_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3576_pin_banks),
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.nr_pins = 160,
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.grf_mux_offset = 0x0,
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.set_mux = rk3576_set_mux,
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.set_pull = rk3576_set_pull,
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.set_drive = rk3576_set_drive,
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.set_schmitt = rk3576_set_schmitt,
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};
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static const struct udevice_id rk3576_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3576-pinctrl",
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.data = (ulong)&rk3576_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3576) = {
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.name = "rockchip_rk3576_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3576_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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