8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
92 lines
2.0 KiB
YAML
92 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Quad Serial Peripheral Interface (QSPI)
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maintainers:
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- Mukesh Savaliya <msavaliy@codeaurora.org>
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- Akash Asthana <akashast@codeaurora.org>
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description: The QSPI controller allows SPI protocol communication in single,
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dual, or quad wire transmission modes for read/write access to slaves such
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as NOR flash.
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allOf:
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- $ref: /spi/spi-controller.yaml#
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properties:
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compatible:
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items:
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- const: qcom,sdm845-qspi
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- const: qcom,qspi-v1
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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items:
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- const: iface
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- const: core
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clocks:
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items:
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- description: AHB clock
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- description: QSPI core clock
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interconnects:
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minItems: 1
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maxItems: 2
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interconnect-names:
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minItems: 1
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items:
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- const: qspi-config
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- const: qspi-memory
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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qspi: spi@88df000 {
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compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
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reg = <0 0x88df000 0 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "iface", "core";
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clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
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<&gcc GCC_QSPI_CORE_CLK>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <25000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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};
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...
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