8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
102 lines
1.7 KiB
Plaintext
102 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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/ {
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};
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&cru {
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assigned-clocks =
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<&cru PLL_GPLL>, <&cru PLL_CPLL>,
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<&cru ARMCLK>,
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<&cru CLK_50M_SRC>, <&cru CLK_100M_SRC>,
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<&cru CLK_150M_SRC>, <&cru CLK_200M_SRC>,
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<&cru CLK_250M_SRC>, <&cru CLK_300M_SRC>,
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<&cru CLK_339M_SRC>, <&cru CLK_400M_SRC>,
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<&cru CLK_450M_SRC>, <&cru CLK_500M_SRC>,
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<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
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<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
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<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
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<&cru HCLK_PMU_ROOT>;
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assigned-clock-rates =
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<983040000>, <1188000000>,
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<1104000000>,
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<50000000>, <100000000>,
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<150000000>, <200000000>,
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<250000000>, <300000000>,
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<340000000>, <400000000>,
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<450000000>, <500000000>,
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<400000000>, <200000000>,
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<100000000>, <300000000>,
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<100000000>, <100000000>,
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<200000000>;
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};
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&fiq_debugger {
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rockchip,irq-mode-enable = <1>;
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status = "okay";
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};
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&i2s0_8ch {
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status = "okay";
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clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>,
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<&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>,
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<&cru PLL_GPLL>, <&cru PLL_GPLL>;
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clock-names = "mclk_tx", "mclk_rx", "hclk",
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"mclk_tx_src", "mclk_rx_src",
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"mclk_root0", "mclk_root1";
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rockchip,mclk-calibrate;
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};
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&mpp_srv {
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status = "okay";
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};
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&mpp_vcodec {
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status = "okay";
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};
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&npu {
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status = "okay";
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};
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&rga2 {
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status = "okay";
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};
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&rkvenc {
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status = "okay";
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};
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&rkvenc_pp {
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&rve {
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status = "okay";
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};
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&u2phy {
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status = "okay";
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};
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&u2phy_otg {
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rockchip,dis-u2-susphy;
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status = "okay";
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};
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&usbdrd {
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status = "okay";
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};
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&usbdrd_dwc3 {
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dr_mode = "peripheral";
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status = "okay";
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};
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