project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
247 lines
4.1 KiB
Plaintext
247 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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* Version Sensor I2C_ADDR Lanes
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* v1.0.0 os04a10 0x36 lane0~1(dphy1)
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* sc4336 0x30 lane2~3(dphy2)
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* v1.1.0 gc2053 0x37 lane0~1(dphy1)
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* gc2053 0x3f lane2~3(dphy2)
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*/
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&csi2_dphy_hw {
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status = "okay";
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};
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&csi2_dphy1 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_input0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ahd_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_csi2_input>;
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};
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};
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};
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};
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&csi2_dphy2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_input1: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&sc3336_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csi_dphy_output1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi1_csi2_input>;
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};
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};
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};
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};
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&i2c4 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4m2_xfer>;
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tp9951_00: tp9951@45 {
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compatible = "techpoint,tp9951";
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status = "okay";
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reg = <0x45>;
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clocks = <&cru MCLK_REF_MIPI0>;
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clock-names = "xvclk";
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reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
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power-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_refclk_out0>;
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rockchip,camera-module-index = <1>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "tp9951";
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rockchip,camera-module-lens-name = "tp9951";
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port {
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ahd_out: endpoint {
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remote-endpoint = <&csi_dphy_input0>;
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data-lanes = <1 2>;
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};
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};
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};
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sc3336: sc3336@30 {
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compatible = "smartsens,sc3336";
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status = "okay";
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reg = <0x30>;
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clocks = <&cru MCLK_REF_MIPI1>;
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clock-names = "xvclk";
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reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
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// pwdn-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_refclk_out1>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "front";
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rockchip,camera-module-name = "OT01";
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rockchip,camera-module-lens-name = "40IRC_F16";
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port {
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sc3336_out: endpoint {
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remote-endpoint = <&csi_dphy_input1>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&mipi0_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csi_dphy_output>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in>;
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};
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};
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};
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};
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&mipi1_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csi_dphy_output1>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in1>;
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};
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};
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};
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};
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&rkcif {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mipi_pins>;
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};
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&rkcif_mipi_lvds {
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status = "okay";
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port {
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/* MIPI CSI-2 endpoint */
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cif_mipi_in: endpoint {
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remote-endpoint = <&mipi_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds1 {
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status = "okay";
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port {
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/* MIPI CSI-2 endpoint */
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cif_mipi_in1: endpoint {
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remote-endpoint = <&mipi1_csi2_output>;
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};
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};
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};
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&rkcif_mipi_lvds1_sditf {
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status = "okay";
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port {
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/* MIPI CSI-2 endpoint */
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mipi_lvds1_sditf: endpoint {
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remote-endpoint = <&isp_in1>;
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};
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};
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};
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&rkisp {
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status = "okay";
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};
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&rkisp_vir0 {
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status = "okay";
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port@0 {
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isp_in1: endpoint {
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remote-endpoint = <&mipi_lvds1_sditf>;
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};
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};
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};
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