8f34c2760d
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp: Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem. sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately. sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades. sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for fastboot. Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
77 lines
2.9 KiB
C
77 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static void gd25q256_default_init(struct spi_nor *nor)
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{
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/*
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* Some manufacturer like GigaDevice may use different
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* bit to set QE on different memories, so the MFR can't
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* indicate the quad_enable method for this case, we need
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* to set it in the default_init fixup hook.
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*/
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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}
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static struct spi_nor_fixups gd25q256_fixups = {
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.default_init = gd25q256_default_init,
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};
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static const struct flash_info gigadevice_parts[] = {
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{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_TB) },
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{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
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{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
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SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
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.fixups = &gd25q256_fixups },
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{ "gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
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SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
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.fixups = &gd25q256_fixups },
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{ "gd25lq255", INFO(0xc86019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
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{ "gd25lb512m", INFO(0xc8671a, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
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{ "gd25b512m", INFO(0xc8471a, 0, 64 * 1024, 1024,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
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{ "gd55b01ge", INFO(0xc8471b, 0, 64 * 1024, 2048,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK) },
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};
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const struct spi_nor_manufacturer spi_nor_gigadevice = {
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.name = "gigadevice",
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.parts = gigadevice_parts,
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.nparts = ARRAY_SIZE(gigadevice_parts),
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};
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