luckfox-pico-sdk/sysdrv/source/uboot/u-boot/examples/standalone/README_rkspi.md
luckfox-eng29 8f34c2760d project:build.sh: Added fastboot support; custom modifications to U-Boot and kernel implemented using patches.
project:cfg:BoardConfig_IPC: Added fastboot BoardConfig file and firmware post-scripts, distinguishing between
the BoardConfigs for Luckfox Pico Pro and Luckfox Pico Max. project:app: Added fastboot_client and rk_smart_door
for quick boot applications; updated rkipc app to adapt to the latest media library. media:samples: Added more
usage examples. media:rockit: Fixed bugs; removed support for retrieving data frames from VPSS. media:isp:
Updated rkaiq library and related tools to support connection to RKISP_Tuner. sysdrv:Makefile: Added support for
compiling drv_ko on Luckfox Pico Ultra W using Ubuntu; added support for custom root filesystem.
sysdrv:tools:board: Updated Buildroot optional mirror sources, updated some software versions, and stored device
tree files and configuration files that undergo multiple modifications for U-Boot and kernel separately.
sysdrv:source:mcu: Used RISC-V MCU SDK with RT-Thread system, mainly for initializing camera AE during quick
boot. sysdrv:source:uboot: Added support for fastboot; added high baud rate DDR bin for serial firmware upgrades.
sysdrv:source:kernel: Upgraded to version 5.10.160; increased NPU frequency for RV1106G3; added support for
fastboot.

Signed-off-by: luckfox-eng29 <eng29@luckfox.com>
2024-10-14 09:47:04 +08:00

2.6 KiB

RK SPI Standalone Bin

This is the readme for the Das U-Boot standalone program rkspi

How To Use

Compile

1.Define the standalone load address in includes/configs/rkxxxxx_common.h

#define CONFIG_STANDALONE_LOAD_ADDR    0x40000000

2.Enable rkspi in defconfig

CONFIG_ROCKCHIP_SPI=y

Setting SPI hardware

1.Setting the iomux and spiclk through:

  • u-boot shell command
  • define it in rkspi.c spi_hw_init

Note:

  • spiclk is the clock for spi controller, output to IO after internal frequency division of the controller.

Load And Executable

  1. load the bin by serial or tftp, take tftp as example:
setenv ipaddr 172.16.12.157
setenv serverip 172.16.12.167
tftp 0x40000000 rkspi.bin		# 0x40000000 is define by CONFIG_STANDALONE_LOAD_ADDR
  1. execute it
go 0x40000000		# 0x40000000 is define by CONFIG_STANDALONE_LOAD_ADDR

Abort Codes

Introduction

int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode);
  • bus: spi bus
  • base_addr: spi register base address
  • rsd: read sample clock shift with spiclk which is controller working rate
  • clock_div: internal frequency division of the controller
  • mode: spi mode, support:
#define SPI_CPHA	BIT(0)			/* clock phase */
#define SPI_CPOL	BIT(1)			/* clock polarity */
#define SPI_MODE_0	(0 | 0)			/* (original MicroWire) */
#define SPI_MODE_1	(0 | SPI_CPHA)
#define SPI_MODE_2	(SPI_CPOL | 0)
#define SPI_MODE_3	(SPI_CPOL | SPI_CPHA)
int rockchip_spi_claim_bus(u8 bus);
  • bus: spi bus
void rockchip_spi_release_bus(u8 bus);
  • bus: spi bus
int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags);
  • bus: spi bus
  • cs: spi cs
  • bitlen: the transfer length in bits
  • dout: write buffer (if exits)
  • din: read buffer (if exits), if the dout and din both defined, spi work in duplex mode
  • flags: operation chip select, support:
#define SPI_XFER_BEGIN		BIT(0)	/* Assert CS before transfer */
#define SPI_XFER_END		BIT(1)	/* Deassert CS after transfer */
#define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
int rockchip_spi_write_then_read(u8 bus, u8 cs,
				 const u8 *opcode, size_t n_opcode,
				 const u8 *txbuf, u8 *rxbuf, size_t n_buf);
  • bus: spi bus
  • cs: spi cs
  • opcode: command code
  • n_opcode: the numbers of command code in bytes
  • txbuf: write buffer (if exits)
  • rxbuf: read buffer (if exits), if the dout and din both defined, spi work in duplex mode
  • n_buf: the transfer length in bytes

Demo

Is right in the main function of rkspi.